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    Searched defs:Sequence (Results 1 - 14 of 14) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/
CodeEmitter.h 42 ArrayRef<MCInst> Sequence;
56 : STI(ST), MAB(AB), MCE(CE), VecOS(Code), Sequence(S),
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
ScheduleDAGSDNodes.h 53 std::vector<SUnit*> Sequence;
111 /// in the Sequence member.
116 /// consistent with the Sequence of scheduled instructions.
120 /// according to the order specified in Sequence.
ScheduleDAGFast.cpp 187 Sequence.push_back(SU);
542 Sequence.reserve(SUnits.size());
629 std::reverse(Sequence.begin(), Sequence.end());
653 std::vector<SDNode*> Sequence;
671 Sequence.push_back(N);
757 Sequence.reserve(DAGSize);
768 unsigned NumNodes = Sequence.size();
771 SDNode *N = Sequence[NumNodes-i-1];
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/ObjCARC/
PtrState.h 10 // is only used by the ARC Sequence Dataflow computation. By separating this
37 /// \enum Sequence
39 /// A sequence of states that a pointer may go through in which an
41 enum Sequence {
51 const Sequence S) LLVM_ATTRIBUTE_UNUSED;
54 /// retain-decrement-use-release sequence or release-use-decrement-retain
55 /// reverse sequence.
78 /// For a top-down sequence, the set of objc_retains or
83 /// sequence.
110 /// The current position in the sequence
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
PostRASchedulerList.cpp 133 std::vector<SUnit*> Sequence;
239 Sequence.clear();
253 /// dumpSchedule - dump the scheduled Sequence.
255 for (unsigned i = 0, e = Sequence.size(); i != e; i++) {
256 if (SUnit *SU = Sequence[i])
331 // Schedule each sequence of instructions not interrupted by a label
501 Sequence.push_back(SU);
511 /// emitNoop - Add a noop to the current instruction sequence.
515 Sequence.push_back(nullptr); // NULL here means noop
549 Sequence.reserve(SUnits.size())
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  /src/external/apache2/llvm/dist/llvm/include/llvm/Support/
YAMLTraits.h 46 Sequence,
112 /// of bit values and the YAML representation is a flow sequence of
232 /// to/from a YAML sequence. For example:
252 // a flow sequence (e.g. [a,b,c]).
257 /// type need to be converted to/from a YAML sequence.
283 /// a scalar, map, or sequence, decided dynamically. For example:
878 // omit key/value instead of outputting empty sequence
1103 case NodeKind::Sequence:
1752 // Define non-member operator>> so that Input can stream in a sequence as
1833 // Define non-member operator<< so that Output can stream out a sequence
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  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/DWARF/
DWARFDebugLine.h 185 /// first byte after the end of a sequence of target machine
201 struct Sequence {
202 Sequence();
204 /// Sequence describes instructions at address range [LowPC, HighPC)
218 static bool orderByHighPC(const Sequence &LHS, const Sequence &RHS) {
241 void appendSequence(const DWARFDebugLine::Sequence &S) {
289 using SequenceVector = std::vector<Sequence>;
297 uint32_t findRowInSeq(const DWARFDebugLine::Sequence &Seq,
315 /// Helper to allow for parsing of an entire .debug_line section in sequence
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  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenSchedule.h 40 /// sequences. TheDef is nonnull for explicit SchedWrites, but Sequence may or
41 /// may not be empty. TheDef is null for inferred sequences, and Sequence must
45 /// or a sequence of writes on one operand.
55 IdxVec Sequence;
70 // added. Note that implicit Reads (from ReadVariant) may have a Sequence
78 HasVariants(false), IsVariadic(false), IsSequence(true), Sequence(Seq) {
79 assert(Sequence.size() > 1 && "implied sequence needs >1 RWs");
85 assert((!IsSequence || !HasVariants) && "Sequence can't have variant");
86 assert((!IsSequence || !Sequence.empty()) && "Sequence should be nonempty")
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RegisterInfoEmitter.cpp 588 // Print a BitVector as a sequence of hex numbers using a little-endian mapping.
627 // compression on regular register banks. The sequence is computed from the
639 // Differentially encode a sequence of numbers into V. The starting value and
783 SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
784 NextSIdx = SIdx + Sequence.size() + 1;
785 if (Sequence == IdxSequence) {
805 const SmallVectorImpl<MaskRolPair> &Sequence = Sequences[s];
806 for (size_t p = 0, pe = Sequence.size(); p != pe; ++p) {
807 const MaskRolPair &P = Sequence[p];
814 OS << " // Sequence " << Idx << "\n"
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  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/DWARF/
DWARFDebugLine.cpp 503 DWARFDebugLine::Sequence::Sequence() { reset(); }
505 void DWARFDebugLine::Sequence::reset() {
548 Sequence.reset();
553 if (Sequence.Empty) {
554 // Record the beginning of instruction sequence.
555 Sequence.Empty = false;
556 Sequence.LowPC = Row.Address.Address;
557 Sequence.FirstRowIndex = RowNumber;
561 // Record the end of instruction sequence
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  /src/sys/external/bsd/gnu-efi/dist/inc/
efipxebc.h 92 UINT16 Sequence;
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LoopStrengthReduce.cpp 4124 SmallVector<const SCEV *, 8> Sequence;
4130 Sequence.push_back(Reg);
4140 for (const SCEV *Reg : Sequence) {
4196 Sequence.clear();
  /src/sys/external/bsd/acpica/dist/include/
actbl1.h 497 UINT32 Sequence; /* Used to detect runtime CDAT table changes */
2237 UINT8 Sequence; /* HPET sequence number */
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 1465 // Try and match an index sequence, which we can lower directly to the vid
1487 SmallVector<SDValue> Sequence;
1492 BV->getRepeatedSequence(Sequence) &&
1493 (Sequence.size() * EltBitSize) <= 64) {
1494 unsigned SeqLen = Sequence.size();
1499 "Unexpected sequence type");
1506 for (const auto &SeqV : Sequence) {
1523 "Unexpected bitcast sequence");
1674 // length VL. It ensures the final sequence is type legal, which is useful when
2489 // Generate a sequence for accessing addresses within the first 2 GiB o
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