HomeSort by: relevance | last modified time | path
    Searched defs:ShiftAmount (Results 1 - 19 of 19) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
RISCVMatInt.cpp 66 int ShiftAmount = 12 + findFirstSet((uint64_t)Hi52);
67 Hi52 = SignExtend64(Hi52 >> (ShiftAmount - 12), 64 - ShiftAmount);
71 Res.push_back(RISCVMatInt::Inst(RISCV::SLLI, ShiftAmount));
86 unsigned ShiftAmount = countLeadingZeros((uint64_t)Val);
87 Val <<= ShiftAmount;
91 Val |= maskTrailingOnes<uint64_t>(ShiftAmount);
95 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount));
102 Val &= maskTrailingZeros<uint64_t>(ShiftAmount);
105 TmpSeq.push_back(RISCVMatInt::Inst(RISCV::SRLI, ShiftAmount));
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVRegisterInfo.cpp 307 uint32_t ShiftAmount = Log2_32(ZvlssegInfo->second);
308 if (ShiftAmount != 0)
311 .addImm(ShiftAmount);
RISCVFrameLowering.cpp 499 unsigned ShiftAmount = Log2(MaxAlignment);
504 .addImm(ShiftAmount);
507 .addImm(ShiftAmount);
RISCVInstrInfo.cpp 1374 uint32_t ShiftAmount = Log2_32(NumOfVReg);
1375 if (ShiftAmount == 0)
1379 .addImm(ShiftAmount);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsMCCodeEmitter.cpp 753 template <unsigned ShiftAmount>
764 OffBits >>= ShiftAmount;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeVectorOps.cpp 1043 SDValue ShiftAmount = DAG.getConstant(EltWidth - SrcEltWidth, DL, VT);
1045 DAG.getNode(ISD::SHL, DL, VT, Op, ShiftAmount),
1046 ShiftAmount);
LegalizeIntegerTypes.cpp 823 SDValue ShiftAmount = DAG.getConstant(SHLAmount, dl, SHVT);
825 DAG.getNode(ISD::SHL, dl, PromotedType, Op1Promoted, ShiftAmount);
828 DAG.getNode(ISD::SHL, dl, PromotedType, Op2Promoted, ShiftAmount);
832 return DAG.getNode(ShiftOp, dl, PromotedType, Result, ShiftAmount);
3489 SDValue ShiftAmount = DAG.getConstant(Scale % NVTSize, dl, ShiftTy);
3491 ShiftAmount);
3493 ShiftAmount);
TargetLowering.cpp 6336 unsigned ShiftAmount = OuterBitSize - InnerBitSize;
6338 if (APInt::getMaxValue(ShiftAmountTy.getSizeInBits()).ult(ShiftAmount)) {
6344 SDValue Shift = DAG.getConstant(ShiftAmount, dl, ShiftAmountTy);
7337 SDValue ShiftAmount =
7340 SDValue ShiftedElt = DAG.getNode(ISD::SRL, SL, LoadVT, Load, ShiftAmount);
7422 SDValue ShiftAmount =
7425 DAG.getNode(ISD::SHL, SL, IntVT, ExtElt, ShiftAmount);
7599 SDValue ShiftAmount =
7602 SDValue Result = DAG.getNode(ISD::SHL, dl, VT, Hi, ShiftAmount);
7713 SDValue ShiftAmount = DAG.getConstant
    [all...]
DAGCombiner.cpp 10765 SDValue ShiftAmount = DAG.getConstant(ShCt, DL, VT);
10768 return DAG.getNode(ShiftOpcode, DL, VT, NotX, ShiftAmount);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
AVRISelLowering.cpp 312 uint64_t ShiftAmount = cast<ConstantSDNode>(N->getOperand(1))->getZExtValue();
321 ShiftAmount = ShiftAmount % VT.getSizeInBits();
325 ShiftAmount = ShiftAmount % VT.getSizeInBits();
339 if (Op.getOpcode() == ISD::SHL && 4 <= ShiftAmount && ShiftAmount < 7) {
340 // Optimize LSL when 4 <= ShiftAmount <= 6.
344 ShiftAmount -= 4;
345 } else if (Op.getOpcode() == ISD::SRL && 4 <= ShiftAmount &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstCombineIntrinsic.cpp 1004 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros();
1009 ShiftAmount));
1049 unsigned ShiftAmount = MaskC->getValue().countTrailingZeros();
1053 ShiftAmount));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonISelDAGToDAG.cpp 1857 uint64_t ShiftAmount = V.getConstantOperandVal(1);
1858 if (ShiftAmount == Power)
1860 Ops[1] = CurDAG->getConstant(ShiftAmount - Power,
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCasts.cpp 498 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0;
500 if ((VecWidth % DestWidth != 0) || (ShiftAmount % DestWidth != 0))
511 unsigned Elt = ShiftAmount / DestWidth;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/AsmParser/
AArch64AsmParser.cpp 391 unsigned ShiftAmount;
545 return ShiftedImm.ShiftAmount;
838 unsigned Shift = ShiftedImm.ShiftAmount;
1884 unsigned ShiftAmount = 0,
1892 Op->Reg.ShiftExtend.Amount = ShiftAmount;
1903 unsigned ShiftAmount = 0,
1908 auto Op = CreateReg(RegNum, Kind, S, E, Ctx, EqualsReg, ExtTy, ShiftAmount,
1948 unsigned ShiftAmount,
1953 Op->ShiftedImm.ShiftAmount = ShiftAmount;
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 5274 SDValue ShiftAmount = DAG.getTargetConstant(WidthM1 + 1, DL, MVT::i32);
5275 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/
ARMAsmParser.cpp 460 unsigned &ShiftAmount);
5255 const MCExpr *ShiftAmount;
5258 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5262 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5338 const MCExpr *ShiftAmount;
5340 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5344 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
5400 const MCExpr *ShiftAmount;
5402 if (getParser().parseExpression(ShiftAmount, EndLoc)) {
5406 const MCConstantExpr *CE = dyn_cast<MCConstantExpr>(ShiftAmount);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/
MipsAsmParser.cpp 1338 template <unsigned Bits, unsigned ShiftAmount = 0>
1346 isShiftedInt<Bits, ShiftAmount>(getConstantMemOff())))
1350 return IsReloc && isShiftedInt<Bits, ShiftAmount>(Res.getConstant());
2814 unsigned ShiftAmount = FirstSet - (15 - (LastSet - FirstSet));
2815 uint16_t Bits = (ImmValue >> ShiftAmount) & 0xffff;
2817 TOut.emitRRI(Mips::DSLL, TmpReg, TmpReg, ShiftAmount, IDLoc, STI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 10963 uint64_t ShiftAmount = Base.getOperand(1).getConstantOperandVal(1);
10965 if (ShiftAmount == Log2_32(LoadBytes))
12539 static bool findEXTRHalf(SDValue N, SDValue &Src, uint32_t &ShiftAmount,
12551 ShiftAmount = N->getConstantOperandVal(1);
12927 uint64_t ShiftAmount = Shift.getConstantOperandVal(1);
12928 if (ShiftAmount != 1)
13576 int64_t ShiftAmount;
13586 ShiftAmount = SplatValue.getSExtValue();
13588 ShiftAmount = CVN->getSExtValue();
13627 if (IsRightShift && ShiftAmount <= -1 && ShiftAmount >= -(int)ElemBits)
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMISelLowering.cpp 16883 unsigned ShiftAmount = TrueConst->logBase2();
16884 if (ShiftAmount)
16889 if (ShiftAmount)
16891 DAG.getConstant(ShiftAmount, dl, MVT::i32));

Completed in 144 milliseconds