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    Searched defs:ShiftVal (Results 1 - 15 of 15) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64MCCodeEmitter.cpp 267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm());
268 assert((ShiftVal == 0 || ShiftVal == 12) &&
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal));
288 ShiftVal = 12;
290 return ShiftVal == 0 ? 0 : (1 << ShiftVal);
528 unsigned ShiftVal = AArch64_AM::getShiftValue(ShiftOpnd);
529 assert((ShiftVal == 0 || ShiftVal == 8) &
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AArch64InstPrinter.cpp 1009 unsigned ShiftVal = AArch64_AM::getArithShiftValue(Val);
1021 if (ShiftVal != 0)
1022 O << ", lsl #" << ShiftVal;
1027 if (ShiftVal != 0)
1028 O << " #" << ShiftVal;
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMParallelDSP.cpp 792 Value *ShiftVal = ConstantInt::get(LoadTy, OffsetTy->getBitWidth());
793 Value *Top = IRB.CreateLShr(WideLoad, ShiftVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64InstrInfo.cpp 895 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
896 if (ShiftVal == 0)
898 return AArch64_AM::getShiftType(Imm) == AArch64_AM::LSL && ShiftVal <= 5;
922 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
923 return ShiftVal == 0 ||
924 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 31);
930 unsigned ShiftVal = AArch64_AM::getShiftValue(Imm);
931 return ShiftVal == 0 ||
932 (AArch64_AM::getShiftType(Imm) == AArch64_AM::ASR && ShiftVal == 63);
AArch64FastISel.cpp 1234 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1239 ShiftVal, SetFlags, WantResult);
1256 uint64_t ShiftVal = C->getZExtValue();
1262 ShiftVal, SetFlags, WantResult);
1603 uint64_t ShiftVal = cast<ConstantInt>(MulRHS)->getValue().logBase2();
1608 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
1618 uint64_t ShiftVal = C->getZExtValue();
1622 ResultReg = emitLogicalOp_rs(ISDOpc, RetVT, LHSReg, RHSReg, ShiftVal);
4577 uint64_t ShiftVal = C->getValue().logBase2();
4605 emitLSL_ri(VT, SrcVT, Src0Reg, ShiftVal, IsZExt)
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AArch64ISelDAGToDAG.cpp 481 unsigned ShiftVal = CSD->getZExtValue();
482 if (ShiftVal > 3)
767 unsigned ShiftVal = 0;
774 ShiftVal = CSD->getZExtValue();
775 if (ShiftVal > 4)
803 Shift = CurDAG->getTargetConstant(getArithExtendImm(Ext, ShiftVal), SDLoc(N),
1017 unsigned ShiftVal = CSD->getZExtValue();
1019 if (ShiftVal != 0 && ShiftVal != LegalShiftVal)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsFastISel.cpp 1990 uint64_t ShiftVal = C->getZExtValue();
2006 emitInst(Opcode, ResultReg).addReg(Op0Reg).addImm(ShiftVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 2010 auto ShiftVal = DAG.getSplatValue(Op.getOperand(1));
2011 if (!ShiftVal)
2015 ShiftVal = DAG.getAnyExtOrTrunc(ShiftVal, DL, MVT::i32);
2032 return DAG.getNode(Opcode, DL, Op.getValueType(), Op.getOperand(0), ShiftVal);
  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
ValueTracking.cpp 2408 auto ShiftVal = Shift->getLimitedValue(BitWidth - 1);
2410 if (Known.countMaxLeadingZeros() < BitWidth - ShiftVal)
2413 if (Known.countMinTrailingZeros() >= ShiftVal)
  /src/external/apache2/llvm/dist/llvm/lib/IR/
AutoUpgrade.cpp 1159 unsigned ShiftVal = cast<llvm::ConstantInt>(Shift)->getZExtValue();
1168 ShiftVal &= (NumElts - 1);
1172 if (ShiftVal >= 32)
1177 if (ShiftVal > 16) {
1178 ShiftVal -= 16;
1187 unsigned Idx = ShiftVal + i;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUISelDAGToDAG.cpp 2170 uint32_t ShiftVal = Shift->getZExtValue();
2177 Srl.getOperand(0), ShiftVal, WidthVal));
2192 uint32_t ShiftVal = Shift->getZExtValue();
2193 uint32_t MaskVal = Mask->getZExtValue() >> ShiftVal;
2199 And.getOperand(0), ShiftVal, WidthVal));
AMDGPUISelLowering.cpp 4058 SDValue ShiftVal = DAG.getConstant(OffsetVal, DL, MVT::i32);
4060 BitsFrom, ShiftVal);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/
InstCombineCasts.cpp 488 ConstantInt *ShiftVal = nullptr;
491 m_ConstantInt(ShiftVal)))) ||
498 unsigned ShiftAmount = ShiftVal ? ShiftVal->getZExtValue() : 0;
InstCombineCompares.cpp 2050 const APInt *ShiftVal;
2051 if (Cmp.isEquality() && match(Shl->getOperand(0), m_APInt(ShiftVal)))
2052 return foldICmpShlConstConst(Cmp, Shl->getOperand(1), C, *ShiftVal);
2198 const APInt *ShiftVal;
2199 if (Cmp.isEquality() && match(Shr->getOperand(0), m_APInt(ShiftVal)))
2200 return foldICmpShrConstConst(Cmp, Shr->getOperand(1), C, *ShiftVal);
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZISelLowering.cpp 2322 // Store it in ShiftVal if so.
2323 static bool isSimpleShift(SDValue N, unsigned &ShiftVal) {
2332 ShiftVal = Amount;
2481 unsigned NewCCMask, ShiftVal;
2484 isSimpleShift(NewC.Op0, ShiftVal) &&
2485 (MaskVal >> ShiftVal != 0) &&
2486 ((CmpVal >> ShiftVal) << ShiftVal) == CmpVal &&
2488 MaskVal >> ShiftVal,
2489 CmpVal >> ShiftVal,
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