| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonOptimizeSZextends.cpp | 101 // %sext233 = shl i32 %34, 16
116 Instruction *Shl = dyn_cast<Instruction>(Ashr->getOperand(0));
117 if (!(Shl && Shl->getOpcode() == Instruction::Shl))
119 Value *Intr = Shl->getOperand(0);
120 Value *ShlOp1 = Shl->getOperand(1);
126 // The first operand of Shl comes from an intrinsic.
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUInstCombineIntrinsic.cpp | 451 Value *Shl = IC.Builder.CreateShl(Src, IntSize - Offset - Width);
452 Value *RightShift = Signed ? IC.Builder.CreateAShr(Shl, IntSize - Width)
453 : IC.Builder.CreateLShr(Shl, IntSize - Width);
|
| AMDGPUISelDAGToDAG.cpp | 2139 const SDValue &Shl = N->getOperand(0);
2140 ConstantSDNode *B = dyn_cast<ConstantSDNode>(Shl->getOperand(1));
2151 ReplaceNode(N, getS_BFE(Opcode, SDLoc(N), Shl.getOperand(0), CVal - BVal,
2203 } else if (N->getOperand(0).getOpcode() == ISD::SHL) {
2209 if (N->getOperand(0).getOpcode() == ISD::SHL) {
|
| AMDGPUISelLowering.cpp | 428 setOperationAction(ISD::SHL, VT, Expand);
549 setTargetDAGCombine(ISD::SHL);
1962 REM = DAG.getNode(ISD::SHL, DL, VT, REM, DAG.getConstant(1, DL, VT));
2449 DAG.getNode(ISD::SHL, SL, MVT::i64, L, LZ),
2459 DAG.getNode(ISD::SHL, SL, MVT::i32, E, DAG.getConstant(23, SL, MVT::i32)),
2667 DAG.getNode(ISD::SHL, DL, MVT::i32, E,
2681 SDValue D0 = DAG.getNode(ISD::SHL, DL, MVT::i32, D, B);
2826 uint32_t Shl = static_cast<uint32_t>(Src0) << (32 - Offset - Width);
2827 IntTy Result = static_cast<IntTy>(Shl) >> (32 - Width);
3074 // (shl ([asz]ext i16:x), 16 -> build_vector 0,
[all...] |
| SIISelLowering.cpp | 668 setOperationAction(ISD::SHL, MVT::v2i16, Legal);
696 setOperationAction(ISD::SHL, MVT::v4i16, Custom);
2796 Y = DAG.getNode(ISD::SHL, SL, MVT::i32, Y,
2804 Z = DAG.getNode(ISD::SHL, SL, MVT::i32, Z,
3294 ISD::SHL, dl, VT, Size,
4533 case ISD::SHL:
5146 SDValue Result = DAG.getNode(ISD::SHL, SL, VT, LHS, ShiftAmt);
5275 return DAG.getNode(ISD::SHL, DL, MVT::i32, ApertureReg, ShiftAmount);
5442 // v_bfi_b32 (v_bfm_b32 16, (shl idx, 16)), val, vec
5453 SDValue ScaledIdx = DAG.getNode(ISD::SHL, SL, MVT::i32, Idx, ScaleFactor)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineMulDivRem.cpp | 85 if (I->getOpcode() == Instruction::Shl && !I->hasNoUnsignedWrap()) {
176 Constant *Shl = ConstantExpr::getShl(C1, C2);
178 BinaryOperator *BO = BinaryOperator::CreateMul(NewOp, Shl);
182 Shl->isNotMinSignedValue())
190 BinaryOperator *Shl = BinaryOperator::CreateShl(NewOp, NewCst);
193 Shl->setHasNoUnsignedWrap();
197 Shl->setHasNoSignedWrap();
200 return Shl;
|
| InstCombineAddSub.cpp | 977 // add (ashr (shl i32 X, 31), 31), 1 --> and (not X), 1
1108 /// than an 'add'. The new shl is always nsw, and is nuw if old `and` was.
1319 auto *Shl = BinaryOperator::CreateShl(LHS, ConstantInt::get(Ty, 1));
1320 Shl->setHasNoSignedWrap(I.hasNoSignedWrap());
1321 Shl->setHasNoUnsignedWrap(I.hasNoUnsignedWrap());
1322 return Shl;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86ISelDAGToDAG.cpp | 662 // BTS: (or X, (shl 1, n))
664 // BTC: (xor X, (shl 1, n))
666 if (U->getOperand(0).getOpcode() == ISD::SHL &&
670 if (U->getOperand(1).getOpcode() == ISD::SHL &&
692 case ISD::SHL:
1017 case ISD::SHL:
1028 case ISD::SHL: NewOpc = X86ISD::VSHLV; break;
1857 SDValue Shl = DAG.getNode(ISD::SHL, DL, VT, And, ShlCount);
1869 insertDAGNode(DAG, N, Shl);
[all...] |
| /src/external/apache2/llvm/dist/llvm/bindings/go/llvm/ |
| ir.go | 155 Shl Opcode = C.LLVMShl
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| SystemZISelLowering.cpp | 386 setOperationAction(ISD::SHL, VT, Custom);
2271 // Check whether C compares (shl X, 32) with 0 and whether X is
2276 // with (sext (trunc X)) into a comparison with (shl X, 32).
2278 // Check for a comparison between (shl X, 32) and 0.
2279 if (C.Op0.getOpcode() == ISD::SHL &&
2483 NewC.Op0.getOpcode() == ISD::SHL &&
3135 SDValue TPHiShifted = DAG.getNode(ISD::SHL, DL, PtrVT, TPHi,
3350 In64 = DAG.getNode(ISD::SHL, DL, MVT::i64, In64,
3832 SDValue Tmp = DAG.getNode(ISD::SHL, DL, VT, Op, DAG.getConstant(I, DL, VT));
3926 SDValue BitShift = DAG.getNode(ISD::SHL, DL, PtrVT, Addr
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/ |
| SimplifyCFG.cpp | 6230 auto *Shl = Builder.CreateShl(Sub, Ty->getBitWidth() - Shift);
6231 auto *Rot = Builder.CreateOr(LShr, Shl);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| LegalizerHelper.cpp | 1374 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
1375 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
1795 // 2. SHL by M-N
1796 // 3. [US][ADD|SUB|SHL]SAT
2740 // v4 = i32 shl v3, 16
5426 // fshr X, Y, Z -> fshl (fshl X, Y, 1), (shl Y, 1), ~Z
5811 auto Shl = MIRBuilder.buildShl(DstTy, R, SubExponent);
5818 R = MIRBuilder.buildSelect(DstTy, CmpGt, Shl, Srl);
6171 auto Shl = MIRBuilder.buildShl(WideTy, ZextInput, ShiftAmt);
6172 MIRBuilder.buildOr(NextResult, ResultReg, Shl);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCISelLowering.cpp | 685 // BUILD_PAIR can't be handled natively, and should be expanded to shl/or
1006 setOperationAction(ISD::SHL, MVT::v2i64, Legal);
1010 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1014 setOperationAction(ISD::SHL, MVT::v1i128, Expand);
1021 setOperationAction(ISD::SHL, MVT::v2i64, Expand);
1144 // 128 bit shifts can be accomplished via 3 instructions for SHL and
1147 setOperationAction(ISD::SHL, MVT::v1i128, Legal);
1304 setTargetDAGCombine(ISD::SHL);
1612 case PPCISD::SHL: return "PPCISD::SHL";
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| DAGCombiner.cpp | 1649 case ISD::SHL: return visitSHL(N);
1776 case ISD::SHL:
2640 // fold (add x, shl(0 - y, n)) -> sub(x, shl(y, n))
2641 if (N1.getOpcode() == ISD::SHL && N1.getOperand(0).getOpcode() == ISD::SUB &&
2644 DAG.getNode(ISD::SHL, DL, VT,
3813 return DAG.getNode(ISD::SHL, DL, VT, N0, Trunc);
3824 DAG.getNode(ISD::SHL, DL, VT, N0,
3831 // mul x, (2^N + 1) --> add (shl x, N), x
3832 // mul x, (2^N - 1) --> sub (shl x, N),
[all...] |
