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    Searched defs:Slots (Results 1 - 12 of 12) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/DebugInfo/CodeView/
TypeRecordMapping.cpp 481 ArrayRef<VFTableSlotKind> Slots = Record.getSlots();
482 Size = Slots.size();
485 for (size_t SlotIndex = 0; SlotIndex < Slots.size(); SlotIndex += 2) {
486 uint8_t Byte = static_cast<uint8_t>(Slots[SlotIndex]) << 4;
487 if ((SlotIndex + 1) < Slots.size()) {
488 Byte |= static_cast<uint8_t>(Slots[SlotIndex + 1]);
497 Record.Slots.push_back(static_cast<VFTableSlotKind>(Byte & 0xF));
499 Record.Slots.push_back(static_cast<VFTableSlotKind>(Byte >> 4));
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
HexagonShuffler.h 38 // Mask of the slots or units that may execute the insn and
40 unsigned Slots, Weight;
46 Slots = s & ((1u << HEXAGON_PACKET_SIZE) - 1);
55 unsigned getUnits() const { return (Slots); }
75 // Available HVX slots.
85 // Count of adjacent slots that the insn requires to be executed.
130 // Check if the handles are in ascending order by core slots.
135 // Check if the handles are in ascending order by HVX slots.
HexagonMCInstrInfo.cpp 152 Check->reportError("invalid instruction packet: out of slots");
442 /// Return the slots this instruction can execute out of
451 /// Return the slots this instruction consumes in addition to
459 unsigned Slots = 0;
461 // FirstStage are slots that this instruction can execute in.
462 // FirstStage+1 are slots that are also consumed by this instruction.
470 Slots |= Units;
473 // if 0 is returned, then no additional slots are consumed by this inst.
474 return Slots;
  /src/external/apache2/llvm/dist/llvm/include/llvm/AsmParser/
LLParser.h 94 SlotMapping *Slots;
165 SlotMapping *Slots = nullptr)
167 Slots(Slots), BlockAddressPFS(nullptr) {}
172 bool parseStandaloneConstantValue(Constant *&C, const SlotMapping *Slots);
175 const SlotMapping *Slots);
185 void restoreParsingState(const SlotMapping *Slots);
  /src/external/apache2/llvm/dist/llvm/include/llvm/IR/
Value.h 899 Use *Slots[MaxSlots];
905 Slots[0] = UseList;
918 if (!Slots[I])
923 // Since the uses in Slots[I] originally preceded those in Current, send
924 // Slots[I] in as the left parameter to maintain a stable sort.
925 Current = mergeUseLists(Slots[I], Current, Cmp);
926 Slots[I] = nullptr;
935 Slots[I] = Current;
943 if (Slots[I])
944 // Since the uses in Slots[I] originally preceded those in UseList, sen
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
FixupStatepointCallerSaved.cpp 20 /// statepoint operands to added spill slots.
41 STATISTIC(NumSpillSlotsAllocated, "Number of spill slots allocated");
42 STATISTIC(NumSpillSlotsExtended, "Number of spill slots extended");
199 // extends the size of spill slots to reduce the number of them, causing
205 SmallVector<int, 8> Slots;
217 // Keeps track of slots reserved for the shared landing pad processing.
238 // the exception of slots reserved for landing pad processing (if any).
269 while (Line.Index < Line.Slots.size()) {
270 int FI = Line.Slots[Line.Index++];
284 Line.Slots.push_back(FI)
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LiveIntervals.cpp 916 ArrayRef<SlotIndex> Slots;
919 Slots = getRegMaskSlotsInBlock(MBB->getNumber());
922 Slots = getRegMaskSlots();
926 // We are going to enumerate all the register mask slots contained in LI.
928 ArrayRef<SlotIndex>::iterator SlotI = llvm::lower_bound(Slots, LiveI->start);
929 ArrayRef<SlotIndex>::iterator SlotE = Slots.end();
931 // No slots in range, LI begins after the last call.
949 // Loop over all slots overlapping this segment.
952 unionBitMask(SlotI - Slots.begin());
960 unionBitMask(SlotI++ - Slots.begin())
    [all...]
LiveDebugVariables.cpp 16 // are moved between registers and stack slots. Finally emit new DBG_VALUE
1729 auto Slots = LIS->getSlotIndexes();
1733 auto *MBB = Slots->getMBBFromIndex(Idx);
MachinePipeliner.cpp 387 SlotIndexes &Slots = *getAnalysis<LiveIntervals>().getSlotIndexes();
408 Slots.insertMachineInstrInMaps(*Copy);
RegisterCoalescer.cpp 3582 const SlotIndexes &Slots = *LIS->getSlotIndexes();
3602 SlotIndex CurrentSlot = Slots.getMBBStartIdx(&MBB);
3611 CurrentSlot = Slots.getInstructionIndex(MI);
3617 CloseNewDVRange(Slots.getMBBEndIdx(&MBB));
  /src/external/apache2/llvm/dist/llvm/include/llvm/DebugInfo/CodeView/
TypeRecord.h 556 explicit VFTableShapeRecord(ArrayRef<VFTableSlotKind> Slots)
557 : TypeRecord(TypeRecordKind::VFTableShape), SlotsRef(Slots) {}
558 explicit VFTableShapeRecord(std::vector<VFTableSlotKind> Slots)
559 : TypeRecord(TypeRecordKind::VFTableShape), Slots(std::move(Slots)) {}
564 return Slots;
570 std::vector<VFTableSlotKind> Slots;
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ISelLowering.cpp 1720 SDValue Slots[4];
1729 Slots[i] = DAG.getNode(AMDGPUISD::CONST_ADDRESS, DL, MVT::i32, NewPtr);
1737 SDValue Result = DAG.getBuildVector(NewVT, DL, makeArrayRef(Slots, NumElements));

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