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    Searched defs:Spill (Results 1 - 6 of 6) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
RegAllocBasic.cpp 56 /// algorithm. It prioritizes live virtual registers by spill weight and spills
206 // Spill or split all live virtual registers currently unified under PhysReg
230 // Spill each interfering vreg allocated to PhysReg or an alias.
232 LiveInterval &Spill = *Intfs[i];
235 if (!VRM->hasPhys(Spill.reg()))
240 Matrix->unassign(Spill);
242 // Spill the extracted interval.
243 LiveRangeEdit LRE(&Spill, SplitVRegs, *MF, *LIS, VRM, this, &DeadRemats);
244 spiller().spill(LRE);
263 // Populate a list of physical register spill candidates
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InlineSpiller.cpp 77 static cl::opt<bool> DisableHoisting("disable-spill-hoist", cl::Hidden,
78 cl::desc("Disable inline spill hoisting"));
115 /// siblings. To hoist a spill to another BB, we need to find out a live
116 /// sibling there and use it as the source of the new spill.
152 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
154 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
172 // Variables that are valid during spill(), but used by multiple methods.
178 // All registers to spill to StackSlot, including the main register.
212 void spill(LiveRangeEdit &) override;
256 // When spilling a virtual register, we also spill any snippets it is connecte
1182 void InlineSpiller::spill(LiveRangeEdit &edit) { function in class:InlineSpiller
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  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
FunctionLoweringInfo.h 101 Spill,
144 /// used to spill values at a statepoint. We store them here to enable
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIMachineFunctionInfo.cpp 293 assert(Size >= 4 && "invalid sgpr spill size");
296 // Make sure to handle the case where a wide SGPR spill may span between two
306 // 2. All spill lanes of reserved VGPR(s) are full and another spill lane is
315 // partially spill the SGPR to VGPRs.
371 auto &Spill = VGPRToAGPRSpills[FI];
374 if (!Spill.Lanes.empty())
375 return Spill.FullyAllocated;
379 Spill.Lanes.resize(NumLanes, AMDGPU::NoRegister);
387 Spill.FullyAllocated = true
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SIFrameLowering.cpp 73 llvm_unreachable("allocate SGPR spill should have worked");
77 LLVM_DEBUG(auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
79 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane
93 // 3: There's no free lane to spill, and no free register to save FP/BP,
94 // so we're forced to spill another VGPR to use for the spill.
98 auto Spill = MFI->getSGPRToVGPRSpills(NewFI).front();
99 dbgs() << (IsFP ? "FP" : "BP") << " requires fallback spill to "
100 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';)
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SIRegisterInfo.cpp 31 "amdgpu-spill-sgpr-to-vgpr",
48 // A temporary struct to spill SGPRs.
49 // This is mostly to spill SGPRs to memory. Spilling SGPRs into VGPR lanes emits
61 // - Spill/Restore SGPRs using TmpVGPR
89 // Temporary spill slot to save TmpVGPR to.
91 // If TmpVGPR is live before the spill or if it is scavenged.
132 assert(SuperReg != AMDGPU::M0 && "m0 should never spill");
134 SuperReg != AMDGPU::EXEC && "exec should never spill");
165 assert(RS && "Cannot spill SGPR to memory without RegScavenger");
172 // need to spill inactive lanes
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