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    Searched defs:SpillSize (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
InfoByHwMode.h 150 unsigned SpillSize;
157 return std::tie(RegSize, SpillSize, SpillAlignment) ==
158 std::tie(I.RegSize, I.SpillSize, I.SpillAlignment);
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
TargetRegisterInfo.h 236 unsigned RegSize, SpillSize, SpillAlignment;
281 return getRegClassInfo(RC).SpillSize / 8;
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
StatepointLowering.cpp 111 unsigned SpillSize = ValueType.getStoreSize();
112 assert((SpillSize * 8) ==
130 if (MFI.getObjectSize(FI) == SpillSize) {
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveDebugVariables.cpp 1435 unsigned SpillSize;
1438 bool Success = TII.getStackSlotRange(TRC, Loc.getSubReg(), SpillSize,
TargetInstrInfo.cpp 534 unsigned SpillSize;
540 TII.getStackSlotRange(RC, MO.getSubReg(), SpillSize, SpillOffset, MF);
544 MIB.addImm(SpillSize);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFrameLowering.cpp 2030 const uint64_t SpillSize = 4; // Condition register is always 4 bytes.
2034 MFI.CreateFixedObject(SpillSize, SpillOffset,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 6212 unsigned SpillSize = STI.getRegisterInfo()->getSpillSize(*RC);
6213 assert((SpillSize == 64 || STI.hasVLX()) &&
6219 switch (SpillSize) {
6227 switch (SpillSize) {
6235 switch (SpillSize) {
6243 switch (SpillSize) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIInstrInfo.cpp 1420 unsigned SpillSize = TRI->getSpillSize(*RC);
1430 const MCInstrDesc &OpDesc = get(getSGPRSpillSaveOpcode(SpillSize));
1434 if (SrcReg.isVirtual() && SpillSize == 4) {
1450 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillSaveOpcode(SpillSize)
1451 : getVGPRSpillSaveOpcode(SpillSize);
1546 unsigned SpillSize = TRI->getSpillSize(*RC);
1563 const MCInstrDesc &OpDesc = get(getSGPRSpillRestoreOpcode(SpillSize));
1564 if (DestReg.isVirtual() && SpillSize == 4) {
1579 unsigned Opcode = RI.hasAGPRs(RC) ? getAGPRSpillRestoreOpcode(SpillSize)
1580 : getVGPRSpillRestoreOpcode(SpillSize);
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