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    Searched defs:Splat (Results 1 - 10 of 10) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64GlobalISelUtils.cpp 23 if (auto Splat = getVectorSplat(MI, MRI))
24 return Splat;
37 auto Splat = getAArch64VectorSplat(MI, MRI);
38 if (!Splat || Splat->isReg())
40 return Splat->getCst();
AArch64PostLegalizerLowering.cpp 307 // Try to match a vector splat operation into a dup instruction.
315 // %splat:fpr(<2 x s64>) = G_SHUFFLE_VECTOR %ins(<2 x s64>), %undef, %zerovec(<2 x s32>)
318 // %splat = G_DUP %scalar
363 // If this is undef splat, generate it via "just" vdup, if possible.
723 auto Splat = getAArch64VectorSplat(MI, MRI);
724 if (!Splat)
726 if (Splat->isReg())
731 int64_t Cst = Splat->getCst();
926 auto Splat = getAArch64VectorSplat(*MRI.getVRegDef(RHS), MRI);
929 bool IsZero = Splat && Splat->isCst() && Splat->getCst() == 0
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
ARMAddressingModes.h 321 // If 'Arg' is an 8-bit splat, then get the encoded value.
322 int Splat = getT2SOImmValSplatVal(Arg);
323 if (Splat != -1)
324 return Splat;
343 // Passing values can be any combination of splat values and shifter
344 // values. If this can be handled with a single shifter or splat, bail
355 // Likewise, try masking out a splat value first.
376 // Try masking out a splat value first.
380 // The other splat is all that's left as an option.
613 // Encode NEON 16 bits Splat immediate for instructions like VBIC/VOR
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  /src/external/apache2/llvm/dist/llvm/lib/Analysis/
TargetTransformInfo.cpp 676 const Value *Splat = getSplatValue(V);
678 // Check for a splat of a constant or for a non uniform vector of constants
682 if (Splat) {
684 if (auto *CI = dyn_cast<ConstantInt>(Splat))
699 // Check for a splat of a uniform value. This is not loop aware, so return
701 if (Splat && (isa<Argument>(Splat) || isa<GlobalValue>(Splat)))
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
LowerMatrixIntrinsics.cpp 1061 Value *Splat = Builder.CreateVectorSplat(BlockSize, RH, "splat");
1062 Sum = createMulAdd(isSumZero && K == 0 ? nullptr : Sum, L, Splat,
1088 Value *Splat = Builder.CreateVectorSplat(BlockSize, LH, "splat");
1089 Sum = createMulAdd(isSumZero && K == 0 ? nullptr : Sum, Splat, R,
RewriteStatepointsForGC.cpp 2865 auto *Splat = B.CreateVectorSplat(VF, I.getOperand(0));
2866 I.setOperand(0, Splat);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
SLPVectorizer.cpp 911 Splat, ///< Matching the same instruction multiple times (broadcast)
966 /// Identical instructions (a.k.a. splat or broadcast).
1116 // or if they are SPLAT,
1240 case ReorderingMode::Splat:
1424 ReorderingModes[OpIdx] = ReorderingMode::Splat;
1431 // Our best hope is a Splat. It may save some cost in some cases.
1432 ReorderingModes[OpIdx] = ReorderingMode::Splat;
1496 case ReorderingMode::Splat:
1497 return "Splat";
2528 OS << "<splat> " << *Entry->Scalars[0]
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  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 1333 SDValue Splat = DAG.getNode(Opc, DL, ContainerVT, Op.getOperand(0), VL);
1334 return convertFromScalableVector(VT, Splat, DAG, Subtarget);
1440 if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue()) {
1441 // For a splat, perform a scalar truncate before creating the wider
1443 assert(Splat.getValueType() == XLenVT &&
1444 "Unexpected type for i1 splat value");
1445 Splat = DAG.getNode(ISD::AND, DL, XLenVT, Splat,
1447 WideVec = DAG.getSplatBuildVector(WideVecVT, DL, Splat);
1458 if (SDValue Splat = cast<BuildVectorSDNode>(Op)->getSplatValue())
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 2089 /// specifies a splat of a single element that is suitable for input to
2090 /// one of the splat operations (VSPLTB/VSPLTH/VSPLTW/XXSPLTW/LXVDSX/etc.).
2100 // This is a splat operation if each element of the permute is the same, and
2386 /// getSplatIdxForPPCMnemonics - Return the splat index as a value that is
2406 // If ByteSize of the splat is bigger than the element size of the
2407 // build_vector, then we have a case where we are checking for a splat where
2409 // logical element of the splat (e.g. "vsplish 1" to splat {0,1}*8).
2481 // If the splat value is larger than the element value, then we can never do
2482 // this splat. The only case that we could fit the replicated bits into ou
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelLowering.cpp 4160 SDValue Splat = Index.getOperand(1);
4161 if (Splat.getOpcode() != ISD::SPLAT_VECTOR)
4163 ConstantSDNode *Mask = dyn_cast<ConstantSDNode>(Splat.getOperand(0));
4176 // getelementptr nullptr, <vscale x N x T> (splat(%offset)) + %indices)
4179 // getelementptr nullptr, <vscale x N x T> (splat(#x)) + %indices)
9024 // If this is undef splat, generate it via "just" vdup, if possible.
9181 // Extend input splat value where needed to fit into a GPR (32b or 64b only)
9665 // operands already. Otherwise, if Op is a floating-point splat
9754 // we can splat the constant value into the whole vector then fill
9939 // Firstly, try to materialize the splat constant
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