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  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonPeephole.cpp 155 MachineOperand &Src1 = MI.getOperand(1);
157 if (Src1.getImm() != 0)
172 MachineOperand &Src1 = MI.getOperand(1);
177 Register SrcReg = Src1.getReg();
HexagonGenMux.cpp 134 unsigned getMuxOpcode(const MachineOperand &Src1,
208 unsigned HexagonGenMux::getMuxOpcode(const MachineOperand &Src1,
210 bool IsReg1 = Src1.isReg(), IsReg2 = Src2.isReg();
305 MachineOperand *Src1 = &Def1.getOperand(2), *Src2 = &Def2.getOperand(2);
306 Register SR1 = Src1->isReg() ? Src1->getReg() : Register();
323 MachineOperand *SrcT = (MinX == CI.TrueX) ? Src1 : Src2;
324 MachineOperand *SrcF = (MinX == CI.FalseX) ? Src1 : Src2;
HexagonConstPropagation.cpp 1300 // X <= 0 and Src1 < 0 => cannot compare
1873 bool evaluateHexCompare2(uint32_t Cmp, const MachineOperand &Src1,
2573 // Classic compare: Dst0 = CMP Src1, Src2
2582 const MachineOperand &Src1 = MI.getOperand(1);
2587 bool Computed = evaluateHexCompare2(Opc, Src1, Src2, Inputs, Result);
2605 const MachineOperand &Src1, const MachineOperand &Src2,
2608 bool Reg1 = Src1.isReg(), Reg2 = Src2.isReg();
2609 bool Imm1 = Src1.isImm(), Imm2 = Src2.isImm();
2611 RegisterSubReg R1(Src1);
2620 APInt A1 = getCmpImm(Opc, 1, Src1);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64AdvSIMDScalarPass.cpp 299 unsigned Src1 = 0, SubReg1;
328 Src1 = MOSrc1->getReg();
347 if (!Src1) {
349 Src1 = MRI->createVirtualRegister(&AArch64::FPR64RegClass);
350 insertCopy(TII, MI, Src1, OrigSrc1, KillSrc1);
364 .addReg(Src1, getKillRegState(KillSrc1), SubReg1);
AArch64FastISel.cpp 4569 const Value *Src1 = I->getOperand(1);
4572 std::swap(Src0, Src1);
4575 if (const auto *C = dyn_cast<ConstantInt>(Src1))
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 53 Register Src1 = MI.getOperand(1).getReg();
63 auto *FAddMI = getOpcodeDef(TargetOpcode::G_FADD, Src1, MRI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
R600ExpandSpecialInstrs.cpp 112 R600::ZERO); // src1
149 Register Src1 =
150 BMI->getOperand(TII->getOperandIdx(Opcode, R600::OpName::src1))
153 (void) Src1;
155 (TRI.getEncodingValue(Src1) & 0xff) < 127)
156 assert(TRI.getHWRegChan(Src0) == TRI.getHWRegChan(Src1));
200 unsigned Src1 = 0;
204 int Src1Idx = TII->getOperandIdx(MI, R600::OpName::src1);
206 Src1 = MI.getOperand(Src1Idx).getReg();
212 Src1 = TRI.getSubReg(Src1, SubRegIndex)
    [all...]
SIOptimizeExecMasking.cpp 105 const MachineOperand &Src1 = MI.getOperand(1);
106 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
121 const MachineOperand &Src1 = MI.getOperand(1);
122 if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC_LO)
429 MachineOperand &Src1 = SaveExecInst->getOperand(2);
434 OtherOp = &Src1;
435 } else if (Src1.isReg() && Src1.getReg() == CopyFromExec)
    [all...]
GCNDPPCombine.cpp 15 // $res = VALU $dpp_value [, src1]
19 // $res = VALU_DPP $combined_old, $vgpr_to_be_read_from_other_lane, [src1,]
32 // -> $combined_old = src1,
261 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) {
262 if (!TII->isOperandLegal(*DPPInst.getInstr(), NumOperands, Src1)) {
263 LLVM_DEBUG(dbgs() << " failed: src1 is illegal\n");
267 DPPInst.add(*Src1);
352 auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1);
    [all...]
SIPeepholeSDWA.cpp 312 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) {
349 // If this is not src0 then it could be src1
350 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
545 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
547 if (Src1->getReg().isPhysical() || Dst->getReg().isPhysical())
553 Dst, Src1, *Imm == 16 ? WORD_1 : BYTE_3, UNUSED_PAD);
556 Src1, Dst, *Imm == 16 ? WORD_1 : BYTE_3, false, false,
582 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1);
    [all...]
SIShrinkInstructions.cpp 182 const MachineOperand &Src1 = MI.getOperand(1);
183 if (!Src1.isImm())
194 if (isKImmOrKUImmOperand(TII, Src1, HasUImm)) {
208 if ((TII->sopkIsZext(SOPKOpc) && isKUImmOperand(TII, Src1)) ||
209 (!TII->sopkIsZext(SOPKOpc) && isKImmOperand(TII, Src1))) {
316 MachineOperand *Src1 = &MI.getOperand(2);
318 MachineOperand *SrcImm = Src1;
651 MachineOperand *Src1 = &MI.getOperand(2);
653 if (!Src0->isReg() && Src1->isReg()) {
655 std::swap(Src0, Src1);
    [all...]
AMDGPUInstCombineIntrinsic.cpp 43 static APFloat fmed3AMDGCN(const APFloat &Src0, const APFloat &Src1,
45 APFloat Max3 = maxnum(maxnum(Src0, Src1), Src2);
50 return maxnum(Src1, Src2);
52 APFloat::cmpResult Cmp1 = Max3.compare(Src1);
57 return maxnum(Src0, Src1);
279 Value *Src1 = II.getArgOperand(1);
280 const ConstantInt *CMask = dyn_cast<ConstantInt>(Src1);
286 if (isa<UndefValue>(Src1)) {
324 II, 1, ConstantInt::get(Src1->getType(), Mask & ~(S_NAN | Q_NAN)));
337 {Src0, ConstantInt::get(Src1->getType(), Mask & FullMask)})
    [all...]
SIFoldOperands.cpp 221 else if (OpNo == AMDGPU::getNamedOperandIdx(Opcode, AMDGPU::OpName::src1))
866 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
885 UseMI->RemoveOperand(2); // Remove exec read (or src1 for readlane)
1066 int Src1Idx = AMDGPU::getNamedOperandIdx(Opc, AMDGPU::OpName::src1);
1069 MachineOperand *Src1 = getImmOrMaterializedImm(MRI, MI->getOperand(Src1Idx));
1071 if (!Src0->isImm() && !Src1->isImm())
1077 if (Src0->isImm() && Src1->isImm()) {
1079 if (!evalBinaryInstruction(Opc, NewImm, Src0->getImm(), Src1->getImm()))
1096 if (Src0->isImm() && !Src1->isImm()) {
1097 std::swap(Src0, Src1);
    [all...]
SILoadStoreOptimizer.cpp 1462 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata);
1467 .add(*Src1)
1617 const auto *Src1 = TII->getNamedOperand(*Paired.I, AMDGPU::OpName::vdata);
1622 .add(*Src1)
1791 const auto *Src1 = TII->getNamedOperand(*BaseLoDef, AMDGPU::OpName::src1);
1795 BaseLo = *Src1;
1797 if (!(Offset0P = extractConstOffset(*Src1)))
1803 Src1 = TII->getNamedOperand(*BaseHiDef, AMDGPU::OpName::src1);
    [all...]
AMDGPUISelDAGToDAG.cpp 1135 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp, omod
1149 // src0_modifiers, src0, src1_modifiers, src1, clamp, omod
1171 // src0_modifiers, src0, src1_modifiers, src1, src2_modifiers, src2, clamp,
2320 SDValue Src1 = N->getOperand(1);
2327 bool Sel1 = SelectVOP3PMadMixModsImpl(Src1, Src1, Src1Mods);
2340 CurDAG->getTargetConstant(Src1Mods, SDLoc(), MVT::i32), Src1,
AMDGPUInstructionSelector.cpp 604 Register Src1 = MI.getOperand(2).getReg();
612 getConstantVRegValWithLookThrough(Src1, *MRI, true, true, true);
631 MachineInstr *Src1Def = getDefIgnoringCopies(Src1, *MRI);
645 // (build_vector_trunc (lshr_oneuse $src0, 16), (lshr_oneuse $src1, 16)
646 // => (S_PACK_HH_B32_B16 $src0, $src1)
647 // (build_vector_trunc $src0, (lshr_oneuse SReg_32:$src1, 16))
648 // => (S_PACK_LH_B32_B16 $src0, $src1)
649 // (build_vector_trunc $src0, $src1)
650 // => (S_PACK_LL_B32_B16 $src0, $src1)
656 Src1, *MRI, m_OneUse(m_GLShr(m_Reg(ShiftSrc1), m_SpecificICst(16))))
    [all...]
AMDGPURegisterBankInfo.cpp 1383 Register Src1 = getSrcRegIgnoringCopies(*MRI, Add->getOperand(2).getReg());
1386 const RegisterBank *Src1Bank = RBI.getRegBank(Src1, *MRI, *RBI.TRI);
1390 SOffsetReg = Src1;
1395 VOffsetReg = Src1;
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGBuiltin.cpp 462 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1));
467 return CGF.Builder.CreateConstrainedFPCall(F, { Src0, Src1 });
470 return CGF.Builder.CreateCall(F, { Src0, Src1 });
480 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1));
486 return CGF.Builder.CreateConstrainedFPCall(F, { Src0, Src1, Src2 });
489 return CGF.Builder.CreateCall(F, { Src0, Src1, Src2 });
528 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1));
531 return CGF.Builder.CreateCall(F, { Src0, Src1 });
539 llvm::Value *Src1 = CGF.EmitScalarExpr(E->getArg(1));
543 return CGF.Builder.CreateCall(F, { Src0, Src1, Src2 })
    [all...]
  /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
MIPatternMatch.h 521 Src1Ty Src1;
524 TernaryOp_match(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2)
525 : Src0(Src0), Src1(Src1), Src2(Src2) {}
532 Src1.match(MRI, TmpMI->getOperand(2).getReg()) &&
542 m_GInsertVecElt(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
544 TargetOpcode::G_INSERT_VECTOR_ELT>(Src0, Src1, Src2);
549 m_GISelect(const Src0Ty &Src0, const Src1Ty &Src1, const Src2Ty &Src2) {
551 Src0, Src1, Src2);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/
InferAddressSpaces.cpp 657 Constant *Src1 = CE->getOperand(2);
659 Src1->getType()->getPointerAddressSpace()) {
663 ConstantExpr::getAddrSpaceCast(Src1, TargetType));
843 Value *Src1 = Op.getOperand(2);
849 auto J = InferredAddrSpace.find(Src1);
851 J->second : Src1->getType()->getPointerAddressSpace();
854 auto *C1 = dyn_cast<Constant>(Src1);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
AArch64InstPrinter.cpp 1016 unsigned Src1 = MI->getOperand(1).getReg();
1017 if ( ((Dest == AArch64::SP || Src1 == AArch64::SP) &&
1019 ((Dest == AArch64::WSP || Src1 == AArch64::WSP) &&
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelDAGToDAG.cpp 441 SDValue Src1 = Node->getOperand(1);
453 MVT Src1VT = Src1.getSimpleValueType();
502 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
510 SDValue Src1 = Node->getOperand(2);
522 MVT Src1VT = Src1.getSimpleValueType();
595 CurDAG->getMachineNode(VMSLTOpcode, DL, VT, {Src1, Src2, VL, SEW}),
606 {MaskedOff, Src1, Src2, Mask, VL, SEW}),
  /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
WebAssemblyISelLowering.cpp 1834 SDValue Src1 = ShuffleSrc1;
1836 if (Src1.getValueType() != VecT) {
1838 Src1.getValueType().getVectorElementType().getFixedSizeInBits() / 8;
1841 Src1 = DAG.getBitcast(VecT, Src1);
1865 Result = DAG.getVectorShuffle(VecT, DL, Src1, Src2, MaskRef);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
IRTranslator.cpp 1648 Register Src1 = getOrCreateVReg(*CI.getOperand(1));
1650 MIRBuilder.buildInstr(Op, {Dst}, { Src0, Src1, Scale });
  /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
SparcISelLowering.cpp 2894 SDValue Src1 = Op.getOperand(0);
2895 SDValue Src1Lo = DAG.getNode(ISD::TRUNCATE, dl, MVT::i32, Src1);
2896 SDValue Src1Hi = DAG.getNode(ISD::SRL, dl, MVT::i64, Src1,

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