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    Searched defs:SrcReg1 (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SIMDInstrOpt.cpp 435 Register SrcReg1 = MI.getOperand(2).getReg();
455 .addReg(SrcReg1, Src1IsKill)
459 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg1, LaneNumber, &DupDest)) {
462 .addReg(SrcReg1, Src1IsKill)
AArch64InstrInfo.cpp 3583 Register SrcReg1 = SrcReg;
3587 SrcReg1 = TRI.getSubReg(SrcReg, SubIdx1);
3592 .addReg(SrcReg1, getKillRegState(IsKill), SubIdx1)
5017 Register SrcReg1 = MUL->getOperand(2).getReg();
5035 if (Register::isVirtualRegister(SrcReg1))
5036 MRI.constrainRegClass(SrcReg1, RC);
5044 .addReg(SrcReg1, getKillRegState(Src1IsKill))
5050 .addReg(SrcReg1, getKillRegState(Src1IsKill))
5056 .addReg(SrcReg1, getKillRegState(Src1IsKill));
5168 Register SrcReg1 = MUL->getOperand(2).getReg()
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  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 850 unsigned SrcReg1 = getRegForValue(SrcValue1);
851 if (SrcReg1 == 0)
864 auto RC1 = MRI.getRegClass(SrcReg1);
886 SrcReg1 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg1);
932 if (!PPCEmitIntExt(SrcVT, SrcReg1, MVT::i32, ExtReg, IsZExt))
934 SrcReg1 = ExtReg;
946 .addReg(SrcReg1).addReg(SrcReg2);
949 .addReg(SrcReg1).addImm(Imm);
1299 unsigned SrcReg1 = getRegForValue(I->getOperand(0))
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  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 1409 unsigned SrcReg1 = getRegForValue(Src1Value);
1410 if (SrcReg1 == 0) return false;
1420 SrcReg1 = ARMEmitIntExt(SrcVT, SrcReg1, MVT::i32, isZExt);
1421 if (SrcReg1 == 0) return false;
1429 SrcReg1 = constrainOperandRegClass(II, SrcReg1, 0);
1433 .addReg(SrcReg1).addReg(SrcReg2));
1437 .addReg(SrcReg1);
1755 unsigned SrcReg1 = getRegForValue(I->getOperand(0))
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