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    Searched defs:SrcReg2 (Results 1 - 7 of 7) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64SIMDInstrOpt.cpp 441 Register SrcReg2 = MI.getOperand(3).getReg();
447 if (!reuseDUP(MI, DupMCID->getOpcode(), SrcReg2, LaneNumber, &DupDest)) {
450 .addReg(SrcReg2, Src2IsKill)
  /src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
SystemZElimCompare.cpp 627 // SrcReg2 is the register if the source operand is a register,
631 Register SrcReg2 =
636 (SrcReg2 && MBBI->modifiesRegister(SrcReg2, TRI)))
690 // Clear any intervening kills of SrcReg and SrcReg2.
694 if (SrcReg2)
695 MBBI->clearRegisterKills(SrcReg2, TRI);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
PeepholeOptimizer.cpp 613 Register SrcReg, SrcReg2;
615 if (!TII->analyzeCompare(MI, SrcReg, SrcReg2, CmpMask, CmpValue) ||
616 SrcReg.isPhysical() || SrcReg2.isPhysical())
621 if (TII->optimizeCompareInstr(MI, SrcReg, SrcReg2, CmpMask, CmpValue, MRI)) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCFastISel.cpp 854 unsigned SrcReg2 = 0;
856 SrcReg2 = getRegForValue(SrcValue2);
857 if (SrcReg2 == 0)
865 auto RC2 = SrcReg2 != 0 ? MRI.getRegClass(SrcReg2) : nullptr;
888 SrcReg2 = copyRegToRegClass(&PPC::F4RCRegClass, SrcReg2);
938 if (!PPCEmitIntExt(SrcVT, SrcReg2, MVT::i32, ExtReg, IsZExt))
940 SrcReg2 = ExtReg;
946 .addReg(SrcReg1).addReg(SrcReg2);
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMFastISel.cpp 1412 unsigned SrcReg2 = 0;
1414 SrcReg2 = getRegForValue(Src2Value);
1415 if (SrcReg2 == 0) return false;
1423 SrcReg2 = ARMEmitIntExt(SrcVT, SrcReg2, MVT::i32, isZExt);
1424 if (SrcReg2 == 0) return false;
1431 SrcReg2 = constrainOperandRegClass(II, SrcReg2, 1);
1433 .addReg(SrcReg1).addReg(SrcReg2));
1760 unsigned SrcReg2 = getRegForValue(I->getOperand(1))
    [all...]
ARMBaseInstrInfo.cpp 2769 /// in SrcReg and SrcReg2 if having two register operands, and the value it
2773 Register &SrcReg2, int &CmpMask,
2781 SrcReg2 = 0;
2789 SrcReg2 = MI.getOperand(1).getReg();
2796 SrcReg2 = 0;
2844 Register SrcReg, Register SrcReg2,
2850 OI->getOperand(2).getReg() == SrcReg2) ||
2851 (OI->getOperand(1).getReg() == SrcReg2 &&
2859 OI->getOperand(3).getReg() == SrcReg2) ||
2860 (OI->getOperand(2).getReg() == SrcReg2 &
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86InstrInfo.cpp 1537 Register SrcReg2;
1540 SrcReg2, isKill2, ImplicitOp2, LV))
1549 NewMI = addRegReg(MIB, SrcReg, isKill, SrcReg2, isKill2);
1551 LV->replaceKillInstruction(SrcReg2, MI, *NewMI);
3855 Register &SrcReg2, int &CmpMask,
3867 SrcReg2 = 0;
3881 SrcReg2 = 0;
3890 SrcReg2 = MI.getOperand(2).getReg();
3902 SrcReg2 = 0;
3915 SrcReg2 = MI.getOperand(1).getReg()
    [all...]

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