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    Searched defs:StackSlot (Results 1 - 4 of 4) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
InlineSpiller.cpp 101 // Map from StackSlot to the LiveInterval of the original register.
107 // Map from pair of (StackSlot and Original VNI) to a set of spills which
108 // have the same stackslot and have equal values defined by Original VNI.
152 void addToMergeableSpills(MachineInstr &Spill, int StackSlot,
154 bool rmFromMergeableSpills(MachineInstr &Spill, int StackSlot);
175 int StackSlot;
178 // All registers to spill to StackSlot, including the main register.
315 if (SnipLI.reg() == TII.isLoadFromStackSlot(MI, FI) && FI == StackSlot)
319 if (SnipLI.reg() == TII.isStoreToStackSlot(MI, FI) && FI == StackSlot)
427 TII.storeRegToStackSlot(*MBB, MII, SrcReg, false, StackSlot,
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  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGBuilder.cpp 2700 // If the guard/stackslot do not equal, branch to failure MBB.
8188 SDValue StackSlot = DAG.getFrameIndex(SSFI, TLI.getFrameIndexTy(DL));
8189 Chain = DAG.getTruncStore(Chain, Location, OpInfo.CallOperand, StackSlot,
8192 OpInfo.CallOperand = StackSlot;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 1624 SDValue StackSlot =
1628 Lo = DAG.getStore(Chain, DL, Lo, StackSlot, MPI, Align(8));
1631 DAG.getMemBasePlusOffset(StackSlot, TypeSize::Fixed(4), DL);
1638 SDValue Ops[] = {Chain, IntID, StackSlot,
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8685 SDValue StackSlot = DAG.getFrameIndex(SSFI, PtrVT);
8686 Chain = DAG.getStore(Chain, dl, MFFS, StackSlot, MachinePointerInfo());
8692 SDValue Addr = DAG.getNode(ISD::ADD, dl, PtrVT, StackSlot, Four);

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