| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| LiveIntervalCalc.cpp | 68 unsigned SubReg = MO.getSubReg();
69 if (LI.hasSubRanges() || (SubReg != 0 && TrackSubRegs)) {
70 LaneBitmask SubMask = SubReg != 0 ? TRI.getSubRegIndexLaneMask(SubReg)
168 unsigned SubReg = MO.getSubReg();
169 if (SubReg != 0) {
170 LaneBitmask SLM = TRI.getSubRegIndexLaneMask(SubReg);
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| LiveRangeEdit.cpp | 201 // FIXME: Targets don't know how to fold subreg uses.
251 unsigned SubReg = MO.getSubReg();
252 LaneBitmask LaneMask = TRI.getSubRegIndexLaneMask(SubReg);
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| MachineInstrBundle.cpp | 198 unsigned SubReg = *SubRegs;
199 if (LocalDefSet.insert(SubReg).second)
200 LocalDefs.push_back(SubReg);
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| DetectDeadLanes.cpp | 174 unsigned SubReg = MI.getOperand(2).getImm();
175 SrcSubIdx = TRI.composeSubRegIndices(SubReg, SrcSubIdx);
424 unsigned SubReg = MO.getSubReg();
447 if (SubReg == 0)
450 UsedLanes |= TRI->getSubRegIndexLaneMask(SubReg);
457 unsigned SubReg = MO.getSubReg();
458 LaneBitmask Mask = TRI->getSubRegIndexLaneMask(SubReg);
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| LiveVariables.cpp | 196 unsigned SubReg = *SubRegs;
197 MachineInstr *Def = PhysRegDef[SubReg];
202 LastDefReg = SubReg;
250 unsigned SubReg = *SubRegs;
251 if (Processed.count(SubReg))
253 if (PartDefRegs.count(SubReg))
257 LastPartialDef->addOperand(MachineOperand::CreateReg(SubReg,
260 PhysRegDef[SubReg] = LastPartialDef;
261 for (MCSubRegIterator SS(SubReg, TRI); SS.isValid(); ++SS)
289 unsigned SubReg = *SubRegs
[all...] |
| VirtRegMap.cpp | 359 // Sort and unique MBB LiveIns as we've not checked if SubReg/PhysReg were in
554 unsigned SubReg = MO.getSubReg();
555 if (SubReg != 0) {
593 PhysReg = TRI->getSubReg(PhysReg, SubReg);
594 assert(PhysReg.isValid() && "Invalid SubReg for physical register");
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| MachineOperand.cpp | 518 OS << "%subreg.";
773 if (unsigned SubReg = getSubReg()) {
775 OS << '.' << TRI->getSubRegIndexName(SubReg);
777 OS << ".subreg" << SubReg;
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| LiveIntervals.cpp | 577 unsigned SubReg = MO.getSubReg();
578 if (SubReg != 0) {
579 LaneBitmask LaneMask = TRI->getSubRegIndexLaneMask(SubReg);
791 unsigned SubReg = MO.getSubReg();
792 LaneBitmask UseMask = SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
1031 unsigned SubReg = MO.getSubReg();
1032 LaneBitmask LaneMask = SubReg ? TRI.getSubRegIndexLaneMask(SubReg)
1193 // We merge OldIdxOut and its successor. As we're dealing with subreg
[all...] |
| ScheduleDAGInstrs.cpp | 340 for (MCSubRegIterator SubReg(Reg, TRI, true); SubReg.isValid(); ++SubReg) {
341 if (Uses.contains(*SubReg))
342 Uses.eraseAll(*SubReg);
344 Defs.eraseAll(*SubReg);
376 unsigned SubReg = MO.getSubReg();
377 if (SubReg == 0)
379 return TRI->getSubRegIndexLaneMask(SubReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFixSGPRCopies.cpp | 247 unsigned SubReg = CopyUse.getOperand(1).getSubReg();
248 if (SubReg != AMDGPU::NoSubRegister)
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| SIPreAllocateWWMRegs.cpp | 132 const unsigned SubReg = MO.getSubReg();
133 if (SubReg != 0) {
134 PhysReg = TRI->getSubReg(PhysReg, SubReg);
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| R600OptimizeVectorRegisters.cpp | 11 /// common data and/or have enough undef subreg using swizzle abilities.
196 unsigned SubReg = (*It).first;
203 .addReg(SubReg)
205 UpdatedRegToChan[SubReg] = Chan;
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| SIRegisterInfo.cpp | 282 "getNumCoveredRegs() will not work with generated subreg masks!");
1144 Register SubReg = e == 1
1190 // current SubReg has been already spilled into AGPRs by the loop above.
1197 SubReg = Register(getSubReg(ValueReg,
1203 unsigned FinalReg = SubReg;
1217 .addReg(SubReg, getKillRegState(IsKill));
1222 SubReg = TmpReg;
1232 .addReg(SubReg, getDefRegState(!IsStore) | getKillRegState(IsKill));
1321 Register SubReg =
1333 .addReg(SubReg, getKillRegState(UseKill)
[all...] |
| SIWholeQuadMode.cpp | 187 unsigned SubReg, char Flag, std::vector<WorkItem> &Worklist);
316 Register Reg, unsigned SubReg, char Flag,
328 SubReg ? TRI->getSubRegIndexLaneMask(SubReg)
1428 const unsigned SubReg = MI->getOperand(0).getSubReg();
1433 if (SubReg)
1434 regClass = TRI->getSubRegClass(regClass, SubReg);
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AdvSIMDScalarPass.cpp | 104 static bool isGPR64(unsigned Reg, unsigned SubReg,
106 if (SubReg)
113 static bool isFPR64(unsigned Reg, unsigned SubReg,
117 SubReg == 0) ||
119 SubReg == AArch64::dsub);
121 return (AArch64::FPR64RegClass.contains(Reg) && SubReg == 0) ||
122 (AArch64::FPR128RegClass.contains(Reg) && SubReg == AArch64::dsub);
129 unsigned &SubReg) {
130 SubReg = 0;
138 SubReg = AArch64::dsub
[all...] |
| AArch64InstrInfo.cpp | 3186 int SubReg = 0, End = NumRegs, Incr = 1;
3188 SubReg = NumRegs - 1;
3193 for (; SubReg != End; SubReg += Incr) {
3195 AddSubReg(MIB, DestReg, Indices[SubReg], RegState::Define, TRI);
3196 AddSubReg(MIB, SrcReg, Indices[SubReg], 0, TRI);
3197 AddSubReg(MIB, SrcReg, Indices[SubReg], getKillRegState(KillSrc), TRI);
3217 for (unsigned SubReg = 0; SubReg != NumRegs; ++SubReg) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMAsmPrinter.cpp | 417 Register SubReg =
419 O << ARMInstPrinter::getRegisterName(SubReg);
|
| ARMExpandPseudoInsts.cpp | 553 Register SubReg = TRI->getSubReg(DstReg, SubRegIndex);
554 unsigned DstRegPair = TRI->getMatchingSuperReg(SubReg, ARM::dsub_0,
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFMIPeephole.cpp | 219 Register SubReg = MovMI->getOperand(1).getReg();
227 .addImm(0).addReg(SubReg).addImm(BPF::sub_32);
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/ |
| InstructionSelectorImpl.h | 941 unsigned SubReg = 0;
943 SubReg = MatchTable[CurrentIdx++];
947 OutMIs[InsnID].addReg(State.TempRegisters[TempRegID], TempRegFlags, SubReg);
952 if (SubReg)
953 dbgs() << '.' << TRI.getSubRegIndexName(SubReg);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| AArch64InstructionSelector.cpp | 553 const TargetRegisterInfo &TRI, unsigned &SubReg) {
556 SubReg = AArch64::bsub;
559 SubReg = AArch64::hsub;
563 SubReg = AArch64::sub_32;
565 SubReg = AArch64::ssub;
568 SubReg = AArch64::dsub;
803 /// E.g "To = COPY SrcReg:SubReg"
806 const TargetRegisterClass *To, unsigned SubReg) {
809 assert(SubReg && "Expected a valid subregister");
813 MIB.buildInstr(TargetOpcode::COPY, {To}, {}).addReg(SrcReg, 0, SubReg);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| MIParser.cpp | 445 bool parseSubRegisterIndex(unsigned &SubReg);
1428 bool MIParser::parseSubRegisterIndex(unsigned &SubReg) {
1434 SubReg = PFS.Target.getSubRegIndex(Name);
1435 if (!SubReg)
1506 unsigned SubReg = 0;
1508 if (parseSubRegisterIndex(SubReg))
1570 Flags & RegState::EarlyClobber, SubReg, Flags & RegState::Debug,
|
| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| TargetInstrInfo.h | 244 /// expected the pre-extension value is available as a subreg of the result
382 /// DestReg:SubIdx. Any existing subreg index is preserved or composed with
463 /// Used to give some type checking when modeling Reg:SubReg.
466 unsigned SubReg;
468 RegSubRegPair(Register Reg = Register(), unsigned SubReg = 0)
469 : Reg(Reg), SubReg(SubReg) {}
472 return Reg == P.Reg && SubReg == P.SubReg;
485 RegSubRegPairAndIdx(Register Reg = Register(), unsigned SubReg = 0
[all...] |
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenRegisters.cpp | 254 for (const auto &SubReg : SubRegs) {
255 CodeGenRegister *SR = SubReg.second;
301 // Expand any composed subreg indices.
303 // qsub_1 subreg, add a dsub_2 subreg. Keep growing Indices and process
304 // expanded subreg indices recursively.
318 // Add I->second as a name for the subreg SRI->second, assuming it is
331 // Consider this subreg sequence:
342 // dsub_1, dsub_2] subregs without necessarily having a qsub_1 subreg. The
348 for (const auto &SubReg : Map
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| IRTranslator.cpp | 1013 Register SubReg = RangeSub.getReg(0);
1015 SubReg = MIB.buildZExtOrTrunc(MaskTy, SubReg).getReg(0);
1018 B.Reg = SubReg;
|
