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    Searched defs:SubRegs (Results 1 - 8 of 8) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/include/llvm/MC/
MCRegisterInfo.h 99 /// register. The SubRegs field is a zero terminated array of registers that
107 uint32_t SubRegs; // Sub-register set, described above
111 // sub-register in SubRegs.
291 : mc_difflist_iterator(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs) {}
309 iterator_range<mc_subreg_iterator> subregs(MCRegister Reg) const { function in class:llvm::MCRegisterInfo
598 init(Reg, MCRI->DiffLists + MCRI->get(Reg).SubRegs);
  /src/external/apache2/llvm/dist/llvm/utils/TableGen/
CodeGenRegisters.h 185 return SubRegs;
278 SubRegMap SubRegs;
CodeGenRegisters.cpp 167 std::vector<Record*> SRs = TheDef->getValueAsListOfDefs("SubRegs");
171 "SubRegs and SubRegIndices must have the same size");
179 // covered-by-subregs super-registers where it appears as the first explicit
254 for (const auto &SubReg : SubRegs) {
267 return SubRegs;
272 // First insert the explicit subregs and make sure they are fully indexed.
278 if (!SubRegs.insert(std::make_pair(Idx, SR)).second)
286 // Keep track of inherited subregs and how they can be reached.
289 // Clone inherited subregs and place duplicate entries in Orphans.
290 // Here the order is important - earlier subregs take precedence
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  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
AArch64ISelDAGToDAG.cpp 239 const unsigned SubRegs[]);
1193 static const unsigned SubRegs[] = {AArch64::dsub0, AArch64::dsub1,
1196 return createTuple(Regs, RegClassIDs, SubRegs);
1202 static const unsigned SubRegs[] = {AArch64::qsub0, AArch64::qsub1,
1205 return createTuple(Regs, RegClassIDs, SubRegs);
1212 static const unsigned SubRegs[] = {AArch64::zsub0, AArch64::zsub1,
1215 return createTuple(Regs, RegClassIDs, SubRegs);
1220 const unsigned SubRegs[]) {
1239 Ops.push_back(CurDAG->getTargetConstant(SubRegs[i], DL, MVT::i32));
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 521 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(DstRC, SrcSize / 8);
527 MIB.addImm(SubRegs[I]);
566 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SrcRC, DstSize / 8);
570 .addReg(SrcReg, 0, SubRegs[I]);
573 SrcRC = TRI.getSubClassWithSubReg(SrcRC, SubRegs[I]);
2602 ArrayRef<int16_t> SubRegs = TRI.getRegSplitParts(SuperRC, EltSize);
2606 if (static_cast<unsigned>(Offset) >= SubRegs.size())
2607 return std::make_pair(IdxReg, SubRegs[0]);
2608 return std::make_pair(IdxBaseReg, SubRegs[Offset]);
SIInstrInfo.cpp 4927 unsigned SubRegs = RI.getRegSizeInBits(*VRC) / 32;
4938 if (SubRegs == 1) {
4946 for (unsigned i = 0; i < SubRegs; ++i) {
4957 for (unsigned i = 0; i < SubRegs; ++i) {
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMBaseInstrInfo.cpp 933 unsigned SubRegs = 0;
940 SubRegs = 2;
944 SubRegs = 4;
949 SubRegs = 2;
953 SubRegs = 3;
957 SubRegs = 4;
961 SubRegs = 2;
965 SubRegs = 2;
970 SubRegs = 3;
975 SubRegs = 4
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ARMISelDAGToDAG.cpp 201 /// loads of D registers and even subregs and odd subregs of Q registers.
209 /// stores of D registers and even subregs and odd subregs of Q registers.
2165 // Load the even subregs. This is always an updating load, so that it
2166 // provides the address to the second load for the odd subregs.
2174 // Load the odd subregs.
2341 // provides the address to the second store for the odd subregs.
2896 uint16_t SubRegs[2] = {ARM::gsub_0, ARM::gsub_1};
2898 std::swap(SubRegs[0], SubRegs[1])
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