| /src/sys/external/bsd/compiler_rt/dist/lib/xray/tests/unit/ |
| buffer_queue_test.cc | 101 auto T0 = std::async(std::launch::async, F);
212 std::thread T0(Process), T1(Process);
228 T0.join();
|
| /src/external/gpl3/gcc.old/dist/libgcc/config/arc/ieee-754/ |
| divtab-arc-sf.c | 112 long double T0, Ti1;
117 T0 = T[0] - (T[1]-Ti1)/P[1][1] * P[1][0] - (X1 - 1) * Ti1;
118 i0 = T0 * 512 * 1024 + 0.5;
|
| divtab-arc-df.c | 129 long double T0, Ti1;
136 T0 = T[0] - (T[1]-Ti1)/P[1][1] * P[1][0] - (X1 - 1) * Ti1;
137 i0 = T0 * 1024 * 1024 + 0.5;
|
| /src/external/gpl3/gcc.old/dist/libquadmath/math/ |
| tanq_kernel.c | 70 T0 = -1.813014711743583437742363284336855889393E7Q,
125 r = T0 + z * (T1 + z * (T2 + z * (T3 + z * T4)));
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcISelDAGToDAG.cpp | 247 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
249 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
262 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
265 T0.getValue(1));
272 T0,
|
| /src/external/gpl3/gcc.old/dist/gcc/ |
| tree-outof-ssa.cc | 887 tree T0 = var_to_partition_to_var (map, gimple_phi_result (phi));
888 if (T0 == NULL_TREE)
|
| /src/sys/external/isc/libsodium/dist/src/libsodium/crypto_onetimeauth/poly1305/sse2/ |
| poly1305_sse2.c | 110 uint64_t t0, t1; local
122 memcpy(&t0, key, 8);
124 r0 = t0 & 0xffc0fffffff;
125 t0 >>= 44;
126 t0 |= t1 << 20;
127 r1 = t0 & 0xfffffc0ffff;
207 xmmi T0, T1, T2, T3, T4, T5, T6, T7, T8;
239 T0 = _mm_loadu_si128((const xmmi *) (const void *) &st->H.hh[0]);
242 H0 = _mm_shuffle_epi32(T0, _MM_SHUFFLE(1, 1, 0, 0));
243 H1 = _mm_shuffle_epi32(T0, _MM_SHUFFLE(3, 3, 2, 2))
685 uint32_t t0, t1, t2, t3, t4, b; local
[all...] |
| /src/external/bsd/pcc/dist/pcc/arch/mips/ |
| macdefs.h | 151 #define T0 12
156 #define T0 8
269 { A3T0, T0T1, -1 }, /* $t0 */ \
302 { A3, T0, A2A3, T0T1, -1 }, /* $a3:$t0 */ \
303 { T0, T1, A3T0, T1T2, -1 }, /* $t0:$t1 */ \
|
| /src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| sislands_smc.h | 376 uint32_t T0;
|
| /src/sys/external/bsd/drm2/dist/drm/radeon/ |
| sislands_smc.h | 376 uint32_t T0;
|
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/InstCombine/ |
| InstCombineSelect.cpp | 333 Value *T0, *T1, *F0, *F1;
334 if (match(TII, m_MaxOrMin(m_Value(T0), m_Value(T1))) &&
336 if (T0 == F0) {
338 return CallInst::Create(TII->getCalledFunction(), {NewSel, T0});
340 if (T0 == F1) {
342 return CallInst::Create(TII->getCalledFunction(), {NewSel, T0});
345 Value *NewSel = Builder.CreateSelect(Cond, T0, F1, "minmaxop", &SI);
349 Value *NewSel = Builder.CreateSelect(Cond, T0, F0, "minmaxop", &SI);
|
| InstCombineCompares.cpp | 3502 // T0 = add %x, AddCst
3503 Value *T0 = Builder.CreateAdd(X, ConstantInt::get(XType, AddCst));
3504 // T1 = T0 DstPred ICmpCst
3505 Value *T1 = Builder.CreateICmp(DstPred, T0, ConstantInt::get(XType, ICmpCst));
3671 Value *T0 = XShiftOpcode == Instruction::BinaryOps::LShr
3674 Value *T1 = Builder.CreateAnd(T0, Y);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonISelDAGToDAG.cpp | 1044 // Off matched: (add x T0)
1045 SDValue T0 = Off.getOperand(1);
1046 // T0 needs to match: (add T1 T2):
1047 if (T0.getOpcode() != ISD::ADD)
1049 // T0 matched: (add T1 T2)
1050 SDValue T1 = T0.getOperand(0);
1051 SDValue T2 = T0.getOperand(1);
1071 // Replace T0 with: (shl (add y d) c)
1073 EVT VT = T0.getValueType();
1079 ReplaceNode(T0.getNode(), NewShl.getNode())
[all...] |
| HexagonISelLowering.cpp | 2205 SDValue T0 = DAG.getBitcast(MVT::i32, Op0);
2206 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i32, T0);
2232 SDValue T0 = DAG.getBitcast(MVT::i64, Op0);
2233 SDValue T1 = DAG.getNode(ISD::BSWAP, dl, MVT::i64, T0);
2425 SDValue T0 = DAG.getNode(ISD::SHL, dl, MVT::i32, {Vs[1], S8});
2427 SDValue B0 = DAG.getNode(ISD::OR, dl, MVT::i32, {Vs[0], T0});
2547 SDValue T0 = DAG.getNode(HexagonISD::P2D, dl, MVT::i64, VecV);
2548 SDValue T1 = DAG.getNode(ISD::SRL, dl, MVT::i64, T0, S0);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| ARMISelDAGToDAG.cpp | 5552 SDValue T0 = CurDAG->getCopyToReg(Sub0, dl, Reg0, Sub0,
5554 SDValue T1 = CurDAG->getCopyToReg(Sub1, dl, Reg1, Sub1, T0.getValue(1));
5567 SDValue T0 = CurDAG->getCopyFromReg(Chain, dl, Reg0, MVT::i32,
5570 T0.getValue(1));
5571 SDValue Pair = SDValue(createGPRPairNode(MVT::Untyped, T0, T1), 0);
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| CodeGenDAGPatterns.cpp | 1416 const TypeSetByHwMode &T0 = Child->getExtType(0);
1419 if (T0.getMachineValueType() != MVT::Other) {
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| TargetLowering.cpp | 3291 SDValue T0 = DAG.getNode(ISD::SHL, DL, XVT, X, ShiftAmt);
3292 SDValue T1 = DAG.getNode(ISD::SRA, DL, XVT, T0, ShiftAmt);
3363 SDValue T0 = DAG.getNode(NewShiftOpcode, DL, VT, X, Y);
3364 SDValue T1 = DAG.getNode(ISD::AND, DL, VT, T0, C);
|
| DAGCombiner.cpp | 5520 SDValue T0 = DAG.getNode(InnerShift, DL, VT, X, Y);
5522 SDValue T1 = DAG.getNode(OuterShift, DL, VT, T0, Y);
7456 /// t28: i8,ch = load<LD1[%tmp9]> t0, t27, undef:i64
10277 // t1: i8 = select t0, Constant:i8<-1>, Constant:i8<0>
10280 // t3: i64 = select t0, Constant:i64<-1>, Constant:i64<0>
15253 // x0 * offset0 + y0 * ptr0 = t0
15261 // t0 = (x0 * offset0 - x1 * y0 * y1 *offset1) + (y0 * y1) * t1
|
