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    Searched defs:TARGET_HARD_FLOAT (Results 1 - 14 of 14) sorted by relevancy

  /src/external/gpl3/gcc.old/dist/gcc/config/loongarch/
loongarch-opts.h 58 #define TARGET_HARD_FLOAT (la_target.isa.fpu != ISA_EXT_NOFPU)
  /src/external/gpl3/gcc/dist/gcc/config/loongarch/
loongarch-opts.h 95 #define TARGET_HARD_FLOAT (la_target.isa.fpu != ISA_EXT_NONE)
  /src/external/gpl3/gcc/dist/gcc/config/csky/
csky.h 141 #define TARGET_HARD_FLOAT (csky_float_abi != CSKY_FLOAT_ABI_SOFT)
148 #define TARGET_DOUBLE_FPU (TARGET_HARD_FLOAT && !TARGET_SINGLE_FPU)
  /src/external/gpl3/gcc/dist/gcc/config/xtensa/
xtensa.h 40 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
83 if (!TARGET_HARD_FLOAT) \
  /src/external/gpl3/gcc.old/dist/gcc/config/csky/
csky.h 141 #define TARGET_HARD_FLOAT (csky_float_abi != CSKY_FLOAT_ABI_SOFT)
148 #define TARGET_DOUBLE_FPU (TARGET_HARD_FLOAT && !TARGET_SINGLE_FPU)
  /src/external/gpl3/gcc.old/dist/gcc/config/xtensa/
xtensa.h 54 #define TARGET_HARD_FLOAT XCHAL_HAVE_FP
90 if (!TARGET_HARD_FLOAT) \
  /src/external/gpl3/gcc/dist/gcc/config/arc/
arc.h 1635 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0)
  /src/external/gpl3/gcc.old/dist/gcc/config/arc/
arc.h 1628 #define TARGET_HARD_FLOAT ((arc_fpu_build & (FPU_SP | FPU_DP)) != 0)
  /src/external/gpl3/gcc/dist/gcc/config/arm/
arm.h 133 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \
210 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE)
220 and TARGET_HARD_FLOAT to ensure that NEON instructions are
223 (TARGET_32BIT && TARGET_HARD_FLOAT \
241 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)
257 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \
346 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers
1469 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1481 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1746 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \
    [all...]
  /src/external/gpl3/gcc/dist/gcc/config/mips/
mips.h 395 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
399 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
1267 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1275 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
  /src/external/gpl3/gcc.old/dist/gcc/config/arm/
arm.h 133 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_SUB \
210 (TARGET_HARD_FLOAT && TARGET_FP16 && TARGET_VFP5 && TARGET_VFP_DOUBLE)
220 and TARGET_HARD_FLOAT to ensure that NEON instructions are
223 (TARGET_32BIT && TARGET_HARD_FLOAT \
241 (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 && arm_fp16_inst)
257 #define TARGET_BF16_FP (TARGET_32BIT && TARGET_HARD_FLOAT && TARGET_VFP5 \
340 TARGET_HARD_FLOAT. But the common instructions, RTL pattern and registers
1445 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1457 ((TARGET_HARD_FLOAT && IS_VFP_CLASS (CLASS)) \
1719 || (TARGET_AAPCS_BASED && TARGET_HARD_FLOAT \
    [all...]
  /src/external/gpl3/gcc.old/dist/gcc/config/mips/
mips.h 388 /* TARGET_HARD_FLOAT and TARGET_SOFT_FLOAT reflect whether the FPU is
392 #define TARGET_HARD_FLOAT (TARGET_HARD_FLOAT_ABI && !TARGET_MIPS16)
1242 'prefx', along with TARGET_HARD_FLOAT and TARGET_DOUBLE_FLOAT.
1250 instructions. Both require TARGET_HARD_FLOAT, and trunc.w.d
  /src/external/gpl3/gcc/dist/gcc/config/nds32/
nds32.h 912 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)
  /src/external/gpl3/gcc.old/dist/gcc/config/nds32/
nds32.h 912 #define TARGET_HARD_FLOAT (nds32_abi == NDS32_ABI_V2_FP_PLUS)

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