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      1 /* Definition of RISC-V target for GNU compiler.
      2    Copyright (C) 2016-2024 Free Software Foundation, Inc.
      3    Contributed by Andrew Waterman (andrew (at) sifive.com).
      4 
      5 This file is part of GCC.
      6 
      7 GCC is free software; you can redistribute it and/or modify
      8 it under the terms of the GNU General Public License as published by
      9 the Free Software Foundation; either version 3, or (at your option)
     10 any later version.
     11 
     12 GCC is distributed in the hope that it will be useful,
     13 but WITHOUT ANY WARRANTY; without even the implied warranty of
     14 MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
     15 GNU General Public License for more details.
     16 
     17 You should have received a copy of the GNU General Public License
     18 along with GCC; see the file COPYING3.  If not see
     19 <http://www.gnu.org/licenses/>.  */
     20 
     21 #ifndef GCC_RISCV_OPTS_H
     22 #define GCC_RISCV_OPTS_H
     23 
     24 enum riscv_abi_type {
     25   ABI_ILP32,
     26   ABI_ILP32E,
     27   ABI_ILP32F,
     28   ABI_ILP32D,
     29   ABI_LP64,
     30   ABI_LP64E,
     31   ABI_LP64F,
     32   ABI_LP64D
     33 };
     34 extern enum riscv_abi_type riscv_abi;
     35 
     36 enum riscv_code_model {
     37   CM_MEDLOW,
     38   CM_MEDANY,
     39   CM_LARGE,
     40   CM_PIC
     41 };
     42 extern enum riscv_code_model riscv_cmodel;
     43 
     44 enum riscv_isa_spec_class {
     45   ISA_SPEC_CLASS_NONE,
     46 
     47   ISA_SPEC_CLASS_2P2,
     48   ISA_SPEC_CLASS_20190608,
     49   ISA_SPEC_CLASS_20191213
     50 };
     51 
     52 extern enum riscv_isa_spec_class riscv_isa_spec;
     53 
     54 /* Keep this list in sync with define_attr "tune" in riscv.md.  */
     55 enum riscv_microarchitecture_type {
     56   generic,
     57   sifive_7,
     58   sifive_p400,
     59   sifive_p600,
     60   xiangshan,
     61   generic_ooo
     62 };
     63 extern enum riscv_microarchitecture_type riscv_microarchitecture;
     64 
     65 enum riscv_align_data {
     66   riscv_align_data_type_xlen,
     67   riscv_align_data_type_natural
     68 };
     69 
     70 /* Where to get the canary for the stack protector.  */
     71 enum stack_protector_guard {
     72   SSP_TLS,			/* per-thread canary in TLS block */
     73   SSP_GLOBAL			/* global canary */
     74 };
     75 
     76 /* RISC-V auto-vectorization RVV LMUL.  */
     77 enum rvv_max_lmul_enum {
     78   RVV_M1 = 1,
     79   RVV_M2 = 2,
     80   RVV_M4 = 4,
     81   RVV_M8 = 8,
     82   /* For dynamic LMUL, we compare COST start with LMUL8.  */
     83   RVV_DYNAMIC = 9
     84 };
     85 
     86 enum riscv_multilib_select_kind {
     87   /* Select multilib by builtin way.  */
     88   select_by_builtin,
     89   /* Select multilib by ABI, arch and code model.  */
     90   select_by_abi_arch_cmodel,
     91   /* Select multilib by ABI only.  */
     92   select_by_abi,
     93 };
     94 
     95 /* ENTITIES in mode switching.  */
     96 enum riscv_entity
     97 {
     98   RISCV_VXRM = 0,
     99   RISCV_FRM,
    100   MAX_RISCV_ENTITIES
    101 };
    102 
    103 /* RISC-V stringop strategy. */
    104 enum stringop_strategy_enum {
    105   /* No expansion. */
    106   STRATEGY_LIBCALL = 1,
    107   /* Use scalar expansion if possible. */
    108   STRATEGY_SCALAR = 2,
    109   /* Only vector expansion if possible. */
    110   STRATEGY_VECTOR = 4,
    111   /* Use any. */
    112   STRATEGY_AUTO = STRATEGY_SCALAR | STRATEGY_VECTOR
    113 };
    114 
    115 /* Behavior of VSETVL Pass.  */
    116 enum vsetvl_strategy_enum {
    117   /* Optimized: Run LCM dataflow analysis to reduce vsetvl* insns and
    118      delete any redundant ones generated in the process.  */
    119   VSETVL_OPT,
    120   /* Simple: Insert a vsetvl* instruction for each Vector instruction.  */
    121   VSETVL_SIMPLE,
    122   /* No fusion: Disable Phase 2 earliest global fusion.  */
    123   VSETVL_OPT_NO_FUSION,
    124 };
    125 
    126 /* RVV vector bits for option -mrvv-vector-bits, default is scalable.  */
    127 enum rvv_vector_bits_enum {
    128   /* scalable indicates taking the value of zvl*b as the minimal vlen.  */
    129   RVV_VECTOR_BITS_SCALABLE,
    130   /* zvl indicates taking the value of zvl*b as the exactly vlen.  */
    131   RVV_VECTOR_BITS_ZVL,
    132 };
    133 
    134 #define TARGET_ZICOND_LIKE (TARGET_ZICOND || (TARGET_XVENTANACONDOPS && TARGET_64BIT))
    135 
    136 /* Bit of riscv_zvl_flags will set contintuly, N-1 bit will set if N-bit is
    137    set, e.g. MASK_ZVL64B has set then MASK_ZVL32B is set, so we can use
    138    popcount to caclulate the minimal VLEN.  */
    139 #define TARGET_MIN_VLEN \
    140   ((riscv_zvl_flags == 0) \
    141    ? 0 \
    142    : 32 << (__builtin_popcount (riscv_zvl_flags) - 1))
    143 
    144 /* Same as TARGET_MIN_VLEN, but take an OPTS as gcc_options.  */
    145 #define TARGET_MIN_VLEN_OPTS(opts)                                             \
    146   ((opts->x_riscv_zvl_flags == 0)                                              \
    147      ? 0                                                                       \
    148      : 32 << (__builtin_popcount (opts->x_riscv_zvl_flags) - 1))
    149 
    150 /* TODO: Enable RVV movmisalign by default for now.  */
    151 #define TARGET_VECTOR_MISALIGN_SUPPORTED 1
    152 
    153 /* The maximmum LMUL according to user configuration.  */
    154 #define TARGET_MAX_LMUL                                                        \
    155   (int) (rvv_max_lmul == RVV_DYNAMIC ? RVV_M8 : rvv_max_lmul)
    156 
    157 /* TLS types.  */
    158 enum riscv_tls_type {
    159   TLS_TRADITIONAL,
    160   TLS_DESCRIPTORS
    161 };
    162 
    163 #endif /* ! GCC_RISCV_OPTS_H */
    164