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      1 /*	$NetBSD: windermerereg.h,v 1.2 2024/06/02 13:28:46 andvar Exp $	*/
      2 /*
      3  * Copyright (c) 2012 KIYOHARA Takashi
      4  * All rights reserved.
      5  *
      6  * Redistribution and use in source and binary forms, with or without
      7  * modification, are permitted provided that the following conditions
      8  * are met:
      9  * 1. Redistributions of source code must retain the above copyright
     10  *    notice, this list of conditions and the following disclaimer.
     11  * 2. Redistributions in binary form must reproduce the above copyright
     12  *    notice, this list of conditions and the following disclaimer in the
     13  *    documentation and/or other materials provided with the distribution.
     14  *
     15  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     16  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
     17  * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
     18  * DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT,
     19  * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
     20  * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
     21  * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     22  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
     23  * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
     24  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     25  * POSSIBILITY OF SUCH DAMAGE.
     26  */
     27 
     28 #define WINDERMERE_LCD_OFFSET		0x200
     29 #define WINDERMERE_INTR_OFFSET		0x500
     30 #define WINDERMERE_COM0_OFFSET		0x600
     31 #define WINDERMERE_COM1_OFFSET		0x700
     32 #define WINDERMERE_TC_OFFSET		0xc00
     33 #define   TC1_OFFSET			 0x00
     34 #define   TC2_OFFSET			 0x20
     35 #define WINDERMERE_RTC_OFFSET		0xd00
     36 #define WINDERMERE_GPIO_OFFSET		0xe00
     37 
     38 /* LCD */
     39 #define LCD_PALETTE_SIZE	0x20
     40 #define LCDCTL		0x00
     41 #define LCDCTL_EN		(1 << 0)
     42 #define LCDCTL_BW		(1 << 1)
     43 #define LCDCTL_DP		(1 << 2)
     44 #define LCDCTL_DONE		(1 << 3)
     45 #define LCDCTL_NEXT		(1 << 4)
     46 #define LCDCTL_ERR		(1 << 5)
     47 #define LCDCTL_TFT		(1 << 7)
     48 #define LCDCTL_M8B		(1 << 8)
     49 #define LCDST		0x01
     50 #define LCDST_NEXT		(1 << 1)
     51 #define LCDST_BER		(1 << 2)
     52 #define LCDST_ABC		(1 << 3)
     53 #define LCDST_FUF		(1 << 5)
     54 #define LCDDBAR1	0x04
     55 #define LCDT0		0x08
     56 #define LCDT0_HSW		(2 << 10)	/* Horizontal sync plus width */
     57 #define LCDT0_HFP		(1 << 16)	/* Horizontal front porch */
     58 #define LCDT0_HBP		(1 << 24)	/* Horizontal back porch */
     59 #define LCDT1		0x09
     60 #define LCDT1_VSW		(2 << 10)	/* Vertical sync plus width */
     61 #define LCDT1_VFP		(1 << 16)	/* Vertical front porch */
     62 #define LCDT1_VBP		(1 << 24)	/* Vertical back porch */
     63 #define LCDT2		0x0a
     64 #define LCDT2_IVS		(1 << 20)
     65 #define LCDT2_IHS		(1 << 21)
     66 #define LCDT2_IPC		(1 << 22)
     67 #define LCDT2_IEO		(1 << 23)
     68 
     69 /* Interrupt */
     70 #define INTSR		0x00	/* Interrupt Status(after masking) */
     71 #define INTRSR		0x01	/* Interrupt Status(before masking) */
     72 #define INTENS		0x02	/* Interrupt Enable */
     73 #define INTENC		0x03	/* Interrupt Disable */
     74 
     75 /* UART */
     76 #define UART_SIZE	0x20
     77 #define UART_FIFO_SIZE	0x10
     78 #define UARTDR		0x00
     79 #define   RSR_FE		(1 << 0)	/* bit8:  Frame Error */
     80 #define   RSR_PE		(1 << 1)	/* bit9:  Parity Error */
     81 #define   RSR_OE		(1 << 2)	/* bit10: Overrun Error */
     82 #define UARTFCR		0x01
     83 #define   FCR_BREAK		(1 << 0)
     84 #define   FCR_PRTEN		(1 << 1)
     85 #define   FCR_EVENPRT		(1 << 2)
     86 #define   FCR_XSTOP		(1 << 3)
     87 #define   FCR_UFIFOEN		(1 << 4)
     88 #define   FCR_WLEN_5		(0 << 5)
     89 #define   FCR_WLEN_6		(1 << 5)
     90 #define   FCR_WLEN_7		(2 << 5)
     91 #define   FCR_WLEN_8		(3 << 5)
     92 #define UARTLCR		0x02
     93 #define UARTCON		0x03
     94 #define   CON_UARTEN		(1 << 0)	/* UART Enable */
     95 #define   CON_SIREN		(1 << 1)	/* SiR disable */
     96 #define   CON_IRTXM		(1 << 2)	/* IrDA TX mode bit */
     97 #define UARTFR		0x04
     98 #define   FR_TXFF		(1 << 5)
     99 #define   FR_RXFE		(1 << 4)
    100 #define   FR_BUSY		(1 << 3)
    101 #define   FR_DCD		(1 << 2)
    102 #define   FR_DSR		(1 << 1)
    103 #define   FR_CTS		(1 << 0)
    104 #define UARTINT		0x05
    105 #define UARTINTM	0x06	/* Mask register */
    106 #define UARTINTR	0x07	/* Raw status register */
    107 #define   INT_RXINT		(1 << 0)
    108 #define   INT_TXINT		(1 << 1)
    109 #define   INT_MSINT		(1 << 2)	/* MODEM status */
    110 
    111 /* Time Counter (decremental counter) */
    112 #define TC_BITS		16	/* 16bit counter */
    113 #define TC_MAX		((1 << TC_BITS) - 1)
    114 #define TC_MASK		TC_MAX
    115 #define TC_LOAD		0x00
    116 #define TC_VAL		0x01
    117 #define TC_CTRL		0x02
    118 #define   CTRL_CLKSEL		(1 << 3)	/* 512kHz */
    119 #define   CTRL_MODE		(1 << 6)	/* Periodic Mode */
    120 #define   CTRL_ENABLE		(1 << 7)
    121 #define TC_EOI		0x03
    122 #define   EOI_EOI		(1 << 0)
    123 
    124 /* Real Time Clock */
    125 #define RTC_DRL		0x00	/* Data Register Low */
    126 #define RTC_DRH		0x01	/* Data Register High */
    127 #define RTC_MRL		0x02	/* Match Register Low */
    128 #define RTC_MRH		0x03	/* Match Register High */
    129 
    130 /* GPIO/KBD */
    131 #define GPIO_PADR	0x00
    132 #define GPIO_PBDR	0x01
    133 #define GPIO_PCDR	0x02
    134 #define GPIO_PDDR	0x03
    135 #define GPIO_PADDR	0x04
    136 #define GPIO_PBDDR	0x05
    137 #define GPIO_PCDDR	0x06
    138 #define GPIO_PDDDR	0x07
    139 #define GPIO_PEDR	0x08
    140 #define GPIO_PEDDR	0x09
    141 #define KSCAN		0x0a
    142