1 /* $NetBSD: i82801lpcreg.h,v 1.17 2023/04/12 06:39:15 riastradh Exp $ */ 2 3 /*- 4 * Copyright (c) 2004 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Minoura Makoto. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 /* 33 * Intel 82801 Series I/O Controller Hub (ICH) -- LPC Interface Bridge part 34 * register definitions. 35 */ 36 37 #ifndef _DEV_IC_I82801LPCREG_H_ 38 #define _DEV_IC_I82801LPCREG_H_ 39 /* 40 * PCI configuration registers 41 */ 42 #define LPCIB_PCI_PMBASE 0x40 43 #define LPCIB_PCI_PM_SIZE 0x00000080 44 #define LPCIB_PCI_ACPI_CNTL 0x44 45 # define LPCIB_PCI_ACPI_CNTL_EN (1 << 4) 46 /* GPIO config registers ICH6+ */ 47 #define LPCIB_PCI_GPIO_BASE_ICH6 0x48 48 #define LPCIB_PCI_GPIO_CNTL_ICH6 0x4c 49 #define LPCIB_PCI_BIOS_CNTL 0x4c /* actually 0x4e */ 50 #define LPCIB_PCI_BIOS_CNTL_BWE (0x0001 << 16) /* write enable */ 51 #define LPCIB_PCI_BIOS_CNTL_BLE (0x0002 << 16) /* lock enable */ 52 #define LPCIB_PCI_TCO_CNTL 0x54 53 /* GPIO config registers ICH0-ICH5 */ 54 #define LPCIB_PCI_GPIO_BASE 0x58 55 #define LPCIB_PCI_GPIO_SIZE 0x00000080 56 #define LPCIB_PCI_GPIO_CNTL 0x5c 57 #define LPCIB_PCI_GPIO_CNTL_EN (1 << 4) 58 #define LPCIB_PCI_PIRQA_ROUT 0x60 59 #define LPCIB_PCI_PIRQB_ROUT 0x61 60 #define LPCIB_PCI_PIRQC_ROUT 0x62 61 #define LPCIB_PCI_PIRQD_ROUT 0x63 62 #define LPCIB_PCI_SIRQ_CNTL 0x64 63 #define LPCIB_PCI_PIRQE_ROUT 0x68 64 #define LPCIB_PCI_PIRQF_ROUT 0x69 65 #define LPCIB_PCI_PIRQG_ROUT 0x6a 66 #define LPCIB_PCI_PIRQH_ROUT 0x6b 67 #define LPCIB_PCI_D31_ERR_CFG 0x88 68 #define LPCIB_PCI_D31_ERR_STS 0x8a 69 #define LPCIB_PCI_PCI_DMA_C 0x90 70 #define LPCIB_PCI_GEN_PMCON_1 0xa0 71 # define LPCIB_PCI_GEN_PMCON_1_SS_EN 0x08 72 #define LPCIB_PCI_GEN_PMCON_2 0xa2 73 #define LPCIB_PCI_GEN_PMCON_3 0xa4 74 #define LPCIB_PCI_STPCLK_DEL 0xa8 75 #define LPCIB_PCI_GPI_ROUT 0xb8 76 #define LPCIB_PCI_TRP_FWD_EN 0xc0 77 #define LPCIB_PCI_MON4_TRP_RNG 0xc4 78 #define LPCIB_PCI_MON5_TRP_RNG 0xc5 79 #define LPCIB_PCI_MON6_TRP_RNG 0xc6 80 #define LPCIB_PCI_MON7_TRP_RNG 0xc7 81 #define LPCIB_PCI_MON_TRP_MSK 0xcc 82 #define LPCIB_PCI_GEN_CNTL 0xd0 83 #define LPCIB_ICH5_HPTC_EN 0x00020000 84 #define LPCIB_ICH5_HPTC_WIN_MASK 0x0000c000 85 #define LPCIB_ICH5_HPTC_0000 0x00000000 86 #define LPCIB_ICH5_HPTC_0000_BASE 0xfed00000 87 #define LPCIB_ICH5_HPTC_1000 0x00008000 88 #define LPCIB_ICH5_HPTC_1000_BASE 0xfed01000 89 #define LPCIB_ICH5_HPTC_2000 0x00010000 90 #define LPCIB_ICH5_HPTC_2000_BASE 0xfed02000 91 #define LPCIB_ICH5_HPTC_3000 0x00018000 92 #define LPCIB_ICH5_HPTC_3000_BASE 0xfed03000 93 #define LPCIB_PCI_GEN_STA 0xd4 94 # define LPCIB_PCI_GEN_STA_SAFE_MODE (1 << 2) 95 # define LPCIB_PCI_GEN_STA_NO_REBOOT (1 << 1) 96 #define LPCIB_PCI_BACK_CNTL 0xd5 97 #define LPCIB_PCI_RTC_CONF 0xd8 98 #define LPCIB_PCI_COM_DEC 0xe0 99 #define LPCIB_PCI_LPCFDD_DEC 0xe1 100 #define LPCIB_PCI_SND_DEC 0xe2 101 #define LPCIB_PCI_FWH_DEC_EN1 0xe3 102 #define LPCIB_PCI_GEN1_DEC 0xe4 103 #define LPCIB_PCI_LPC_EN 0xe6 104 #define LPCIB_PCI_FWH_SEL1 0xe8 105 #define LPCIB_PCI_GEN2_DEC 0xec 106 #define LPCIB_PCI_FWH_SEL2 0xee 107 #define LPCIB_PCI_FWH_DEC_EN2 0xf0 108 #define LPCIB_PCI_FUNC_DIS 0xf2 109 110 /* 111 * Power management I/O registers 112 * (offset from PMBASE) 113 */ 114 #define PMC_PM1_STS 0x00 /* ACPI PM1a_EVT_BLK fixed event status */ 115 #define PMC_PM1_EN 0x02 /* ACPI PM1a_EVT_BLK fixed event enable */ 116 #define PMC_PM1_CNT 0x04 /* ACPI PM1a_CNT_BLK */ 117 #define PMC_PM1_TMR 0x08 /* ACPI PMTMR_BLK power mgmt timer */ 118 #define PMC_PROC_CNT 0x10 /* ACPI P_BLK processor control */ 119 #define PMC_LV2 0x14 /* ACPI P_BLK processor C2 control */ 120 #define PMC_PM_CTRL 0x20 /* ACPI Power Management Control */ 121 # define PMC_PM_SS_STATE_LOW 0x01 /* SpeedStep Low Power State */ 122 #define PMC_GPE0_STS 0x28 /* ACPI GPE0_BLK GPE0 status */ 123 #define PMC_GPE0_EN 0x2c /* ACPI GPE0_BLK GPE0 enable */ 124 #define PMC_SMI_EN 0x30 125 # define PMC_SMI_EN_INTEL_USB2_EN (1 << 18) 126 # define PMC_SMI_EN_LEGACY_USB2_EN (1 << 17) 127 # define PMC_SMI_EN_PERIODIC_EN (1 << 14) 128 # define PMC_SMI_EN_TCO_EN (1 << 13) 129 # define PMC_SMI_EN_MCSMI_EN (1 << 11) 130 # define PMC_SMI_EN_BIOS_RLS (1 << 7) 131 # define PMC_SMI_EN_SWSMI_TMR_EN (1 << 6) 132 # define PMC_SMI_EN_APMC_EN (1 << 5) 133 # define PMC_SMI_EN_SLP_SMI_EN (1 << 4) 134 # define PMC_SMI_EN_LEGACY_USB_EN (1 << 3) 135 # define PMC_SMI_EN_BIOS_EN (1 << 2) 136 # define PMC_SMI_EN_EOS (1 << 1) 137 # define PMC_SMI_EN_GBL_SMI_EN (1 << 0) 138 #define PMC_SMI_STS 0x34 139 #define PMC_ALT_GP_SMI_EN 0x38 140 #define PMC_ALT_GP_SMI_STS 0x3a 141 #define PMC_MON_SMI 0x40 142 #define PMC_DEVACT_STS 0x44 143 #define PMC_DEVTRAP_EN 0x48 144 #define PMC_BUS_ADDR_TRACK 0x4c 145 #define PMC_BUS_CYC_TRACK 0x4e 146 #define PMC_PM_SS_CNTL 0x50 /* SpeedStep control */ 147 # define PMC_PM_SS_CNTL_ARB_DIS 0x01 /* disable arbiter */ 148 #define PMC_TCO_BASE 0x60 149 150 /* 151 * General Purpose I/O Registers 152 * (offset from GPIO_BASE) 153 */ 154 #define LPCIB_GPIO_GPIO_USE_SEL 0x00 155 #define LPCIB_GPIO_GP_IO_SEL 0x04 156 #define LPCIB_GPIO_GP_LVL 0x0c 157 #define LPCIB_GPIO_GPO_TTL 0x14 158 #define LPCIB_GPIO_GPO_BLINK 0x18 159 #define LPCIB_GPIO_GPI_INV 0x2c 160 #define LPCIB_GPIO_GPIO_USE_SEL2 0x30 161 #define LPCIB_GPIO_GP_IO_SEL2 0x34 162 #define LPCIB_GPIO_GP_LVL2 0x38 163 164 /* 165 * SMBus controller registers. 166 */ 167 168 /* PCI configuration registers */ 169 #define SMB_BASE 0x20 /* SMBus base address */ 170 #define SMB_HOSTC 0x40 /* host configuration */ 171 #define SMB_HOSTC_HSTEN (1 << 0) /* enable host controller */ 172 #define SMB_HOSTC_SMIEN (1 << 1) /* generate SMI */ 173 #define SMB_HOSTC_I2CEN (1 << 2) /* enable I2C commands */ 174 #define SMB_TCOBASE 0x50 /* TCO Base Address */ 175 #define SMB_TCOBASE_TCOBA __BITS(15,5) /* TCO Base Address */ 176 #define SMB_TCOBASE_IOS __BIT(0) /* I/O Space */ 177 #define SMB_TCOCTL 0x54 /* TCO Control */ 178 #define SMB_TCOCTL_TCO_BASE_EN __BIT(8) /* TCO Base Enable */ 179 180 /* SMBus I/O registers */ 181 #define SMB_HS 0x00 /* host status */ 182 #define SMB_HS_BUSY (1 << 0) /* running a command */ 183 #define SMB_HS_INTR (1 << 1) /* command completed */ 184 #define SMB_HS_DEVERR (1 << 2) /* command error */ 185 #define SMB_HS_BUSERR (1 << 3) /* transaction collision */ 186 #define SMB_HS_FAILED (1 << 4) /* failed bus transaction */ 187 #define SMB_HS_SMBAL (1 << 5) /* SMBALERT# asserted */ 188 #define SMB_HS_INUSE (1 << 6) /* bus semaphore */ 189 #define SMB_HS_BDONE (1 << 7) /* byte received/transmitted */ 190 #define SMB_HS_BITS "\020\001BUSY\002INTR\003DEVERR\004BUSERR\005FAILED\006SMBAL\007INUSE\010BDONE" 191 #define SMB_HC 0x02 /* host control */ 192 #define SMB_HC_INTREN (1 << 0) /* enable interrupts */ 193 #define SMB_HC_KILL (1 << 1) /* kill current transaction */ 194 #define SMB_HC_CMD_QUICK (0 << 2) /* QUICK command */ 195 #define SMB_HC_CMD_BYTE (1 << 2) /* BYTE command */ 196 #define SMB_HC_CMD_BDATA (2 << 2) /* BYTE DATA command */ 197 #define SMB_HC_CMD_WDATA (3 << 2) /* WORD DATA command */ 198 #define SMB_HC_CMD_PCALL (4 << 2) /* PROCESS CALL command */ 199 #define SMB_HC_CMD_BLOCK (5 << 2) /* BLOCK command */ 200 #define SMB_HC_CMD_I2CREAD (6 << 2) /* I2C READ command */ 201 #define SMB_HC_CMD_BLOCKP (7 << 2) /* BLOCK PROCESS command */ 202 #define SMB_HC_LASTB (1 << 5) /* last byte in block */ 203 #define SMB_HC_START (1 << 6) /* start transaction */ 204 #define SMB_HC_PECEN (1 << 7) /* enable PEC */ 205 #define SMB_HCMD 0x03 /* host command */ 206 #define SMB_TXSLVA 0x04 /* transmit slave address */ 207 #define SMB_TXSLVA_READ (1 << 0) /* read direction */ 208 #define SMB_TXSLVA_ADDR(x) (((x) & 0x7f) << 1) /* 7-bit address */ 209 #define SMB_HD0 0x05 /* host data 0 */ 210 #define SMB_HD1 0x06 /* host data 1 */ 211 #define SMB_HBDB 0x07 /* host block data byte */ 212 #define SMB_PEC 0x08 /* PEC data */ 213 #define SMB_RXSLVA 0x09 /* receive slave address */ 214 #define SMB_SD 0x0a /* receive slave data */ 215 #define SMB_SD_MSG0(x) ((x) & 0xff) /* data message byte 0 */ 216 #define SMB_SD_MSG1(x) ((x) >> 8) /* data message byte 1 */ 217 #define SMB_AS 0x0c /* auxiliary status */ 218 #define SMB_AS_CRCE (1 << 0) /* CRC error */ 219 #define SMB_AS_TCO (1 << 1) /* advanced TCO mode */ 220 #define SMB_AC 0x0d /* auxiliary control */ 221 #define SMB_AC_AAC (1 << 0) /* automatically append CRC */ 222 #define SMB_AC_E32B (1 << 1) /* enable 32-byte buffer */ 223 #define SMB_SMLPC 0x0e /* SMLink pin control */ 224 #define SMB_SMLPC_LINK0 (1 << 0) /* SMLINK0 pin state */ 225 #define SMB_SMLPC_LINK1 (1 << 1) /* SMLINK1 pin state */ 226 #define SMB_SMLPC_CLKC (1 << 2) /* SMLINK0 pin is untouched */ 227 #define SMB_SMBPC 0x0f /* SMBus pin control */ 228 #define SMB_SMBPC_CLK (1 << 0) /* SMBCLK pin state */ 229 #define SMB_SMBPC_DATA (1 << 1) /* SMBDATA pin state */ 230 #define SMB_SMBPC_CLKC (1 << 2) /* SMBCLK pin is untouched */ 231 #define SMB_SS 0x10 /* slave status */ 232 #define SMB_SS_HN (1 << 0) /* Host Notify command */ 233 #define SMB_SCMD 0x11 /* slave command */ 234 #define SMB_SCMD_INTREN (1 << 0) /* enable interrupts on HN */ 235 #define SMB_SCMD_WKEN (1 << 1) /* wake on HN */ 236 #define SMB_SCMD_SMBALDS (1 << 2) /* disable SMBALERT# intr */ 237 #define SMB_NDADDR 0x14 /* notify device address */ 238 #define SMB_NDADDR_ADDR(x) ((x) >> 1) /* 7-bit address */ 239 #define SMB_NDLOW 0x16 /* notify data low byte */ 240 #define SMB_NDHIGH 0x17 /* notify data high byte */ 241 242 /* ICH Chipset Configuration Registers (ICH6 and newer) */ 243 #define LPCIB_RCBA 0xf0 244 #define LPCIB_RCBA_EN 0x00000001 245 #define LPCIB_RCBA_SIZE 0x00004000 246 #define LPCIB_GCS_OFFSET 0x3410 247 #define LPCIB_GCS_NO_REBOOT 0x20 248 #define LPCIB_RCBA_HPTC 0x00003404 249 #define LPCIB_RCBA_HPTC_EN 0x00000080 250 #define LPCIB_RCBA_HPTC_WIN_MASK 0x00000003 251 #define LPCIB_RCBA_HPTC_0000 0x00000000 252 #define LPCIB_RCBA_HPTC_0000_BASE 0xfed00000 253 #define LPCIB_RCBA_HPTC_1000 0x00000001 254 #define LPCIB_RCBA_HPTC_1000_BASE 0xfed01000 255 #define LPCIB_RCBA_HPTC_2000 0x00000002 256 #define LPCIB_RCBA_HPTC_2000_BASE 0xfed02000 257 #define LPCIB_RCBA_HPTC_3000 0x00000003 258 #define LPCIB_RCBA_HPTC_3000_BASE 0xfed03000 259 260 /* 261 * System management TCO registers 262 */ 263 #define TCO_RLD 0x00 264 #define TCO_TMR 0x01 /* ICH5 and older */ 265 # define TCO_TMR_MASK 0x3f 266 #define TCO_DAT_IN 0x02 267 #define TCO_DAT_OUT 0x03 268 #define TCO1_STS 0x04 269 # define TCO1_STS_TIMEOUT 0x08 270 #define TCO2_STS 0x06 271 # define TCO2_STS_BOOT_STS 0x04 272 # define TCO2_STS_SECONDS_TO_STS 0x02 273 #define TCO1_CNT 0x08 274 # define TCO1_CNT_TCO_LOCK (1 << 12) 275 # define TCO1_CNT_TCO_TMR_HLT (1 << 11) 276 # define TCO1_CNT_SEND_NOW (1 << 10) 277 # define TCO1_CNT_NMI2SMI_EN (1 << 9) 278 # define TCO1_CNT_NMI_NOW (1 << 8) 279 #define TCO2_CNT 0x0a 280 #define TCO_MESSAGE1 0x0c 281 #define TCO_MESSAGE2 0x0d 282 #define TCO_WDSTATUS 0x0e 283 #define TCO_SW_IRQ_GEN 0x10 284 #define TCO_TMR2 0x12 /* ICH6 and newer */ 285 #define TCO_REGSIZE 0x20 286 287 /* 288 * TCO timer tick. ICH datasheets say: 289 * - The timer is clocked at approximately 0.6 seconds 290 * - 6 bit; values of 0-3 will be ignored and should not be attempted 291 */ 292 static __inline int 293 tcotimer_tick_to_second(int ltick) 294 { 295 return ltick * 6 / 10; 296 } 297 298 static __inline int 299 tcotimer_second_to_tick(int ltick) 300 { 301 return ltick * 10 / 6; 302 } 303 304 #define TCOTIMER_MIN_TICK 4 305 #define TCOTIMER2_MIN_TICK 2 306 #define TCOTIMER_MAX_TICK 0x3f /* 39 seconds max */ 307 #define TCOTIMER2_MAX_TICK 0x265 /* 613 seconds max */ 308 309 /* 310 * P2SB: Primary to Sideband Bridge, PCI configuration registers 311 */ 312 #define P2SB_SBREG_BAR 0x10 /* Sideband Register Access BAR */ 313 #define P2SB_SBREG_BARH 0x14 /* Sideband BAR High DWORD */ 314 #define P2SB_P2SBC 0xe0 /* P2SB Control */ 315 #define P2SB_P2SBC_HIDE __BIT(8) /* Hide Device */ 316 317 /* 318 * PCH Private Configuration Space -- Sideband 319 */ 320 #define SB_PORTID __BITS(23,16) 321 #define SB_PORTID_SMBUS 0xc6 322 323 #define SB_PORT(id) __SHIFTIN(id, SB_PORTID) 324 325 #define SB_SMBUS_BASE (SB_PORT(SB_PORTID_SMBUS) + 0x00) 326 #define SB_SMBUS_SIZE 0x14 327 328 #define SB_SMBUS_TCOCFG 0x00 /* TCO Configuration */ 329 #define SB_SMBUS_TCOCFG_IE __BIT(7) /* TCO IRQ Enable */ 330 #define SB_SMBUS_TCOCFG_IS __BITS(2,0) /* TCO IRQ Select */ 331 #define SB_SMBUS_TCOCFG_IS_IRQ9 0 /* maps to 8259 and APIC */ 332 #define SB_SMBUS_TCOCFG_IS_IRQ10 1 /* maps to 8259 and APIC */ 333 #define SB_SMBUS_TCOCFG_IS_IRQ11 2 /* maps to 8259 and APIC */ 334 #define SB_SMBUS_TCOCFG_IS_IRQ20 4 /* maps to APIC */ 335 #define SB_SMBUS_TCOCFG_IS_IRQ21 3 /* maps to APIC */ 336 #define SB_SMBUS_TCOCFG_IS_IRQ22 4 /* maps to APIC */ 337 #define SB_SMBUS_TCOCFG_IS_IRQ23 5 /* maps to APIC */ 338 #define SB_SMBUS_GC 0x0c /* General Control */ 339 #define SB_SMBUS_GC_NR __BIT(1) /* No Reboot */ 340 #define SB_SMBUS_GC_FD __BIT(0) /* Function Disable */ 341 #define SB_SMBUS_PCE 0x10 /* Power Control Enable */ 342 #define SB_SMBUS_PCE_SE __BIT(3) /* Sleep Enable */ 343 #define SB_SMBUS_PCE_D3HE __BIT(2) /* D3-Hot Enable */ 344 #define SB_SMBUS_PCE_I3E __BIT(1) /* I3 Enable */ 345 #define SB_SMBUS_PCE_PMCRE __BIT(0) /* PMC Request Enable */ 346 347 #endif /* _DEV_IC_I82801LPCREG_H_ */ 348
Indexes created Tue Sep 30 07:10:03 GMT 2025