1 2 #ifdef HAVE_CONFIG_H 3 #include "config.h" 4 #endif 5 6 #include "xf86.h" 7 #include "xf86_OSproc.h" 8 #include "xf86Pci.h" 9 #include "tdfx.h" 10 11 #define AACLKOUTDEL 0x2 12 #define CFGSWAPALGORITHM 0x1 13 14 /* #define RD_ABORT_ERROR */ 15 #define H3VDD 16 17 Bool TDFXDisableSLI(TDFXPtr pTDFX) 18 { 19 int i; 20 uint32_t v; 21 22 for (i=0; i<pTDFX->numChips; i++) { 23 PCI_READ_LONG(v, CFG_INIT_ENABLE, i); 24 PCI_WRITE_LONG(v & ~(CFG_SNOOP_MEMBASE0 | CFG_SNOOP_EN | 25 CFG_SNOOP_MEMBASE0_EN | 26 CFG_SNOOP_MEMBASE1_EN | CFG_SNOOP_SLAVE | 27 CFG_SNOOP_FBIINIT_WR_EN | CFG_SWAP_ALGORITHM | 28 CFG_SWAP_QUICK), 29 CFG_INIT_ENABLE, i); 30 31 PCI_READ_LONG(v, CFG_SLI_LFB_CTRL, i); 32 PCI_WRITE_LONG(v & ~(CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN | 33 CFG_SLI_RD_EN), 34 CFG_SLI_LFB_CTRL, i); 35 #ifdef H3VDD 36 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 0); 37 pTDFX->writeChipLong(pTDFX, i, SST_3D_AACTRL, 0); 38 #endif 39 40 PCI_READ_LONG(v, CFG_AA_LFB_CTRL, i); 41 PCI_WRITE_LONG(v & ~(CFG_AA_LFB_CPU_WR_EN | CFG_AA_LFB_DPTCH_WR_EN | 42 CFG_AA_LFB_RD_EN), 43 CFG_AA_LFB_CTRL, i); 44 45 PCI_READ_LONG(v, CFG_SLI_AA_MISC, i); 46 PCI_WRITE_LONG((v & ~CFG_VGA_VSYNC_OFFSET) | 47 (0 << CFG_VGA_VSYNC_OFFSET_PIXELS_SHIFT) | 48 (0 << CFG_VGA_VSYNC_OFFSET_CHARS_SHIFT) | 49 (0 << CFG_VGA_VSYNC_OFFSET_HXTRA_SHIFT), 50 CFG_SLI_AA_MISC, i); 51 52 PCI_WRITE_LONG(0, CFG_VIDEO_CTRL0, i); 53 PCI_WRITE_LONG(0, CFG_VIDEO_CTRL1, i); 54 PCI_WRITE_LONG(0, CFG_VIDEO_CTRL2, i); 55 56 if (pTDFX->numChips>1) { 57 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 58 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 59 (v&~(SST_PCI_DISABLE_IO|SST_PCI_DISABLE_MEM| 60 SST_PCI_RETRY_INTERVAL)) | 61 (0<<SST_PCI_RETRY_INTERVAL_SHIFT) | 62 SST_PCI_FORCE_FB_HIGH); 63 } else { 64 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 65 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 66 (v&~(SST_PCI_DISABLE_IO|SST_PCI_DISABLE_MEM| 67 SST_PCI_RETRY_INTERVAL)) | 68 (0<<SST_PCI_RETRY_INTERVAL_SHIFT)); 69 } 70 71 #if 0 72 if (i>0) { 73 pTDFX->writeChipLong(pTDFX, i, DACMODE, 74 SST_DAC_DPMS_ON_VSYNC | SST_DAC_DPMS_ON_HSYNC); 75 v=pTDFX->readChipLong(pTDFX, i, VIDPROCCFG); 76 pTDFX->writeChipLong(pTDFX, i, VIDPROCCFG, v&~SST_VIDEO_PROCESSOR_EN); 77 } 78 #endif 79 } 80 return TRUE; 81 } 82 83 Bool TDFXSetupSLI(ScrnInfoPtr pScrn, Bool sliEnable, int aaSamples) 84 { 85 TDFXPtr pTDFX; 86 uint32_t v; 87 int i, sliLines, sliLinesLog2, nChipsLog2; 88 int sli_renderMask, sli_compareMask, sli_scanMask; 89 int sliAnalog, dwFormat; 90 91 pTDFX=TDFXPTR(pScrn); 92 if (pScrn->depth == 24 || pScrn->depth==32) { 93 if ((aaSamples == 4) && (pTDFX->numChips>1)) { 94 pTDFX->pixelFormat=GR_PIXFMT_AA_4_ARGB_8888; 95 } else if (aaSamples >= 2) { 96 pTDFX->pixelFormat=GR_PIXFMT_AA_2_ARGB_8888; 97 } else { 98 pTDFX->pixelFormat=GR_PIXFMT_ARGB_8888; 99 } 100 } else if (pScrn->depth == 16) { 101 if ((aaSamples == 4) && (pTDFX->numChips>1)) { 102 pTDFX->pixelFormat=GR_PIXFMT_AA_4_RGB_565; 103 } else if (aaSamples >= 2) { 104 pTDFX->pixelFormat=GR_PIXFMT_AA_2_RGB_565; 105 } else { 106 pTDFX->pixelFormat=GR_PIXFMT_RGB_565; 107 } 108 } else if (pScrn->depth == 8) { 109 pTDFX->pixelFormat=GR_PIXFMT_I_8; 110 } 111 if (!sliEnable && !aaSamples) { /* Turn off */ 112 return TDFXDisableSLI(pTDFX); 113 } 114 115 if (pScrn->virtualY>768) sliLinesLog2=5; 116 else sliLinesLog2=4; 117 sliLines=1<<sliLinesLog2; 118 if (pScrn->virtualY*pScrn->virtualX>1600*1024) sliAnalog=1; 119 else sliAnalog=0; 120 /* XXX We need to avoid SLI in double scan modes somehow */ 121 122 switch (pTDFX->numChips) { 123 case 1: 124 nChipsLog2=0; 125 break; 126 case 2: 127 nChipsLog2=1; 128 break; 129 case 4: 130 nChipsLog2=2; 131 break; 132 default: 133 return FALSE; 134 /* XXX Huh? Unsupported configuration */ 135 } 136 137 for (i=0; i<pTDFX->numChips; i++) { 138 /* Do we want to set these differently for a VIA board? */ 139 v=pTDFX->readChipLong(pTDFX, i, PCIINIT0); 140 v=(v&~(SST_PCI_RETRY_INTERVAL|SST_PCI_FORCE_FB_HIGH)) | 141 SST_PCI_READ_WS | SST_PCI_WRITE_WS | 142 SST_PCI_DISABLE_IO | SST_PCI_DISABLE_MEM | 143 (5<<SST_PCI_RETRY_INTERVAL_SHIFT); 144 pTDFX->writeChipLong(pTDFX, i, PCIINIT0, 145 (v&~(SST_PCI_RETRY_INTERVAL|SST_PCI_FORCE_FB_HIGH)) | 146 SST_PCI_READ_WS | SST_PCI_WRITE_WS | 147 SST_PCI_DISABLE_IO | SST_PCI_DISABLE_MEM | 148 (5<<SST_PCI_RETRY_INTERVAL_SHIFT)); 149 v=pTDFX->readChipLong(pTDFX, i, TMUGBEINIT); 150 pTDFX->writeChipLong(pTDFX, i, TMUGBEINIT, 151 (v&~(SST_AA_CLK_DELAY | SST_AA_CLK_INVERT)) | 152 (AACLKOUTDEL<<SST_AA_CLK_DELAY_SHIFT) | 153 SST_AA_CLK_INVERT); 154 155 if (pTDFX->numChips>1) { 156 PCI_READ_LONG(v, CFG_INIT_ENABLE, i); 157 PCI_WRITE_LONG(v | 158 (CFGSWAPALGORITHM << CFG_SWAPBUFFER_ALGORITHM_SHIFT) | 159 CFG_SWAP_ALGORITHM | ((!i)? CFG_SWAP_MASTER : 0), 160 CFG_INIT_ENABLE, i); 161 if (!i) { 162 PCI_READ_LONG(v, CFG_INIT_ENABLE, i); 163 PCI_WRITE_LONG(v | CFG_SNOOP_EN, CFG_INIT_ENABLE, i); 164 PCI_READ_LONG(v, CFG_PCI_DECODE, i); 165 } else { 166 PCI_READ_LONG(v, CFG_INIT_ENABLE, i); 167 168 v = (v & ~CFG_SNOOP_MEMBASE0) | CFG_SNOOP_EN | 169 CFG_SNOOP_MEMBASE0_EN | CFG_SNOOP_MEMBASE1_EN | 170 CFG_SNOOP_SLAVE | CFG_SNOOP_FBIINIT_WR_EN | 171 (((pTDFX->MMIOAddr[0]>>22)&0x3ff)<<CFG_SNOOP_MEMBASE0_SHIFT) | 172 ((pTDFX->numChips>2)? CFG_SWAP_QUICK : 0); 173 174 PCI_WRITE_LONG(v, CFG_INIT_ENABLE, i); 175 176 PCI_READ_LONG(v, CFG_PCI_DECODE, i); 177 v = (v & ~CFG_SNOOP_MEMBASE1) | 178 ((pTDFX->LinearAddr[0]>>22)&0x3ff)<<CFG_SNOOP_MEMBASE1_SHIFT; 179 PCI_WRITE_LONG(v, CFG_PCI_DECODE, i); 180 } 181 } 182 183 if (sliEnable && aaSamples<4) { 184 /* SLI is on and we're using less than 4 AA samples */ 185 sli_renderMask = (pTDFX->numChips-1) << sliLinesLog2; 186 sli_compareMask = i << sliLinesLog2; 187 sli_scanMask = sliLines - 1; 188 v = (sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 189 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 190 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 191 (nChipsLog2 << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT) | 192 CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN; 193 #ifndef RD_ABORT_ERROR 194 v|=CFG_SLI_RD_EN; 195 #endif 196 PCI_WRITE_LONG(v, CFG_SLI_LFB_CTRL, i); 197 198 #ifdef H3VDD 199 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 200 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 201 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 202 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 203 (nChipsLog2 << SLICTL_3D_NUMCHIPS_LOG2_SHIFT) | 204 SLICTL_3D_EN); 205 #endif 206 } else if (!sliEnable && aaSamples) { 207 /* SLI is off and AA is on */ 208 sli_renderMask = 0; 209 sli_compareMask = 0; 210 sli_scanMask = 0; 211 PCI_WRITE_LONG((sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 212 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 213 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 214 (0x0 << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT), 215 CFG_SLI_LFB_CTRL, i); 216 #ifdef H3VDD 217 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 218 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 219 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 220 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 221 (0 << SLICTL_3D_NUMCHIPS_LOG2_SHIFT)); 222 #endif 223 } else { 224 /* SLI is on && aaSamples=4 */ 225 sli_renderMask = ((pTDFX->numChips>>1)-1) << sliLinesLog2; 226 sli_compareMask = (i>>1) << sliLinesLog2; 227 sli_scanMask = sliLines - 1; 228 v = (sli_renderMask << CFG_SLI_LFB_RENDERMASK_SHIFT) | 229 (sli_compareMask << CFG_SLI_LFB_COMPAREMASK_SHIFT) | 230 (sli_scanMask << CFG_SLI_LFB_SCANMASK_SHIFT) | 231 ((nChipsLog2-1) << CFG_SLI_LFB_NUMCHIPS_LOG2_SHIFT) | 232 CFG_SLI_LFB_CPU_WR_EN | CFG_SLI_LFB_DPTCH_WR_EN; 233 #ifndef RD_ABORT_ERROR 234 v|=CFG_SLI_RD_EN; 235 #endif 236 PCI_WRITE_LONG(v, CFG_SLI_LFB_CTRL, i); 237 #ifdef H3VDD 238 pTDFX->writeChipLong(pTDFX, i, SST_3D_SLICTRL, 239 (sli_renderMask << SLICTL_3D_RENDERMASK_SHIFT) | 240 (sli_compareMask << SLICTL_3D_COMPAREMASK_SHIFT) | 241 (sli_scanMask << SLICTL_3D_SCANMASK_SHIFT) | 242 ((nChipsLog2-1) << SLICTL_3D_NUMCHIPS_LOG2_SHIFT) | 243 SLICTL_3D_EN); 244 #endif 245 } 246 247 TDFXSetLFBConfig(pTDFX); 248 if (pTDFX->cpp==2) dwFormat = CFG_AA_LFB_RD_FORMAT_16BPP; 249 else dwFormat = CFG_AA_LFB_RD_FORMAT_32BPP; 250 if (pTDFX->numChips==2 && !sliEnable && aaSamples==2) 251 dwFormat|=CFG_AA_LFB_RD_DIVIDE_BY_4; 252 /* Thess are wrong, because we don't know where the secondary buffers 253 are located */ 254 pTDFX->writeChipLong(pTDFX, i, CFG_AA_LFB_CTRL, 255 (pScrn->videoRam<<10 /* 2nd buf */ << CFG_AA_BASEADDR_SHIFT) | 256 CFG_AA_LFB_CPU_WR_EN | CFG_AA_LFB_DPTCH_WR_EN | 257 CFG_AA_LFB_RD_EN | dwFormat | 258 ((aaSamples==4)?CFG_AA_LFB_RD_DIVIDE_BY_4:0)); 259 pTDFX->writeChipLong(pTDFX, i, CFG_AA_ZBUFF_APERTURE, 260 ((pTDFX->depthOffset>>12)<<CFG_AA_DEPTH_BUFFER_BEG_SHIFT) | 261 ((pScrn->videoRam>>2)<<CFG_AA_DEPTH_BUFFER_END_SHIFT)); 262 263 if (pTDFX->numChips>1 && i && (aaSamples || sliEnable)) { 264 int vsyncOffsetPixels, vsyncOffsetChars, vsyncOffsetHXtra; 265 266 if (aaSamples || (pTDFX->numChips==4 && sliEnable && aaSamples==4 && 267 sliAnalog && i==3)) { 268 vsyncOffsetPixels=7; 269 vsyncOffsetChars=4; 270 vsyncOffsetHXtra=0; 271 } else { 272 vsyncOffsetPixels=7; 273 vsyncOffsetChars=5; 274 vsyncOffsetHXtra=0; 275 } 276 PCI_READ_LONG(v, CFG_SLI_AA_MISC, i); 277 PCI_WRITE_LONG((v & ~CFG_VGA_VSYNC_OFFSET) | 278 (vsyncOffsetPixels << CFG_VGA_VSYNC_OFFSET_PIXELS_SHIFT) | 279 (vsyncOffsetChars << CFG_VGA_VSYNC_OFFSET_CHARS_SHIFT) | 280 (vsyncOffsetHXtra << CFG_VGA_VSYNC_OFFSET_HXTRA_SHIFT), 281 CFG_SLI_AA_MISC, i); 282 } 283 if (pTDFX->numChips==1 && aaSamples) { 284 /* 1 chip 2 AA */ 285 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 286 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 287 CFG_VIDEO_OTHERMUX_SEL_PIPE<<CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT | 288 CFG_DIVIDE_VIDEO_BY_2, 289 CFG_VIDEO_CTRL0, i); 290 PCI_WRITE_LONG(0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT | 291 0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT | 292 0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT | 293 0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT, 294 CFG_VIDEO_CTRL1, i); 295 PCI_WRITE_LONG(0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT | 296 0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT, 297 CFG_VIDEO_CTRL2, i); 298 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==4 && 299 !sliAnalog) { 300 /* 2 chips 4 digital AA */ 301 if (!i) { 302 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 303 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 304 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 305 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 306 CFG_DIVIDE_VIDEO_BY_4, 307 CFG_VIDEO_CTRL0, i); 308 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 309 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 310 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 311 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 312 CFG_VIDEO_CTRL1, i); 313 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 314 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 315 CFG_VIDEO_CTRL2, i); 316 } else { 317 PCI_WRITE_LONG((CFG_ENHANCED_VIDEO_EN | 318 CFG_ENHANCED_VIDEO_SLV | 319 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 320 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 321 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 322 CFG_DIVIDE_VIDEO_BY_1), 323 CFG_VIDEO_CTRL0, i); 324 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 325 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 326 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 327 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 328 CFG_VIDEO_CTRL1, i); 329 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 330 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 331 CFG_VIDEO_CTRL2, i); 332 } 333 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==4 && sliAnalog) { 334 /* 2 chips 4 analog AA */ 335 if (!i) { 336 PCI_WRITE_LONG((CFG_ENHANCED_VIDEO_EN | 337 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 338 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 339 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 340 CFG_DIVIDE_VIDEO_BY_4), 341 CFG_VIDEO_CTRL0, i); 342 } else { 343 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 344 CFG_ENHANCED_VIDEO_SLV | 345 CFG_DAC_HSYNC_TRISTATE | 346 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 347 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 348 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 349 CFG_DIVIDE_VIDEO_BY_4, 350 CFG_VIDEO_CTRL0, i); 351 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 352 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 353 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 354 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 355 CFG_VIDEO_CTRL1, i); 356 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 357 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 358 CFG_VIDEO_CTRL2, i); 359 } 360 } else if (pTDFX->numChips==2 && sliEnable && !aaSamples && !sliAnalog) { 361 /* 2 chips 2 digital SLI */ 362 if (!i) { 363 PCI_WRITE_LONG((CFG_ENHANCED_VIDEO_EN | 364 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 365 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 366 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 367 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 368 CFG_DIVIDE_VIDEO_BY_1), 369 CFG_VIDEO_CTRL0, i); 370 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 371 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 372 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 373 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 374 CFG_VIDEO_CTRL1, i); 375 PCI_WRITE_LONG(((0x0<<sliLinesLog2) << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 376 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 377 CFG_VIDEO_CTRL2, i); 378 } else { 379 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 380 CFG_ENHANCED_VIDEO_SLV | 381 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 382 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 383 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 384 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 385 CFG_DIVIDE_VIDEO_BY_1, 386 CFG_VIDEO_CTRL0, i); 387 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 388 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 389 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 390 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 391 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 392 CFG_VIDEO_CTRL1, i); 393 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 394 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 395 ((i<<sliLinesLog2) << 396 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 397 CFG_VIDEO_CTRL2, i); 398 } 399 } else if (pTDFX->numChips>=2 && sliEnable && !aaSamples && sliAnalog) { 400 /* 2 or 4 chips 2/4 analog SLI */ 401 if (!i) { 402 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 403 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 404 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 405 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 406 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 407 CFG_DIVIDE_VIDEO_BY_1, 408 CFG_VIDEO_CTRL0, i); 409 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 410 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 411 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 412 (((pTDFX->numChips-1)<<sliLinesLog2) << 413 CFG_SLI_RENDERMASK_CRT_SHIFT) | 414 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 415 CFG_VIDEO_CTRL1, i); 416 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 417 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 418 CFG_VIDEO_CTRL2, i); 419 } else { 420 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 421 CFG_ENHANCED_VIDEO_SLV | 422 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 423 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 424 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 425 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 426 CFG_DIVIDE_VIDEO_BY_1, 427 CFG_VIDEO_CTRL0, i); 428 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 429 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 430 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 431 (((pTDFX->numChips-1)<<sliLinesLog2) << 432 CFG_SLI_RENDERMASK_CRT_SHIFT) | 433 ((i<<sliLinesLog2) << 434 CFG_SLI_COMPAREMASK_CRT_SHIFT), 435 CFG_VIDEO_CTRL1, i); 436 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 437 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 438 CFG_VIDEO_CTRL2, i); 439 } 440 } else if (pTDFX->numChips==2 && sliEnable && aaSamples==2 && !sliAnalog) { 441 /* 2 chips 2 AA 2 digital SLI */ 442 if (!i) { 443 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 444 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 445 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 446 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 447 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 448 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 449 CFG_DIVIDE_VIDEO_BY_2, 450 CFG_VIDEO_CTRL0, i); 451 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 452 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 453 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 454 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 455 CFG_VIDEO_CTRL1, i); 456 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 457 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 458 CFG_VIDEO_CTRL2, i); 459 } else { 460 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 461 CFG_ENHANCED_VIDEO_SLV | 462 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 463 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 464 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 465 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 466 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 467 CFG_DIVIDE_VIDEO_BY_1, 468 CFG_VIDEO_CTRL0, i); 469 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 470 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 471 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 472 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 473 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 474 CFG_VIDEO_CTRL1, i); 475 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 476 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 477 ((i<<sliLinesLog2) << 478 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 479 CFG_VIDEO_CTRL2, i); 480 } 481 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==2 && !sliAnalog) { 482 /* 2 chips 2 digital AA */ 483 if (!i) { 484 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 485 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 486 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 487 CFG_DIVIDE_VIDEO_BY_2, 488 CFG_VIDEO_CTRL0, i); 489 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 490 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 491 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 492 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 493 CFG_VIDEO_CTRL1, i); 494 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 495 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 496 CFG_VIDEO_CTRL2, i); 497 } else { 498 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 499 CFG_ENHANCED_VIDEO_SLV | 500 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 501 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 502 CFG_DIVIDE_VIDEO_BY_1, 503 CFG_VIDEO_CTRL0, i); 504 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 505 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 506 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 507 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 508 CFG_VIDEO_CTRL1, i); 509 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 510 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 511 CFG_VIDEO_CTRL2, i); 512 } 513 } else if (pTDFX->numChips==2 && !sliEnable && aaSamples==2 && sliAnalog) { 514 /* 2 chips 2 analog AA */ 515 if (!i) { 516 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 517 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 518 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 519 CFG_DIVIDE_VIDEO_BY_2, 520 CFG_VIDEO_CTRL0, i); 521 } else { 522 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 523 CFG_ENHANCED_VIDEO_SLV | 524 CFG_DAC_HSYNC_TRISTATE | 525 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 526 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 527 CFG_DIVIDE_VIDEO_BY_2, 528 CFG_VIDEO_CTRL0, i); 529 } 530 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 531 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 532 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 533 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 534 CFG_VIDEO_CTRL1, i); 535 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 536 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 537 CFG_VIDEO_CTRL2, i); 538 } else if (pTDFX->numChips>=2 && sliEnable && aaSamples==2 && sliAnalog) { 539 /* 2 or 4 chips 2 AA 2 or 4 analog SLI */ 540 if (!i) { 541 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 542 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 543 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 544 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 545 CFG_DIVIDE_VIDEO_BY_2, 546 CFG_VIDEO_CTRL0, i); 547 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 548 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 549 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 550 (((pTDFX->numChips-1)<<sliLinesLog2) << 551 CFG_SLI_RENDERMASK_CRT_SHIFT) | 552 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 553 CFG_VIDEO_CTRL1, i); 554 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 555 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 556 CFG_VIDEO_CTRL2, i); 557 } else { 558 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 559 CFG_ENHANCED_VIDEO_SLV | 560 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 561 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 562 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 563 CFG_DIVIDE_VIDEO_BY_2, 564 CFG_VIDEO_CTRL0, i); 565 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 566 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 567 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 568 (((pTDFX->numChips-1)<<sliLinesLog2) << 569 CFG_SLI_RENDERMASK_CRT_SHIFT) | 570 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 571 CFG_VIDEO_CTRL1, i); 572 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 573 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 574 CFG_VIDEO_CTRL2, i); 575 } 576 } else if (pTDFX->numChips==4 && sliEnable && !aaSamples && !sliAnalog) { 577 /* 4 chips 4 digital SLI */ 578 if (!i) { 579 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 580 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 581 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 582 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 583 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 584 CFG_SLI_AAFIFO_COMPARE_INV | 585 CFG_DIVIDE_VIDEO_BY_1, 586 CFG_VIDEO_CTRL0, i); 587 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 588 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 589 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 590 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 591 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 592 CFG_VIDEO_CTRL1, i); 593 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 594 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 595 ((0x0<<sliLinesLog2) << 596 CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 597 CFG_VIDEO_CTRL2, i); 598 } else { 599 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 600 CFG_ENHANCED_VIDEO_SLV | 601 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 602 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 603 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 604 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 605 CFG_DIVIDE_VIDEO_BY_1, 606 CFG_VIDEO_CTRL0, i); 607 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 608 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 609 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 610 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 611 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 612 CFG_VIDEO_CTRL1, i); 613 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 614 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 615 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 616 CFG_VIDEO_CTRL2, i); 617 } 618 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==2 && !sliAnalog) { 619 /* 4 chips 2 AA 4 digital SLI */ 620 if (!i) { 621 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 622 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 623 (CFG_VIDEO_OTHERMUX_SEL_AAFIFO << 624 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 625 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 626 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 627 CFG_SLI_AAFIFO_COMPARE_INV | 628 CFG_DIVIDE_VIDEO_BY_2, 629 CFG_VIDEO_CTRL0, i); 630 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 631 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 632 (0x0 << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 633 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 634 (0x0 << CFG_SLI_COMPAREMASK_CRT_SHIFT), 635 CFG_VIDEO_CTRL1, i); 636 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 637 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 638 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 639 CFG_VIDEO_CTRL2, i); 640 } else { 641 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 642 CFG_ENHANCED_VIDEO_SLV | 643 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 644 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 645 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 646 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 647 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 648 CFG_DIVIDE_VIDEO_BY_1, 649 CFG_VIDEO_CTRL0, i); 650 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 651 CFG_SLI_RENDERMASK_FETCH_SHIFT) | 652 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 653 (0x0 << CFG_SLI_RENDERMASK_CRT_SHIFT) | 654 (0xff << CFG_SLI_COMPAREMASK_CRT_SHIFT), 655 CFG_VIDEO_CTRL1, i); 656 PCI_WRITE_LONG((((pTDFX->numChips-1)<<sliLinesLog2) << 657 CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 658 ((i<<sliLinesLog2) << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 659 CFG_VIDEO_CTRL2, i); 660 } 661 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && !sliAnalog) { 662 /* 4 chips 4 AA 2 digital SLI */ 663 if (!i) { 664 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 665 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 666 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 667 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 668 CFG_DIVIDE_VIDEO_BY_4, 669 CFG_VIDEO_CTRL0, i); 670 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 671 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 672 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 673 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 674 CFG_VIDEO_CTRL1, i); 675 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 676 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 677 CFG_VIDEO_CTRL2, i); 678 } else if (i==1 || i==3) { 679 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 680 CFG_ENHANCED_VIDEO_SLV | 681 CFG_DAC_HSYNC_TRISTATE | 682 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 683 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 684 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 685 CFG_DIVIDE_VIDEO_BY_1, 686 CFG_VIDEO_CTRL0, i); 687 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 688 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 689 ((0x0<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 690 ((0xff<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 691 CFG_VIDEO_CTRL1, i); 692 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 693 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 694 CFG_VIDEO_CTRL2, i); 695 } else { 696 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 697 CFG_ENHANCED_VIDEO_SLV | 698 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 699 (CFG_VIDEO_OTHERMUX_SEL_PIPE_PLUS_AAFIFO << 700 CFG_VIDEO_OTHERMUX_SEL_FALSE_SHIFT) | 701 CFG_DIVIDE_VIDEO_BY_4, 702 CFG_VIDEO_CTRL0, i); 703 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 704 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 705 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 706 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 707 CFG_VIDEO_CTRL1, i); 708 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 709 (0xff << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 710 CFG_VIDEO_CTRL2, i); 711 } 712 } else if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && sliAnalog) { 713 /* 4 chips 4 AA 2 analog SLI */ 714 if (!i) { 715 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 716 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 717 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 718 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 719 CFG_DIVIDE_VIDEO_BY_4, 720 CFG_VIDEO_CTRL0, i); 721 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 722 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 723 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 724 ((0x0<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 725 CFG_VIDEO_CTRL1, i); 726 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 727 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 728 CFG_VIDEO_CTRL2, i); 729 } else if (i==1 || i==3) { 730 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 731 CFG_ENHANCED_VIDEO_SLV | 732 CFG_DAC_HSYNC_TRISTATE | 733 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 734 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 735 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 736 CFG_DIVIDE_VIDEO_BY_4, 737 CFG_VIDEO_CTRL0, i); 738 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 739 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 740 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 741 ((((i+1)>>2)<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 742 CFG_VIDEO_CTRL1, i); 743 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 744 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 745 CFG_VIDEO_CTRL2, i); 746 } else { 747 PCI_WRITE_LONG(CFG_ENHANCED_VIDEO_EN | 748 CFG_ENHANCED_VIDEO_SLV | 749 CFG_VIDEO_LOCALMUX_DESKTOP_PLUS_OVERLAY | 750 (CFG_VIDEO_OTHERMUX_SEL_PIPE << 751 CFG_VIDEO_OTHERMUX_SEL_TRUE_SHIFT) | 752 CFG_DIVIDE_VIDEO_BY_4, 753 CFG_VIDEO_CTRL0, i); 754 PCI_WRITE_LONG(((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_FETCH_SHIFT) | 755 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_FETCH_SHIFT) | 756 ((0x1<<sliLinesLog2) << CFG_SLI_RENDERMASK_CRT_SHIFT) | 757 ((0x1<<sliLinesLog2) << CFG_SLI_COMPAREMASK_CRT_SHIFT), 758 CFG_VIDEO_CTRL1, i); 759 PCI_WRITE_LONG((0x0 << CFG_SLI_RENDERMASK_AAFIFO_SHIFT) | 760 (0x0 << CFG_SLI_COMPAREMASK_AAFIFO_SHIFT), 761 CFG_VIDEO_CTRL2, i); 762 } 763 } 764 if (pTDFX->numChips==4 && sliEnable && aaSamples==4 && i==3) { 765 PCI_READ_LONG(v, CFG_SLI_AA_MISC, i); 766 PCI_WRITE_LONG(v | CFG_AA_LFB_RD_SLV_WAIT, CFG_SLI_AA_MISC, i); 767 } 768 if (i) { 769 PCI_READ_LONG(v, CFG_VIDEO_CTRL0, i); 770 PCI_WRITE_LONG(v | CFG_VIDPLL_SEL, CFG_VIDEO_CTRL0, i); 771 v=pTDFX->readChipLong(pTDFX, i, MISCINIT1); 772 pTDFX->writeChipLong(pTDFX, i, MISCINIT1, v|SST_POWERDOWN_DAC); 773 } 774 } 775 return TRUE; 776 } 777
Indexes created Sun Jul 05 00:25:41 UTC 2026