1 /* $NetBSD: tdvfbreg.h,v 1.3 2012/07/20 21:31:28 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2012 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 3Dfx Voodoo 2 register definition (mostly from specification) */ 32 33 #ifndef TDVFBREG_H 34 #define TDVFBREG_H 35 36 #define TDV_SST_CLK 50000 /* 50MHz, max is around 60MHz */ 37 #define TDV_CVG_CLK 75000 /* 75MHz, max is around 90MHz */ 38 39 /* CVG PCI config registers */ 40 #define TDV_MM_BAR 0x10 41 42 #define TDV_INITENABLE_REG 0x40 43 #define TDV_INITENABLE_EN_INIT __BIT(0) 44 #define TDV_INITENABLE_EN_FIFO __BIT(1) 45 #define TDV_INITENABLE_REMAPDAC __BIT(2) 46 #define TDV_VCLK_ENABLE_REG 0xC0 /* undocumented? */ 47 #define TDV_VCLK_DISABLE_REG 0xE0 /* undocumented? */ 48 49 /* CVG address space */ 50 #define TDV_OFF_MMREG 0x0 /* memory mapped registers */ 51 #define TDV_OFF_FB 0x400000/* frame buffer */ 52 #define TDV_FB_SIZE 0x3FFFFF/* 4MB */ 53 54 /* CVG registers */ 55 #define TDV_OFF_STATUS 0x0 56 #define TDV_STATUS_FBI_BUSY __BIT(7) /* FBI == CVG Bruce */ 57 #define TDV_STATUS_TREX_BUSY __BIT(8) /* TREX == CVG Chuck */ 58 #define TDV_STATUS_GFX_BUSY __BIT(9) 59 60 #define TDV_OFF_ALPHAMODE 0x10C 61 62 #define TDV_OFF_FBZMODE 0x0110 63 #define TDV_FBZMODE_CLIPPING __BIT(0) 64 #define TDV_FBZMODE_RGB_WR __BIT(9) 65 #define TDV_FBZMODE_ALPHA_WR __BIT(10) 66 #define TDV_FBZMODE_INVERT_Y __BIT(17) 67 68 #define TDV_OFF_LFBMODE 0x0114 69 #define TDV_LFBMODE_565 0 //__BIT(0) 70 #define TDV_LFBMODE_8888 5 71 #define TDV_LFBMODE_PIXPIPE __BIT(8) 72 #define TDV_LFBMODE_WSW_WR __BIT(11) 73 #define TDV_LFBMODE_BSW_WR __BIT(12) 74 #define TDV_LFBMODE_WSW_RD __BIT(15) 75 #define TDV_LFBMODE_BSW_RD __BIT(16) 76 77 #define TDV_OFF_CLIP_LR 0x0118 78 #define TDV_OFF_CLIP_TB 0x011C 79 80 #define TDV_OFF_NOPCMD 0x0120 81 82 #define TDV_OFF_FBIINIT0 0x0210 83 #define TDV_FBIINIT0_VGA_PASS __BIT(0) 84 #define TDV_FBIINIT0_FBI_RST __BIT(1) 85 #define TDV_FBIINIT0_FIFO_RST __BIT(2) 86 87 #define TDV_OFF_FBIINIT1 0x0214 88 #define TDV_FBIINIT1_PCIWAIT __BIT(1) 89 #define TDV_FBIINIT1_LFB_EN __BIT(3) 90 #define TDV_FBIINIT1_TILES_X 4 /* shift, bits 4-7 */ 91 #define TDV_FBIINIT1_VIDEO_RST __BIT(8) 92 #define TDV_FBIINIT1_BLANKING __BIT(12) 93 #define TDV_FBIINIT1_DR_DATA __BIT(13) 94 #define TDV_FBIINIT1_DR_BLANKING __BIT(14) 95 #define TDV_FBIINIT1_DR_HVSYNC __BIT(15) 96 #define TDV_FBIINIT1_DR_DCLK __BIT(16) 97 #define TDV_FBIINIT1_IN_VCLK_2X 0 /* __BIT(17) */ 98 #define TDV_FBIINIT1_VCLK_SRC 20 /* shift, bits 20-21 actually */ 99 #define TDV_FBIINIT1_VCLK_2X 0x2 100 #define TDV_FBIINIT1_TILES_X_MSB 24 101 #define TDV_FBIINIT1_VIDMASK 0x8080010F 102 103 #define TDV_OFF_FBIINIT2 0x0218 104 #define TDV_OFF_DAC_READ TDV_OFF_FBIINIT2 105 #define TDV_FBIINIT2_FAST_RAS __BIT(5) 106 #define TDV_FBIINIT2_DRAM_OE __BIT(6) 107 #define TDV_FBIINIT2_SWB_ALG 0 //__BITS(9,10) /* 00 - based on DAC vsync */ 108 #define TDV_FBIINIT2_FIFO_RDA __BIT(21) 109 #define TDV_FBIINIT2_DRAM_REFR __BIT(22) 110 #define TDV_FBIINIT2_DRAM_REFLD 23 /* shift, bits 23-31 */ 111 #define TDV_FBIINIT2_DRAM_REF16 0x30 /* 16ms */ 112 113 #define TDV_OFF_FBIINIT3 0x021C 114 #define TDV_FBIINIT3_TREX_DIS __BIT(6) 115 116 #define TDV_OFF_FBIINIT4 0x0200 117 #define TDV_FBIINIT4_PCIWAIT __BIT(0) 118 #define TDV_FBIINIT4_LFB_RDA __BIT(1) 119 120 #define TDV_OFF_BACKPORCH 0x0208 121 #define TDV_OFF_VDIMENSIONS 0x020C 122 #define TDV_OFF_HSYNC 0x0220 123 #define TDV_OFF_VSYNC 0x0224 124 125 #define TDV_OFF_DAC_DATA 0x022C 126 #define TDV_DAC_DATA_READ __BIT(11) 127 128 #define TDV_OFF_FBIINIT5 0x0244 129 #define TDV_FBIINIT5_VIDMASK 0xFA40FFFF 130 #define TDV_FBIINIT5_PHSYNC __BIT(23) 131 #define TDV_FBIINIT5_PVSYNC __BIT(24) 132 133 #define TDV_OFF_FBIINIT6 0x0248 134 #define TDV_FBIINIT6_TILES_X_LSB 30 135 136 #define TDV_OFF_BLTSRC 0x02C0 137 #define TDV_OFF_BLTDST 0x02C4 138 #define TDV_OFF_BLTXYSTRIDE 0x02C8 139 #define TDV_OFF_BLTSRCCHROMA 0x02CC 140 #define TDV_OFF_BLTDSTCHROMA 0x02D0 141 #define TDV_OFF_BLTCLIPX 0x02D4 142 #define TDV_OFF_BLTCLIPY 0x02D8 143 #define TDV_OFF_BLTSRCXY 0x02E0 144 #define TDV_OFF_BLTDSTXY 0x02E4 145 #define TDV_OFF_BLTSIZE 0x02E8 146 #define TDV_OFF_BLTROP 0x02EC 147 #define TDV_BLTROP_COPY 0x0CCCC 148 #define TDV_BLTROP_INVERT 0x05555 149 #define TDV_BLTROP_XOR 0x06666 150 #define TDV_OFF_BLTCOLOR 0x02F0 151 #define TDV_OFF_BLTCMD 0x02F8 152 #define TDV_BLTCMD_SCR2SCR 0 153 #define TDV_BLTCMD_CPU2SCR 1 154 #define TDV_BLTCMD_RECTFILL 2 155 #define TDV_BLTCMD_LAUNCH __BIT(31) 156 #define TDV_BLTCMD_FMT_565 2 157 #define TDV_BLTCMD_CLIPRECT __BIT(16) 158 #define TDV_BLTCMD_DSTTILED __BIT(15) 159 #define TDV_OFF_DATA 0x02FC /* CPU2SCR */ 160 161 /* DAC */ 162 #define TDV_GENDAC_REFFREQ 14318 163 #define TDV_GENDAC_MAXVCO 250000 /* not sure about that */ 164 165 #define TDV_GENDAC_MIN_N1 1 166 #define TDV_GENDAC_MAX_N1 31 167 #define TDV_GENDAC_MIN_N2 0 168 #define TDV_GENDAC_MAX_N2 3 169 #define TDV_GENDAC_MIN_M 1 170 #define TDV_GENDAC_MAX_M 127 171 172 #define TDV_GENDAC_ADDRMASK 0x07 173 174 #define TDV_GENDAC_WR 0x0 175 #define TDV_GENDAC_LUT 0x01 176 #define TDV_GENDAC_PIXMASK 0x02 177 #define TDV_GENDAC_RD 0x03 178 179 #define TDV_GENDAC_PLLWR 0x04 180 #define TDV_GENDAC_PLLDATA 0x05 181 #define TDV_GENDAC_CMD 0x06 182 #define TDV_GENDAC_CMD_16BITS 0x50 183 #define TDV_GENDAC_CMD_24BITS 0x60 184 #define TDV_GENDAC_CMD_PWDOWN __BIT(0) 185 #define TDV_GENDAC_PLLRD 0x07 186 187 #define TDV_GENDAC_PLL_A 0xA 188 #define TDV_GENDAC_PLL_0 0x0 189 190 #define TDV_GENDAC_PLL_CTRL 0x0 191 #define TDV_GENDAC_PLL_VIDCLK __BIT(5) 192 #define TDV_GENDAC_PLL_VIDCLK0 0 193 #define TDV_GENDAC_PLL_CVGCLKA 0 194 195 #define TDV_GENDAC_CVGPLLMASK 0xEF 196 #define TDV_GENDAC_VIDPLLMASK 0xD8 197 198 #define TDV_GENDAC_DFLT_F1_M 0x55 199 #define TDV_GENDAC_DFLT_F1_N 0x49 200 #define TDV_GENDAC_DFLT_F7_M 0x71 201 #define TDV_GENDAC_DFLT_F7_N 0x29 202 #define TDV_GENDAC_DFLT_FB_M 0x79 203 #define TDV_GENDAC_DFLT_FB_N 0x2E 204 205 #endif /* TDVFBREG_H */ 206
Indexes created Tue Sep 30 20:09:53 GMT 2025