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      1 /* $NetBSD: tegra_usbreg.h,v 1.2 2017/01/22 17:46:20 jakllsch Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_USBREG_H
     30 #define _ARM_TEGRA_USBREG_H
     31 
     32 #define TEGRA_EHCI_TXFILLTUNING_REG		0x154
     33 #define TEGRA_EHCI_TXFILLTUNING_TXFIFOTHRES	__BITS(21,16)
     34 
     35 #define TEGRA_EHCI_ICUSB_CTRL_REG		0x15c
     36 #define TEGRA_EHCI_ICUSB_CTRL_ENB1		__BIT(3)
     37 #define TEGRA_EHCI_ICUSB_CTRL_VDD1		__BITS(2,0)
     38 
     39 #define TEGRA_EHCI_HOSTPC1_DEVLC_REG		0x1b4
     40 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS		__BITS(31,29)
     41 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_UTMI	0
     42 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ULPI	2
     43 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTS_ICUSB_SER	3
     44 #define TEGRA_EHCI_HOSTPC1_DEVLC_STS		__BIT(28)
     45 #define TEGRA_EHCI_HOSTPC1_DEVLC_PTW		__BIT(27)
     46 #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD		__BITS(26,25)
     47 #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_FS	0
     48 #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_LS	1
     49 #define TEGRA_EHCI_HOSTPC1_DEVLC_PSPD_HS	2
     50 #define TEGRA_EHCI_HOSTPC1_DEVLC_ALPD		__BIT(24)
     51 #define TEGRA_EHCI_HOSTPC1_DEVLC_PFSC		__BIT(23)
     52 #define TEGRA_EHCI_HOSTPC1_DEVLC_PHCD		__BIT(22)
     53 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMX		__BITS(21,20)
     54 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_EPLPM	__BITS(19,16)
     55 #define TEGRA_EHCI_HOSTPC1_DEVLC_H_LPMFRM	__BITS(15,12)
     56 #define TEGRA_EHCI_HOSTPC1_DEVLC_D_ASUS		__BIT(17)
     57 #define TEGRA_EHCI_HOSTPC1_DEVLC_D_STL		__BIT(16)
     58 #define TEGRA_EHCI_HOSTPC1_DEVLC_BA		__BITS(11,1)
     59 
     60 #define TEGRA_EHCI_USBMODE_REG			0x1f8
     61 #define TEGRA_EHCI_USBMODE_CM			__BITS(1,0)
     62 #define TEGRA_EHCI_USBMODE_CM_IDLE		0
     63 #define TEGRA_EHCI_USBMODE_CM_DEVICE		2
     64 #define TEGRA_EHCI_USBMODE_CM_HOST		3
     65 
     66 #define TEGRA_EHCI_SUSP_CTRL_REG		0x400
     67 #define TEGRA_EHCI_SUSP_CTRL_UHSIC_RESET	__BIT(14)
     68 #define TEGRA_EHCI_SUSP_CTRL_ULPI_PHY_ENB	__BIT(13)
     69 #define TEGRA_EHCI_SUSP_CTRL_UTMIP_PHY_ENB	__BIT(12)
     70 #define TEGRA_EHCI_SUSP_CTRL_UTMIP_RESET	__BIT(11)
     71 #define TEGRA_EHCI_SUSP_CTRL_PHY_CLK_VALID	__BIT(7)
     72 
     73 #define TEGRA_EHCI_PHY_VBUS_SENSORS_REG		0x404
     74 #define TEGRA_EHCI_PHY_VBUS_SENSORS_A_VBUS_VLD_STS __BIT(26)
     75 #define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_VALUE __BIT(12)
     76 #define TEGRA_EHCI_PHY_VBUS_SENSORS_B_VLD_SW_EN	__BIT(11)
     77 
     78 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_REG	0x408
     79 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_PU		__BIT(6)
     80 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_DEB_SEL_B	__BIT(5)
     81 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_VALUE	__BIT(4)
     82 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_SW_EN		__BIT(3)
     83 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_STS		__BIT(2)
     84 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_CHG_DET	__BIT(1)
     85 #define TEGRA_EHCI_PHY_VBUS_WAKEUP_ID_ID_INT_EN		__BIT(0)
     86 
     87 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_REG		0x808
     88 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_HSSLEW_MSB	__BITS(31,25)
     89 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP_MSB	__BITS(24,22)
     90 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_LSBIAS_SEL	__BIT(21)
     91 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_SETUP	__BITS(3,0)
     92 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PDZI_POWERDOWN __BIT(18)
     93 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD2_POWERDOWN __BIT(16)
     94 #define TEGRA_EHCI_UTMIP_XCVR_CFG0_PD_POWERDOWN	__BIT(14)
     95 
     96 #define TEGRA_EHCI_UTMIP_BIAS_CFG0_REG		0x80c
     97 #define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL_MSB __BIT(24)
     98 #define TEGRA_EHCI_UTMIP_BIAS_CFG0_BIASPD	__BIT(10)
     99 #define TEGRA_EHCI_UTMIP_BIAS_CFG0_HSDISCON_LEVEL __BITS(3,2)
    100 
    101 #define TEGRA_EHCI_UTMIP_TX_CFG0_REG		0x820
    102 #define TEGRA_EHCI_UTMIP_TX_CFG0_FS_PREAMBLE_J	__BIT(19)
    103 
    104 #define TEGRA_EHCI_UTMIP_MISC_CFG0_REG		0x824
    105 #define TEGRA_EHCI_UTMIP_MISC_CFG0_SUSPEND_EXIT_ON_EDGE __BIT(22)
    106 
    107 #define TEGRA_EHCI_UTMIP_MISC_CFG1_REG		0x828
    108 #define TEGRA_EHCI_UTMIP_MISC_CFG1_PHY_XTAL_CLOCKEN __BIT(30)
    109 
    110 #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_REG	0x82c
    111 #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_B	__BITS(31,16)
    112 #define TEGRA_EHCI_UTMIP_DEBOUNCE_CFG0_A	__BITS(15,0)
    113 
    114 #define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_REG	0x830
    115 #define TEGRA_EHCI_UTMIP_BAT_CHRG_CFG0_PD_CHRG	__BIT(0)
    116 
    117 #define TEGRA_EHCI_UTMIP_SPARE_CFG0_REG		0x834
    118 
    119 #define TEGRA_EHCI_UTMIP_XCVR_CFG1_REG		0x838
    120 #define TEGRA_EHCI_UTMIP_XCVR_CFG1_TERM_RANGE_ADJ __BITS(21,18)
    121 #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDR_POWERDOWN __BIT(4)
    122 #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDCHRP_POWERDOWN __BIT(2)
    123 #define TEGRA_EHCI_UTMIP_XCVR_CFG1_PDDISC_POWERDOWN __BIT(0)
    124 
    125 #define TEGRA_EHCI_UTMIP_BIAS_CFG1_REG		0x83c
    126 #define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_COUNT	__BITS(7,3)
    127 #define TEGRA_EHCI_UTMIP_BIAS_CFG1_PDTRK_POWERDOWN __BIT(0)
    128 
    129 #define TEGRA_EHCI_UTMIP_HSRX_CFG0_REG		0xc08
    130 #define TEGRA_EHCI_UTMIP_HSRX_CFG0_IDLE_WAIT	__BITS(19,15)
    131 #define TEGRA_EHCI_UTMIP_HSRX_CFG0_ELASTIC_LIMIT __BITS(14,10)
    132 
    133 #define TEGRA_EHCI_UTMIP_HSRX_CFG1_REG		0xc0c
    134 #define TEGRA_EHCI_UTMIP_HSRX_CFG1_SYNC_START_DLY __BITS(5,1)
    135 
    136 #endif /* _ARM_TEGRA_USBREG_H */
    137