Home | History | Annotate | Line # | Download | only in nvidia 
      1 /* $NetBSD: tegra_hdaudioreg.h,v 1.1 2015/05/10 11:04:59 jmcneill Exp $ */
      2 
      3 /*-
      4  * Copyright (c) 2015 Jared D. McNeill <jmcneill (at) invisible.ca>
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  *
     16  * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR
     17  * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
     18  * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
     19  * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,
     20  * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
     21  * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
     22  * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
     23  * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
     24  * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     25  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     26  * SUCH DAMAGE.
     27  */
     28 
     29 #ifndef _ARM_TEGRA_HDAUDIOREG_H
     30 #define _ARM_TEGRA_HDAUDIOREG_H
     31 
     32 #define TEGRA_HDA_IFPS_BAR0_REG		0x0080
     33 
     34 #define TEGRA_HDA_IFPS_CONFIG_REG	0x0180
     35 #define TEGRA_HDA_IFPS_CONFIG_FPCI_EN	__BIT(0)
     36 
     37 #define TEGRA_HDA_IFPS_INTR_REG		0x0188
     38 #define TEGRA_HDA_IFPS_INTR_EN		__BIT(16)
     39 
     40 #define TEGRA_HDA_CFG_CMD_REG		0x1004
     41 #define TEGRA_HDA_CFG_CMD_DISABLE_INTR	__BIT(10)
     42 #define TEGRA_HDA_CFG_CMD_ENABLE_SERR	__BIT(8)
     43 #define TEGRA_HDA_CFG_CMD_BUS_MASTER	__BIT(2)
     44 #define TEGRA_HDA_CFG_CMD_MEM_SPACE	__BIT(1)
     45 #define TEGRA_HDA_CFG_CMD_IO_SPACE	__BIT(0)
     46 
     47 #define TEGRA_HDA_CFG_BAR0_REG		0x1010
     48 #define TEGRA_HDA_CFG_BAR0_START	__BIT(6)
     49 
     50 #endif /* _ARM_TEGRA_HDAUDIOREG_H */
     51