HomeSort by: relevance | last modified time | path
    Searched defs:TFE (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
AMDGPUInstructionSelector.cpp 1451 static bool parseTexFail(uint64_t TexFailCtrl, bool &TFE, bool &LWE,
1456 TFE = (TexFailCtrl & 0x1) ? 1 : 0;
1493 bool TFE;
1497 TFE, LWE, IsTexFail))
1540 // unpacked subtargets, or by TFE.
1688 MIB.addImm(TFE); // tfe
1696 // An image load instruction with TFE/LWE only conditionally writes to its
1713 // With enable-prt-strict-null disabled, only initialize the extra TFE/LWE
4183 addZeroImm, // tfe
    [all...]
SIInstrInfo.cpp 3930 // being used TFE/LWE require an extra result register.
3936 const MachineOperand *TFE = getNamedOperand(MI, AMDGPU::OpName::tfe);
3944 // Adjust if using LWE or TFE
3945 if ((LWE && LWE->getImm()) || (TFE && TFE->getImm()))
5647 if (const MachineOperand *TFE =
5648 getNamedOperand(MI, AMDGPU::OpName::tfe)) {
5649 MIB.addImm(TFE->getImm());
SIISelLowering.cpp 1000 // Peek through TFE struct returns to only use the data size.
5911 static bool parseTexFail(SDValue TexFailCtrl, SelectionDAG &DAG, SDValue *TFE,
5921 *TFE = DAG.getTargetConstant((Value & 0x1) ? 1 : 0, DL, MVT::i32);
6178 SDValue TFE;
6182 if (!parseTexFail(TexFail, DAG, &TFE, &LWE, IsTexFail))
6249 Ops.push_back(TFE); //tfe
6250 } else if (cast<ConstantSDNode>(TFE)->getZExtValue()) {
6251 report_fatal_error("TFE is not supported on this GPU");
10951 case AMDGPU::sub4: return 4; // Possible with TFE/LW
    [all...]

Completed in 32 milliseconds