1 /* $NetBSD: tgavar.h,v 1.18 2009/05/18 00:14:27 he Exp $ */ 2 3 /* 4 * Copyright (c) 1995, 1996 Carnegie-Mellon University. 5 * All rights reserved. 6 * 7 * Author: Chris G. Demetriou 8 * 9 * Permission to use, copy, modify and distribute this software and 10 * its documentation is hereby granted, provided that both the copyright 11 * notice and this permission notice appear in all copies of the 12 * software, derivative works or modified versions, and any portions 13 * thereof, and that both notices appear in supporting documentation. 14 * 15 * CARNEGIE MELLON ALLOWS FREE USE OF THIS SOFTWARE IN ITS "AS IS" 16 * CONDITION. CARNEGIE MELLON DISCLAIMS ANY LIABILITY OF ANY KIND 17 * FOR ANY DAMAGES WHATSOEVER RESULTING FROM THE USE OF THIS SOFTWARE. 18 * 19 * Carnegie Mellon requests users of this software to return to 20 * 21 * Software Distribution Coordinator or Software.Distribution (at) CS.CMU.EDU 22 * School of Computer Science 23 * Carnegie Mellon University 24 * Pittsburgh PA 15213-3890 25 * 26 * any improvements or extensions that they make and grant Carnegie the 27 * rights to redistribute these changes. 28 */ 29 30 #include <dev/ic/ramdac.h> 31 #include <dev/pci/tgareg.h> 32 #include <dev/wscons/wsconsio.h> 33 #include <dev/wscons/wscons_raster.h> 34 #include <dev/wscons/wsdisplayvar.h> 35 #include <dev/rasops/rasops.h> 36 37 struct tga_devconfig; 38 struct fbcmap; 39 struct fbcursor; 40 struct fbcurpos; 41 42 struct tga_conf { 43 const char *tgac_name; /* name for this board type */ 44 45 struct ramdac_funcs *(*ramdac_funcs)(void); 46 47 int tgac_phys_depth; /* physical frame buffer depth */ 48 vsize_t tgac_cspace_size; /* core space size */ 49 vsize_t tgac_vvbr_units; /* what '1' in the VVBR means */ 50 51 int tgac_ndbuf; /* number of display buffers */ 52 vaddr_t tgac_dbuf[2]; /* display buffer offsets/addresses */ 53 vsize_t tgac_dbufsz[2]; /* display buffer sizes */ 54 55 int tgac_nbbuf; /* number of display buffers */ 56 vaddr_t tgac_bbuf[2]; /* back buffer offsets/addresses */ 57 vsize_t tgac_bbufsz[2]; /* back buffer sizes */ 58 }; 59 60 struct tga_devconfig { 61 bus_space_tag_t dc_memt; 62 bus_space_handle_t dc_memh; 63 64 pci_chipset_tag_t dc_pc; /* PCI chipset tag */ 65 pcitag_t dc_pcitag; /* PCI tag */ 66 bus_addr_t dc_pcipaddr; /* PCI phys addr. */ 67 68 bus_space_handle_t dc_regs; /* registers; XXX: need aliases */ 69 70 int dc_tga_type; /* the device type; see below */ 71 int dc_tga2; /* True if it is a TGA2 */ 72 const struct tga_conf *dc_tgaconf; /* device buffer configuration */ 73 74 struct ramdac_funcs 75 *dc_ramdac_funcs; /* The RAMDAC functions */ 76 struct ramdac_cookie 77 *dc_ramdac_cookie; /* the RAMDAC type; see above */ 78 79 vaddr_t dc_vaddr; /* memory space virtual base address */ 80 81 int dc_wid; /* width of frame buffer */ 82 int dc_ht; /* height of frame buffer */ 83 int dc_rowbytes; /* bytes in a FB scan line */ 84 85 vaddr_t dc_videobase; /* base of flat frame buffer */ 86 87 struct rasops_info dc_rinfo; /* raster display data */ 88 89 int dc_blanked; /* currently had video disabled */ 90 void *dc_ramdac_private; /* RAMDAC private storage */ 91 92 void (*dc_ramdac_intr)(void *); 93 int dc_intrenabled; /* can we depend on interrupts yet? */ 94 }; 95 96 struct tga_softc { 97 device_t sc_dev; 98 99 struct tga_devconfig *sc_dc; /* device configuration */ 100 void *sc_intr; /* interrupt handler info */ 101 /* XXX should record intr fns/arg */ 102 103 int nscreens; 104 }; 105 106 #define TGA_TYPE_T8_01 0 /* 8bpp, 1MB */ 107 #define TGA_TYPE_T8_02 1 /* 8bpp, 2MB */ 108 #define TGA_TYPE_T8_22 2 /* 8bpp, 4MB */ 109 #define TGA_TYPE_T8_44 3 /* 8bpp, 8MB */ 110 #define TGA_TYPE_T32_04 4 /* 32bpp, 4MB */ 111 #define TGA_TYPE_T32_08 5 /* 32bpp, 8MB */ 112 #define TGA_TYPE_T32_88 6 /* 32bpp, 16MB */ 113 #define TGA_TYPE_POWERSTORM_4D20 7 /* unknown */ 114 #define TGA_TYPE_UNKNOWN 8 /* unknown */ 115 116 #define DEVICE_IS_TGA(class, id) \ 117 (((PCI_VENDOR(id) == PCI_VENDOR_DEC && \ 118 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_21030) || \ 119 PCI_PRODUCT(id) == PCI_PRODUCT_DEC_PBXGB) ? 10 : 0) 120 121 int tga_cnmatch(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, pcitag_t); 122 int tga_cnattach(bus_space_tag_t, bus_space_tag_t, pci_chipset_tag_t, 123 int, int, int); 124 125 int tga_identify(struct tga_devconfig *); 126 const struct tga_conf *tga_getconf(int); 127 128 int tga_builtin_set_cursor(struct tga_devconfig *, struct wsdisplay_cursor *); 129 int tga_builtin_get_cursor(struct tga_devconfig *, struct wsdisplay_cursor *); 130 int tga_builtin_set_curpos(struct tga_devconfig *, struct wsdisplay_curpos *); 131 int tga_builtin_get_curpos(struct tga_devconfig *, struct wsdisplay_curpos *); 132 int tga_builtin_get_curmax(struct tga_devconfig *, struct wsdisplay_curpos *); 133 134 /* Read a TGA register */ 135 #define TGARREG(dc,reg) (bus_space_read_4((dc)->dc_memt, (dc)->dc_regs, \ 136 (reg) << 2)) 137 138 /* Write a TGA register */ 139 #define TGAWREG(dc,reg,val) bus_space_write_4((dc)->dc_memt, (dc)->dc_regs, \ 140 (reg) << 2, (val)) 141 142 /* Write a TGA register at an alternate aliased location */ 143 #define TGAWALREG(dc,reg,alias,val) bus_space_write_4( \ 144 (dc)->dc_memt, (dc)->dc_regs, \ 145 ((alias) * TGA_CREGS_ALIAS) + ((reg) << 2), \ 146 (val)) 147 148 /* Insert a write barrier */ 149 #define TGAREGWB(dc,reg, nregs) bus_space_barrier( \ 150 (dc)->dc_memt, (dc)->dc_regs, \ 151 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_WRITE) 152 153 /* Insert a read barrier */ 154 #define TGAREGRB(dc,reg, nregs) bus_space_barrier( \ 155 (dc)->dc_memt, (dc)->dc_regs, \ 156 ((reg) << 2), 4 * (nregs), BUS_SPACE_BARRIER_READ) 157 158 /* Insert a read/write barrier */ 159 #define TGAREGRWB(dc,reg, nregs) bus_space_barrier( \ 160 (dc)->dc_memt, (dc)->dc_regs, \ 161 ((reg) << 2), 4 * (nregs), \ 162 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE) 163
Indexes created Sat Sep 20 22:09:52 GMT 2025