1 /* $NetBSD: thm_9_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _thm_9_0_SH_MASK_HEADER 24 #define _thm_9_0_SH_MASK_HEADER 25 26 27 // addressBlock: thm_thm_SmuThmDec 28 //THM_TCON_CUR_TMP 29 #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP__SHIFT 0x0 30 #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP__SHIFT 0x5 31 #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN__SHIFT 0x7 32 #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN__SHIFT 0x8 33 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL__SHIFT 0x10 34 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL__SHIFT 0x12 35 #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL__SHIFT 0x13 36 #define THM_TCON_CUR_TMP__MCM_EN__SHIFT 0x14 37 #define THM_TCON_CUR_TMP__CUR_TEMP__SHIFT 0x15 38 #define THM_TCON_CUR_TMP__PER_STEP_TIME_UP_MASK 0x0000001FL 39 #define THM_TCON_CUR_TMP__TMP_MAX_DIFF_UP_MASK 0x00000060L 40 #define THM_TCON_CUR_TMP__TMP_SLEW_DN_EN_MASK 0x00000080L 41 #define THM_TCON_CUR_TMP__PER_STEP_TIME_DN_MASK 0x00001F00L 42 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SEL_MASK 0x00030000L 43 #define THM_TCON_CUR_TMP__CUR_TEMP_TJ_SLEW_SEL_MASK 0x00040000L 44 #define THM_TCON_CUR_TMP__CUR_TEMP_RANGE_SEL_MASK 0x00080000L 45 #define THM_TCON_CUR_TMP__MCM_EN_MASK 0x00100000L 46 #define THM_TCON_CUR_TMP__CUR_TEMP_MASK 0xFFE00000L 47 //THM_TCON_HTC 48 #define THM_TCON_HTC__HTC_EN__SHIFT 0x0 49 #define THM_TCON_HTC__EXTERNAL_PROCHOT__SHIFT 0x2 50 #define THM_TCON_HTC__INTERNAL_PROCHOT__SHIFT 0x3 51 #define THM_TCON_HTC__HTC_ACTIVE__SHIFT 0x4 52 #define THM_TCON_HTC__HTC_ACTIVE_LOG__SHIFT 0x5 53 #define THM_TCON_HTC__HTC_DIAG__SHIFT 0x8 54 #define THM_TCON_HTC__DIS_PROCHOT_PIN__SHIFT 0x9 55 #define THM_TCON_HTC__HTC_TO_IH_EN__SHIFT 0xa 56 #define THM_TCON_HTC__PROCHOT_TO_IH_EN__SHIFT 0xb 57 #define THM_TCON_HTC__PROCHOT_EVENT_SRC__SHIFT 0xc 58 #define THM_TCON_HTC__HTC_TMP_LMT__SHIFT 0x10 59 #define THM_TCON_HTC__HTC_HYST_LMT__SHIFT 0x17 60 #define THM_TCON_HTC__HTC_SLEW_SEL__SHIFT 0x1b 61 #define THM_TCON_HTC__HTC_EN_MASK 0x00000001L 62 #define THM_TCON_HTC__EXTERNAL_PROCHOT_MASK 0x00000004L 63 #define THM_TCON_HTC__INTERNAL_PROCHOT_MASK 0x00000008L 64 #define THM_TCON_HTC__HTC_ACTIVE_MASK 0x00000010L 65 #define THM_TCON_HTC__HTC_ACTIVE_LOG_MASK 0x00000020L 66 #define THM_TCON_HTC__HTC_DIAG_MASK 0x00000100L 67 #define THM_TCON_HTC__DIS_PROCHOT_PIN_MASK 0x00000200L 68 #define THM_TCON_HTC__HTC_TO_IH_EN_MASK 0x00000400L 69 #define THM_TCON_HTC__PROCHOT_TO_IH_EN_MASK 0x00000800L 70 #define THM_TCON_HTC__PROCHOT_EVENT_SRC_MASK 0x00007000L 71 #define THM_TCON_HTC__HTC_TMP_LMT_MASK 0x007F0000L 72 #define THM_TCON_HTC__HTC_HYST_LMT_MASK 0x07800000L 73 #define THM_TCON_HTC__HTC_SLEW_SEL_MASK 0x18000000L 74 //THM_TCON_THERM_TRIP 75 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY__SHIFT 0x0 76 #define THM_TCON_THERM_TRIP__THERM_TP__SHIFT 0x1 77 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED__SHIFT 0x2 78 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE__SHIFT 0x3 79 #define THM_TCON_THERM_TRIP__RSVD2__SHIFT 0x4 80 #define THM_TCON_THERM_TRIP__THERM_TP_EN__SHIFT 0x5 81 #define THM_TCON_THERM_TRIP__THERM_TP_LMT__SHIFT 0x6 82 #define THM_TCON_THERM_TRIP__RSVD3__SHIFT 0xe 83 #define THM_TCON_THERM_TRIP__SW_THERM_TP__SHIFT 0x1f 84 #define THM_TCON_THERM_TRIP__CTF_PAD_POLARITY_MASK 0x00000001L 85 #define THM_TCON_THERM_TRIP__THERM_TP_MASK 0x00000002L 86 #define THM_TCON_THERM_TRIP__CTF_THRESHOLD_EXCEEDED_MASK 0x00000004L 87 #define THM_TCON_THERM_TRIP__THERM_TP_SENSE_MASK 0x00000008L 88 #define THM_TCON_THERM_TRIP__RSVD2_MASK 0x00000010L 89 #define THM_TCON_THERM_TRIP__THERM_TP_EN_MASK 0x00000020L 90 #define THM_TCON_THERM_TRIP__THERM_TP_LMT_MASK 0x00003FC0L 91 #define THM_TCON_THERM_TRIP__RSVD3_MASK 0x7FFFC000L 92 #define THM_TCON_THERM_TRIP__SW_THERM_TP_MASK 0x80000000L 93 //THM_GPIO_PROCHOT_CTRL 94 #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL__SHIFT 0x0 95 #define THM_GPIO_PROCHOT_CTRL__PD__SHIFT 0x1 96 #define THM_GPIO_PROCHOT_CTRL__PU__SHIFT 0x2 97 #define THM_GPIO_PROCHOT_CTRL__SCHMEN__SHIFT 0x3 98 #define THM_GPIO_PROCHOT_CTRL__S0__SHIFT 0x4 99 #define THM_GPIO_PROCHOT_CTRL__S1__SHIFT 0x5 100 #define THM_GPIO_PROCHOT_CTRL__RXEN__SHIFT 0x6 101 #define THM_GPIO_PROCHOT_CTRL__RXSEL0__SHIFT 0x7 102 #define THM_GPIO_PROCHOT_CTRL__RXSEL1__SHIFT 0x8 103 #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE__SHIFT 0x10 104 #define THM_GPIO_PROCHOT_CTRL__OE__SHIFT 0x11 105 #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE__SHIFT 0x12 106 #define THM_GPIO_PROCHOT_CTRL__A__SHIFT 0x13 107 #define THM_GPIO_PROCHOT_CTRL__Y__SHIFT 0x1f 108 #define THM_GPIO_PROCHOT_CTRL__TXIMPSEL_MASK 0x00000001L 109 #define THM_GPIO_PROCHOT_CTRL__PD_MASK 0x00000002L 110 #define THM_GPIO_PROCHOT_CTRL__PU_MASK 0x00000004L 111 #define THM_GPIO_PROCHOT_CTRL__SCHMEN_MASK 0x00000008L 112 #define THM_GPIO_PROCHOT_CTRL__S0_MASK 0x00000010L 113 #define THM_GPIO_PROCHOT_CTRL__S1_MASK 0x00000020L 114 #define THM_GPIO_PROCHOT_CTRL__RXEN_MASK 0x00000040L 115 #define THM_GPIO_PROCHOT_CTRL__RXSEL0_MASK 0x00000080L 116 #define THM_GPIO_PROCHOT_CTRL__RXSEL1_MASK 0x00000100L 117 #define THM_GPIO_PROCHOT_CTRL__OE_OVERRIDE_MASK 0x00010000L 118 #define THM_GPIO_PROCHOT_CTRL__OE_MASK 0x00020000L 119 #define THM_GPIO_PROCHOT_CTRL__A_OVERRIDE_MASK 0x00040000L 120 #define THM_GPIO_PROCHOT_CTRL__A_MASK 0x00080000L 121 #define THM_GPIO_PROCHOT_CTRL__Y_MASK 0x80000000L 122 //THM_GPIO_THERMTRIP_CTRL 123 #define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL__SHIFT 0x0 124 #define THM_GPIO_THERMTRIP_CTRL__PD__SHIFT 0x1 125 #define THM_GPIO_THERMTRIP_CTRL__PU__SHIFT 0x2 126 #define THM_GPIO_THERMTRIP_CTRL__SCHMEN__SHIFT 0x3 127 #define THM_GPIO_THERMTRIP_CTRL__S0__SHIFT 0x4 128 #define THM_GPIO_THERMTRIP_CTRL__S1__SHIFT 0x5 129 #define THM_GPIO_THERMTRIP_CTRL__RXEN__SHIFT 0x6 130 #define THM_GPIO_THERMTRIP_CTRL__RXSEL0__SHIFT 0x7 131 #define THM_GPIO_THERMTRIP_CTRL__RXSEL1__SHIFT 0x8 132 #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE__SHIFT 0x10 133 #define THM_GPIO_THERMTRIP_CTRL__OE__SHIFT 0x11 134 #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE__SHIFT 0x12 135 #define THM_GPIO_THERMTRIP_CTRL__A__SHIFT 0x13 136 #define THM_GPIO_THERMTRIP_CTRL__CTFEN__SHIFT 0x14 137 #define THM_GPIO_THERMTRIP_CTRL__Y__SHIFT 0x1f 138 #define THM_GPIO_THERMTRIP_CTRL__TXIMPSEL_MASK 0x00000001L 139 #define THM_GPIO_THERMTRIP_CTRL__PD_MASK 0x00000002L 140 #define THM_GPIO_THERMTRIP_CTRL__PU_MASK 0x00000004L 141 #define THM_GPIO_THERMTRIP_CTRL__SCHMEN_MASK 0x00000008L 142 #define THM_GPIO_THERMTRIP_CTRL__S0_MASK 0x00000010L 143 #define THM_GPIO_THERMTRIP_CTRL__S1_MASK 0x00000020L 144 #define THM_GPIO_THERMTRIP_CTRL__RXEN_MASK 0x00000040L 145 #define THM_GPIO_THERMTRIP_CTRL__RXSEL0_MASK 0x00000080L 146 #define THM_GPIO_THERMTRIP_CTRL__RXSEL1_MASK 0x00000100L 147 #define THM_GPIO_THERMTRIP_CTRL__OE_OVERRIDE_MASK 0x00010000L 148 #define THM_GPIO_THERMTRIP_CTRL__OE_MASK 0x00020000L 149 #define THM_GPIO_THERMTRIP_CTRL__A_OVERRIDE_MASK 0x00040000L 150 #define THM_GPIO_THERMTRIP_CTRL__A_MASK 0x00080000L 151 #define THM_GPIO_THERMTRIP_CTRL__CTFEN_MASK 0x00100000L 152 #define THM_GPIO_THERMTRIP_CTRL__Y_MASK 0x80000000L 153 //THM_GPIO_PWM_CTRL 154 #define THM_GPIO_PWM_CTRL__TXIMPSEL__SHIFT 0x0 155 #define THM_GPIO_PWM_CTRL__PD__SHIFT 0x1 156 #define THM_GPIO_PWM_CTRL__PU__SHIFT 0x2 157 #define THM_GPIO_PWM_CTRL__SCHMEN__SHIFT 0x3 158 #define THM_GPIO_PWM_CTRL__S0__SHIFT 0x4 159 #define THM_GPIO_PWM_CTRL__S1__SHIFT 0x5 160 #define THM_GPIO_PWM_CTRL__RXEN__SHIFT 0x6 161 #define THM_GPIO_PWM_CTRL__RXSEL0__SHIFT 0x7 162 #define THM_GPIO_PWM_CTRL__RXSEL1__SHIFT 0x8 163 #define THM_GPIO_PWM_CTRL__OE_OVERRIDE__SHIFT 0x10 164 #define THM_GPIO_PWM_CTRL__OE__SHIFT 0x11 165 #define THM_GPIO_PWM_CTRL__A_OVERRIDE__SHIFT 0x12 166 #define THM_GPIO_PWM_CTRL__A__SHIFT 0x13 167 #define THM_GPIO_PWM_CTRL__Y__SHIFT 0x1f 168 #define THM_GPIO_PWM_CTRL__TXIMPSEL_MASK 0x00000001L 169 #define THM_GPIO_PWM_CTRL__PD_MASK 0x00000002L 170 #define THM_GPIO_PWM_CTRL__PU_MASK 0x00000004L 171 #define THM_GPIO_PWM_CTRL__SCHMEN_MASK 0x00000008L 172 #define THM_GPIO_PWM_CTRL__S0_MASK 0x00000010L 173 #define THM_GPIO_PWM_CTRL__S1_MASK 0x00000020L 174 #define THM_GPIO_PWM_CTRL__RXEN_MASK 0x00000040L 175 #define THM_GPIO_PWM_CTRL__RXSEL0_MASK 0x00000080L 176 #define THM_GPIO_PWM_CTRL__RXSEL1_MASK 0x00000100L 177 #define THM_GPIO_PWM_CTRL__OE_OVERRIDE_MASK 0x00010000L 178 #define THM_GPIO_PWM_CTRL__OE_MASK 0x00020000L 179 #define THM_GPIO_PWM_CTRL__A_OVERRIDE_MASK 0x00040000L 180 #define THM_GPIO_PWM_CTRL__A_MASK 0x00080000L 181 #define THM_GPIO_PWM_CTRL__Y_MASK 0x80000000L 182 //THM_GPIO_TACHIN_CTRL 183 #define THM_GPIO_TACHIN_CTRL__TXIMPSEL__SHIFT 0x0 184 #define THM_GPIO_TACHIN_CTRL__PD__SHIFT 0x1 185 #define THM_GPIO_TACHIN_CTRL__PU__SHIFT 0x2 186 #define THM_GPIO_TACHIN_CTRL__SCHMEN__SHIFT 0x3 187 #define THM_GPIO_TACHIN_CTRL__S0__SHIFT 0x4 188 #define THM_GPIO_TACHIN_CTRL__S1__SHIFT 0x5 189 #define THM_GPIO_TACHIN_CTRL__RXEN__SHIFT 0x6 190 #define THM_GPIO_TACHIN_CTRL__RXSEL0__SHIFT 0x7 191 #define THM_GPIO_TACHIN_CTRL__RXSEL1__SHIFT 0x8 192 #define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE__SHIFT 0x10 193 #define THM_GPIO_TACHIN_CTRL__OE__SHIFT 0x11 194 #define THM_GPIO_TACHIN_CTRL__A_OVERRIDE__SHIFT 0x12 195 #define THM_GPIO_TACHIN_CTRL__A__SHIFT 0x13 196 #define THM_GPIO_TACHIN_CTRL__Y__SHIFT 0x1f 197 #define THM_GPIO_TACHIN_CTRL__TXIMPSEL_MASK 0x00000001L 198 #define THM_GPIO_TACHIN_CTRL__PD_MASK 0x00000002L 199 #define THM_GPIO_TACHIN_CTRL__PU_MASK 0x00000004L 200 #define THM_GPIO_TACHIN_CTRL__SCHMEN_MASK 0x00000008L 201 #define THM_GPIO_TACHIN_CTRL__S0_MASK 0x00000010L 202 #define THM_GPIO_TACHIN_CTRL__S1_MASK 0x00000020L 203 #define THM_GPIO_TACHIN_CTRL__RXEN_MASK 0x00000040L 204 #define THM_GPIO_TACHIN_CTRL__RXSEL0_MASK 0x00000080L 205 #define THM_GPIO_TACHIN_CTRL__RXSEL1_MASK 0x00000100L 206 #define THM_GPIO_TACHIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 207 #define THM_GPIO_TACHIN_CTRL__OE_MASK 0x00020000L 208 #define THM_GPIO_TACHIN_CTRL__A_OVERRIDE_MASK 0x00040000L 209 #define THM_GPIO_TACHIN_CTRL__A_MASK 0x00080000L 210 #define THM_GPIO_TACHIN_CTRL__Y_MASK 0x80000000L 211 //THM_GPIO_PUMPOUT_CTRL 212 #define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL__SHIFT 0x0 213 #define THM_GPIO_PUMPOUT_CTRL__PD__SHIFT 0x1 214 #define THM_GPIO_PUMPOUT_CTRL__PU__SHIFT 0x2 215 #define THM_GPIO_PUMPOUT_CTRL__SCHMEN__SHIFT 0x3 216 #define THM_GPIO_PUMPOUT_CTRL__S0__SHIFT 0x4 217 #define THM_GPIO_PUMPOUT_CTRL__S1__SHIFT 0x5 218 #define THM_GPIO_PUMPOUT_CTRL__RXEN__SHIFT 0x6 219 #define THM_GPIO_PUMPOUT_CTRL__RXSEL0__SHIFT 0x7 220 #define THM_GPIO_PUMPOUT_CTRL__RXSEL1__SHIFT 0x8 221 #define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE__SHIFT 0x10 222 #define THM_GPIO_PUMPOUT_CTRL__OE__SHIFT 0x11 223 #define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE__SHIFT 0x12 224 #define THM_GPIO_PUMPOUT_CTRL__A__SHIFT 0x13 225 #define THM_GPIO_PUMPOUT_CTRL__Y__SHIFT 0x1f 226 #define THM_GPIO_PUMPOUT_CTRL__TXIMPSEL_MASK 0x00000001L 227 #define THM_GPIO_PUMPOUT_CTRL__PD_MASK 0x00000002L 228 #define THM_GPIO_PUMPOUT_CTRL__PU_MASK 0x00000004L 229 #define THM_GPIO_PUMPOUT_CTRL__SCHMEN_MASK 0x00000008L 230 #define THM_GPIO_PUMPOUT_CTRL__S0_MASK 0x00000010L 231 #define THM_GPIO_PUMPOUT_CTRL__S1_MASK 0x00000020L 232 #define THM_GPIO_PUMPOUT_CTRL__RXEN_MASK 0x00000040L 233 #define THM_GPIO_PUMPOUT_CTRL__RXSEL0_MASK 0x00000080L 234 #define THM_GPIO_PUMPOUT_CTRL__RXSEL1_MASK 0x00000100L 235 #define THM_GPIO_PUMPOUT_CTRL__OE_OVERRIDE_MASK 0x00010000L 236 #define THM_GPIO_PUMPOUT_CTRL__OE_MASK 0x00020000L 237 #define THM_GPIO_PUMPOUT_CTRL__A_OVERRIDE_MASK 0x00040000L 238 #define THM_GPIO_PUMPOUT_CTRL__A_MASK 0x00080000L 239 #define THM_GPIO_PUMPOUT_CTRL__Y_MASK 0x80000000L 240 //THM_GPIO_PUMPIN_CTRL 241 #define THM_GPIO_PUMPIN_CTRL__TXIMPSEL__SHIFT 0x0 242 #define THM_GPIO_PUMPIN_CTRL__PD__SHIFT 0x1 243 #define THM_GPIO_PUMPIN_CTRL__PU__SHIFT 0x2 244 #define THM_GPIO_PUMPIN_CTRL__SCHMEN__SHIFT 0x3 245 #define THM_GPIO_PUMPIN_CTRL__S0__SHIFT 0x4 246 #define THM_GPIO_PUMPIN_CTRL__S1__SHIFT 0x5 247 #define THM_GPIO_PUMPIN_CTRL__RXEN__SHIFT 0x6 248 #define THM_GPIO_PUMPIN_CTRL__RXSEL0__SHIFT 0x7 249 #define THM_GPIO_PUMPIN_CTRL__RXSEL1__SHIFT 0x8 250 #define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE__SHIFT 0x10 251 #define THM_GPIO_PUMPIN_CTRL__OE__SHIFT 0x11 252 #define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE__SHIFT 0x12 253 #define THM_GPIO_PUMPIN_CTRL__A__SHIFT 0x13 254 #define THM_GPIO_PUMPIN_CTRL__Y__SHIFT 0x1f 255 #define THM_GPIO_PUMPIN_CTRL__TXIMPSEL_MASK 0x00000001L 256 #define THM_GPIO_PUMPIN_CTRL__PD_MASK 0x00000002L 257 #define THM_GPIO_PUMPIN_CTRL__PU_MASK 0x00000004L 258 #define THM_GPIO_PUMPIN_CTRL__SCHMEN_MASK 0x00000008L 259 #define THM_GPIO_PUMPIN_CTRL__S0_MASK 0x00000010L 260 #define THM_GPIO_PUMPIN_CTRL__S1_MASK 0x00000020L 261 #define THM_GPIO_PUMPIN_CTRL__RXEN_MASK 0x00000040L 262 #define THM_GPIO_PUMPIN_CTRL__RXSEL0_MASK 0x00000080L 263 #define THM_GPIO_PUMPIN_CTRL__RXSEL1_MASK 0x00000100L 264 #define THM_GPIO_PUMPIN_CTRL__OE_OVERRIDE_MASK 0x00010000L 265 #define THM_GPIO_PUMPIN_CTRL__OE_MASK 0x00020000L 266 #define THM_GPIO_PUMPIN_CTRL__A_OVERRIDE_MASK 0x00040000L 267 #define THM_GPIO_PUMPIN_CTRL__A_MASK 0x00080000L 268 #define THM_GPIO_PUMPIN_CTRL__Y_MASK 0x80000000L 269 //THM_THERMAL_INT_ENA 270 #define THM_THERMAL_INT_ENA__THERM_INTH_SET__SHIFT 0x0 271 #define THM_THERMAL_INT_ENA__THERM_INTL_SET__SHIFT 0x1 272 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET__SHIFT 0x2 273 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR__SHIFT 0x3 274 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR__SHIFT 0x4 275 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR__SHIFT 0x5 276 #define THM_THERMAL_INT_ENA__THERM_INTH_SET_MASK 0x00000001L 277 #define THM_THERMAL_INT_ENA__THERM_INTL_SET_MASK 0x00000002L 278 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_SET_MASK 0x00000004L 279 #define THM_THERMAL_INT_ENA__THERM_INTH_CLR_MASK 0x00000008L 280 #define THM_THERMAL_INT_ENA__THERM_INTL_CLR_MASK 0x00000010L 281 #define THM_THERMAL_INT_ENA__THERM_TRIGGER_CLR_MASK 0x00000020L 282 //THM_THERMAL_INT_CTRL 283 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH__SHIFT 0x0 284 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL__SHIFT 0x8 285 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD__SHIFT 0x10 286 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK__SHIFT 0x18 287 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK__SHIFT 0x19 288 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK__SHIFT 0x1a 289 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK__SHIFT 0x1b 290 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA__SHIFT 0x1c 291 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT__SHIFT 0x1d 292 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTH_MASK 0x000000FFL 293 #define THM_THERMAL_INT_CTRL__DIG_THERM_INTL_MASK 0x0000FF00L 294 #define THM_THERMAL_INT_CTRL__TEMP_THRESHOLD_MASK 0x00FF0000L 295 #define THM_THERMAL_INT_CTRL__THERM_INTH_MASK_MASK 0x01000000L 296 #define THM_THERMAL_INT_CTRL__THERM_INTL_MASK_MASK 0x02000000L 297 #define THM_THERMAL_INT_CTRL__THERM_TRIGGER_MASK_MASK 0x04000000L 298 #define THM_THERMAL_INT_CTRL__THERM_PROCHOT_MASK_MASK 0x08000000L 299 #define THM_THERMAL_INT_CTRL__THERM_IH_HW_ENA_MASK 0x10000000L 300 #define THM_THERMAL_INT_CTRL__MAX_IH_CREDIT_MASK 0xE0000000L 301 //THM_THERMAL_INT_STATUS 302 #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT__SHIFT 0x0 303 #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT__SHIFT 0x1 304 #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT__SHIFT 0x2 305 #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT__SHIFT 0x3 306 #define THM_THERMAL_INT_STATUS__THERM_INTH_DETECT_MASK 0x00000001L 307 #define THM_THERMAL_INT_STATUS__THERM_INTL_DETECT_MASK 0x00000002L 308 #define THM_THERMAL_INT_STATUS__THERM_TRIGGER_DETECT_MASK 0x00000004L 309 #define THM_THERMAL_INT_STATUS__THERM_PROCHOT_DETECT_MASK 0x00000008L 310 //THM_TMON0_RDIL0_DATA 311 #define THM_TMON0_RDIL0_DATA__Z__SHIFT 0x0 312 #define THM_TMON0_RDIL0_DATA__VALID__SHIFT 0xb 313 #define THM_TMON0_RDIL0_DATA__TEMP__SHIFT 0xc 314 #define THM_TMON0_RDIL0_DATA__Z_MASK 0x000007FFL 315 #define THM_TMON0_RDIL0_DATA__VALID_MASK 0x00000800L 316 #define THM_TMON0_RDIL0_DATA__TEMP_MASK 0x00FFF000L 317 //THM_TMON0_RDIL1_DATA 318 #define THM_TMON0_RDIL1_DATA__Z__SHIFT 0x0 319 #define THM_TMON0_RDIL1_DATA__VALID__SHIFT 0xb 320 #define THM_TMON0_RDIL1_DATA__TEMP__SHIFT 0xc 321 #define THM_TMON0_RDIL1_DATA__Z_MASK 0x000007FFL 322 #define THM_TMON0_RDIL1_DATA__VALID_MASK 0x00000800L 323 #define THM_TMON0_RDIL1_DATA__TEMP_MASK 0x00FFF000L 324 //THM_TMON0_RDIL2_DATA 325 #define THM_TMON0_RDIL2_DATA__Z__SHIFT 0x0 326 #define THM_TMON0_RDIL2_DATA__VALID__SHIFT 0xb 327 #define THM_TMON0_RDIL2_DATA__TEMP__SHIFT 0xc 328 #define THM_TMON0_RDIL2_DATA__Z_MASK 0x000007FFL 329 #define THM_TMON0_RDIL2_DATA__VALID_MASK 0x00000800L 330 #define THM_TMON0_RDIL2_DATA__TEMP_MASK 0x00FFF000L 331 //THM_TMON0_RDIL3_DATA 332 #define THM_TMON0_RDIL3_DATA__Z__SHIFT 0x0 333 #define THM_TMON0_RDIL3_DATA__VALID__SHIFT 0xb 334 #define THM_TMON0_RDIL3_DATA__TEMP__SHIFT 0xc 335 #define THM_TMON0_RDIL3_DATA__Z_MASK 0x000007FFL 336 #define THM_TMON0_RDIL3_DATA__VALID_MASK 0x00000800L 337 #define THM_TMON0_RDIL3_DATA__TEMP_MASK 0x00FFF000L 338 //THM_TMON0_RDIL4_DATA 339 #define THM_TMON0_RDIL4_DATA__Z__SHIFT 0x0 340 #define THM_TMON0_RDIL4_DATA__VALID__SHIFT 0xb 341 #define THM_TMON0_RDIL4_DATA__TEMP__SHIFT 0xc 342 #define THM_TMON0_RDIL4_DATA__Z_MASK 0x000007FFL 343 #define THM_TMON0_RDIL4_DATA__VALID_MASK 0x00000800L 344 #define THM_TMON0_RDIL4_DATA__TEMP_MASK 0x00FFF000L 345 //THM_TMON0_RDIL5_DATA 346 #define THM_TMON0_RDIL5_DATA__Z__SHIFT 0x0 347 #define THM_TMON0_RDIL5_DATA__VALID__SHIFT 0xb 348 #define THM_TMON0_RDIL5_DATA__TEMP__SHIFT 0xc 349 #define THM_TMON0_RDIL5_DATA__Z_MASK 0x000007FFL 350 #define THM_TMON0_RDIL5_DATA__VALID_MASK 0x00000800L 351 #define THM_TMON0_RDIL5_DATA__TEMP_MASK 0x00FFF000L 352 //THM_TMON0_RDIL6_DATA 353 #define THM_TMON0_RDIL6_DATA__Z__SHIFT 0x0 354 #define THM_TMON0_RDIL6_DATA__VALID__SHIFT 0xb 355 #define THM_TMON0_RDIL6_DATA__TEMP__SHIFT 0xc 356 #define THM_TMON0_RDIL6_DATA__Z_MASK 0x000007FFL 357 #define THM_TMON0_RDIL6_DATA__VALID_MASK 0x00000800L 358 #define THM_TMON0_RDIL6_DATA__TEMP_MASK 0x00FFF000L 359 //THM_TMON0_RDIL7_DATA 360 #define THM_TMON0_RDIL7_DATA__Z__SHIFT 0x0 361 #define THM_TMON0_RDIL7_DATA__VALID__SHIFT 0xb 362 #define THM_TMON0_RDIL7_DATA__TEMP__SHIFT 0xc 363 #define THM_TMON0_RDIL7_DATA__Z_MASK 0x000007FFL 364 #define THM_TMON0_RDIL7_DATA__VALID_MASK 0x00000800L 365 #define THM_TMON0_RDIL7_DATA__TEMP_MASK 0x00FFF000L 366 //THM_TMON0_RDIL8_DATA 367 #define THM_TMON0_RDIL8_DATA__Z__SHIFT 0x0 368 #define THM_TMON0_RDIL8_DATA__VALID__SHIFT 0xb 369 #define THM_TMON0_RDIL8_DATA__TEMP__SHIFT 0xc 370 #define THM_TMON0_RDIL8_DATA__Z_MASK 0x000007FFL 371 #define THM_TMON0_RDIL8_DATA__VALID_MASK 0x00000800L 372 #define THM_TMON0_RDIL8_DATA__TEMP_MASK 0x00FFF000L 373 //THM_TMON0_RDIL9_DATA 374 #define THM_TMON0_RDIL9_DATA__Z__SHIFT 0x0 375 #define THM_TMON0_RDIL9_DATA__VALID__SHIFT 0xb 376 #define THM_TMON0_RDIL9_DATA__TEMP__SHIFT 0xc 377 #define THM_TMON0_RDIL9_DATA__Z_MASK 0x000007FFL 378 #define THM_TMON0_RDIL9_DATA__VALID_MASK 0x00000800L 379 #define THM_TMON0_RDIL9_DATA__TEMP_MASK 0x00FFF000L 380 //THM_TMON0_RDIL10_DATA 381 #define THM_TMON0_RDIL10_DATA__Z__SHIFT 0x0 382 #define THM_TMON0_RDIL10_DATA__VALID__SHIFT 0xb 383 #define THM_TMON0_RDIL10_DATA__TEMP__SHIFT 0xc 384 #define THM_TMON0_RDIL10_DATA__Z_MASK 0x000007FFL 385 #define THM_TMON0_RDIL10_DATA__VALID_MASK 0x00000800L 386 #define THM_TMON0_RDIL10_DATA__TEMP_MASK 0x00FFF000L 387 //THM_TMON0_RDIL11_DATA 388 #define THM_TMON0_RDIL11_DATA__Z__SHIFT 0x0 389 #define THM_TMON0_RDIL11_DATA__VALID__SHIFT 0xb 390 #define THM_TMON0_RDIL11_DATA__TEMP__SHIFT 0xc 391 #define THM_TMON0_RDIL11_DATA__Z_MASK 0x000007FFL 392 #define THM_TMON0_RDIL11_DATA__VALID_MASK 0x00000800L 393 #define THM_TMON0_RDIL11_DATA__TEMP_MASK 0x00FFF000L 394 //THM_TMON0_RDIL12_DATA 395 #define THM_TMON0_RDIL12_DATA__Z__SHIFT 0x0 396 #define THM_TMON0_RDIL12_DATA__VALID__SHIFT 0xb 397 #define THM_TMON0_RDIL12_DATA__TEMP__SHIFT 0xc 398 #define THM_TMON0_RDIL12_DATA__Z_MASK 0x000007FFL 399 #define THM_TMON0_RDIL12_DATA__VALID_MASK 0x00000800L 400 #define THM_TMON0_RDIL12_DATA__TEMP_MASK 0x00FFF000L 401 //THM_TMON0_RDIL13_DATA 402 #define THM_TMON0_RDIL13_DATA__Z__SHIFT 0x0 403 #define THM_TMON0_RDIL13_DATA__VALID__SHIFT 0xb 404 #define THM_TMON0_RDIL13_DATA__TEMP__SHIFT 0xc 405 #define THM_TMON0_RDIL13_DATA__Z_MASK 0x000007FFL 406 #define THM_TMON0_RDIL13_DATA__VALID_MASK 0x00000800L 407 #define THM_TMON0_RDIL13_DATA__TEMP_MASK 0x00FFF000L 408 //THM_TMON0_RDIL14_DATA 409 #define THM_TMON0_RDIL14_DATA__Z__SHIFT 0x0 410 #define THM_TMON0_RDIL14_DATA__VALID__SHIFT 0xb 411 #define THM_TMON0_RDIL14_DATA__TEMP__SHIFT 0xc 412 #define THM_TMON0_RDIL14_DATA__Z_MASK 0x000007FFL 413 #define THM_TMON0_RDIL14_DATA__VALID_MASK 0x00000800L 414 #define THM_TMON0_RDIL14_DATA__TEMP_MASK 0x00FFF000L 415 //THM_TMON0_RDIL15_DATA 416 #define THM_TMON0_RDIL15_DATA__Z__SHIFT 0x0 417 #define THM_TMON0_RDIL15_DATA__VALID__SHIFT 0xb 418 #define THM_TMON0_RDIL15_DATA__TEMP__SHIFT 0xc 419 #define THM_TMON0_RDIL15_DATA__Z_MASK 0x000007FFL 420 #define THM_TMON0_RDIL15_DATA__VALID_MASK 0x00000800L 421 #define THM_TMON0_RDIL15_DATA__TEMP_MASK 0x00FFF000L 422 //THM_TMON0_RDIR0_DATA 423 #define THM_TMON0_RDIR0_DATA__Z__SHIFT 0x0 424 #define THM_TMON0_RDIR0_DATA__VALID__SHIFT 0xb 425 #define THM_TMON0_RDIR0_DATA__TEMP__SHIFT 0xc 426 #define THM_TMON0_RDIR0_DATA__Z_MASK 0x000007FFL 427 #define THM_TMON0_RDIR0_DATA__VALID_MASK 0x00000800L 428 #define THM_TMON0_RDIR0_DATA__TEMP_MASK 0x00FFF000L 429 //THM_TMON0_RDIR1_DATA 430 #define THM_TMON0_RDIR1_DATA__Z__SHIFT 0x0 431 #define THM_TMON0_RDIR1_DATA__VALID__SHIFT 0xb 432 #define THM_TMON0_RDIR1_DATA__TEMP__SHIFT 0xc 433 #define THM_TMON0_RDIR1_DATA__Z_MASK 0x000007FFL 434 #define THM_TMON0_RDIR1_DATA__VALID_MASK 0x00000800L 435 #define THM_TMON0_RDIR1_DATA__TEMP_MASK 0x00FFF000L 436 //THM_TMON0_RDIR2_DATA 437 #define THM_TMON0_RDIR2_DATA__Z__SHIFT 0x0 438 #define THM_TMON0_RDIR2_DATA__VALID__SHIFT 0xb 439 #define THM_TMON0_RDIR2_DATA__TEMP__SHIFT 0xc 440 #define THM_TMON0_RDIR2_DATA__Z_MASK 0x000007FFL 441 #define THM_TMON0_RDIR2_DATA__VALID_MASK 0x00000800L 442 #define THM_TMON0_RDIR2_DATA__TEMP_MASK 0x00FFF000L 443 //THM_TMON0_RDIR3_DATA 444 #define THM_TMON0_RDIR3_DATA__Z__SHIFT 0x0 445 #define THM_TMON0_RDIR3_DATA__VALID__SHIFT 0xb 446 #define THM_TMON0_RDIR3_DATA__TEMP__SHIFT 0xc 447 #define THM_TMON0_RDIR3_DATA__Z_MASK 0x000007FFL 448 #define THM_TMON0_RDIR3_DATA__VALID_MASK 0x00000800L 449 #define THM_TMON0_RDIR3_DATA__TEMP_MASK 0x00FFF000L 450 //THM_TMON0_RDIR4_DATA 451 #define THM_TMON0_RDIR4_DATA__Z__SHIFT 0x0 452 #define THM_TMON0_RDIR4_DATA__VALID__SHIFT 0xb 453 #define THM_TMON0_RDIR4_DATA__TEMP__SHIFT 0xc 454 #define THM_TMON0_RDIR4_DATA__Z_MASK 0x000007FFL 455 #define THM_TMON0_RDIR4_DATA__VALID_MASK 0x00000800L 456 #define THM_TMON0_RDIR4_DATA__TEMP_MASK 0x00FFF000L 457 //THM_TMON0_RDIR5_DATA 458 #define THM_TMON0_RDIR5_DATA__Z__SHIFT 0x0 459 #define THM_TMON0_RDIR5_DATA__VALID__SHIFT 0xb 460 #define THM_TMON0_RDIR5_DATA__TEMP__SHIFT 0xc 461 #define THM_TMON0_RDIR5_DATA__Z_MASK 0x000007FFL 462 #define THM_TMON0_RDIR5_DATA__VALID_MASK 0x00000800L 463 #define THM_TMON0_RDIR5_DATA__TEMP_MASK 0x00FFF000L 464 //THM_TMON0_RDIR6_DATA 465 #define THM_TMON0_RDIR6_DATA__Z__SHIFT 0x0 466 #define THM_TMON0_RDIR6_DATA__VALID__SHIFT 0xb 467 #define THM_TMON0_RDIR6_DATA__TEMP__SHIFT 0xc 468 #define THM_TMON0_RDIR6_DATA__Z_MASK 0x000007FFL 469 #define THM_TMON0_RDIR6_DATA__VALID_MASK 0x00000800L 470 #define THM_TMON0_RDIR6_DATA__TEMP_MASK 0x00FFF000L 471 //THM_TMON0_RDIR7_DATA 472 #define THM_TMON0_RDIR7_DATA__Z__SHIFT 0x0 473 #define THM_TMON0_RDIR7_DATA__VALID__SHIFT 0xb 474 #define THM_TMON0_RDIR7_DATA__TEMP__SHIFT 0xc 475 #define THM_TMON0_RDIR7_DATA__Z_MASK 0x000007FFL 476 #define THM_TMON0_RDIR7_DATA__VALID_MASK 0x00000800L 477 #define THM_TMON0_RDIR7_DATA__TEMP_MASK 0x00FFF000L 478 //THM_TMON0_RDIR8_DATA 479 #define THM_TMON0_RDIR8_DATA__Z__SHIFT 0x0 480 #define THM_TMON0_RDIR8_DATA__VALID__SHIFT 0xb 481 #define THM_TMON0_RDIR8_DATA__TEMP__SHIFT 0xc 482 #define THM_TMON0_RDIR8_DATA__Z_MASK 0x000007FFL 483 #define THM_TMON0_RDIR8_DATA__VALID_MASK 0x00000800L 484 #define THM_TMON0_RDIR8_DATA__TEMP_MASK 0x00FFF000L 485 //THM_TMON0_RDIR9_DATA 486 #define THM_TMON0_RDIR9_DATA__Z__SHIFT 0x0 487 #define THM_TMON0_RDIR9_DATA__VALID__SHIFT 0xb 488 #define THM_TMON0_RDIR9_DATA__TEMP__SHIFT 0xc 489 #define THM_TMON0_RDIR9_DATA__Z_MASK 0x000007FFL 490 #define THM_TMON0_RDIR9_DATA__VALID_MASK 0x00000800L 491 #define THM_TMON0_RDIR9_DATA__TEMP_MASK 0x00FFF000L 492 //THM_TMON0_RDIR10_DATA 493 #define THM_TMON0_RDIR10_DATA__Z__SHIFT 0x0 494 #define THM_TMON0_RDIR10_DATA__VALID__SHIFT 0xb 495 #define THM_TMON0_RDIR10_DATA__TEMP__SHIFT 0xc 496 #define THM_TMON0_RDIR10_DATA__Z_MASK 0x000007FFL 497 #define THM_TMON0_RDIR10_DATA__VALID_MASK 0x00000800L 498 #define THM_TMON0_RDIR10_DATA__TEMP_MASK 0x00FFF000L 499 //THM_TMON0_RDIR11_DATA 500 #define THM_TMON0_RDIR11_DATA__Z__SHIFT 0x0 501 #define THM_TMON0_RDIR11_DATA__VALID__SHIFT 0xb 502 #define THM_TMON0_RDIR11_DATA__TEMP__SHIFT 0xc 503 #define THM_TMON0_RDIR11_DATA__Z_MASK 0x000007FFL 504 #define THM_TMON0_RDIR11_DATA__VALID_MASK 0x00000800L 505 #define THM_TMON0_RDIR11_DATA__TEMP_MASK 0x00FFF000L 506 //THM_TMON0_RDIR12_DATA 507 #define THM_TMON0_RDIR12_DATA__Z__SHIFT 0x0 508 #define THM_TMON0_RDIR12_DATA__VALID__SHIFT 0xb 509 #define THM_TMON0_RDIR12_DATA__TEMP__SHIFT 0xc 510 #define THM_TMON0_RDIR12_DATA__Z_MASK 0x000007FFL 511 #define THM_TMON0_RDIR12_DATA__VALID_MASK 0x00000800L 512 #define THM_TMON0_RDIR12_DATA__TEMP_MASK 0x00FFF000L 513 //THM_TMON0_RDIR13_DATA 514 #define THM_TMON0_RDIR13_DATA__Z__SHIFT 0x0 515 #define THM_TMON0_RDIR13_DATA__VALID__SHIFT 0xb 516 #define THM_TMON0_RDIR13_DATA__TEMP__SHIFT 0xc 517 #define THM_TMON0_RDIR13_DATA__Z_MASK 0x000007FFL 518 #define THM_TMON0_RDIR13_DATA__VALID_MASK 0x00000800L 519 #define THM_TMON0_RDIR13_DATA__TEMP_MASK 0x00FFF000L 520 //THM_TMON0_RDIR14_DATA 521 #define THM_TMON0_RDIR14_DATA__Z__SHIFT 0x0 522 #define THM_TMON0_RDIR14_DATA__VALID__SHIFT 0xb 523 #define THM_TMON0_RDIR14_DATA__TEMP__SHIFT 0xc 524 #define THM_TMON0_RDIR14_DATA__Z_MASK 0x000007FFL 525 #define THM_TMON0_RDIR14_DATA__VALID_MASK 0x00000800L 526 #define THM_TMON0_RDIR14_DATA__TEMP_MASK 0x00FFF000L 527 //THM_TMON0_RDIR15_DATA 528 #define THM_TMON0_RDIR15_DATA__Z__SHIFT 0x0 529 #define THM_TMON0_RDIR15_DATA__VALID__SHIFT 0xb 530 #define THM_TMON0_RDIR15_DATA__TEMP__SHIFT 0xc 531 #define THM_TMON0_RDIR15_DATA__Z_MASK 0x000007FFL 532 #define THM_TMON0_RDIR15_DATA__VALID_MASK 0x00000800L 533 #define THM_TMON0_RDIR15_DATA__TEMP_MASK 0x00FFF000L 534 //THM_TMON0_INT_DATA 535 #define THM_TMON0_INT_DATA__Z__SHIFT 0x0 536 #define THM_TMON0_INT_DATA__VALID__SHIFT 0xb 537 #define THM_TMON0_INT_DATA__TEMP__SHIFT 0xc 538 #define THM_TMON0_INT_DATA__Z_MASK 0x000007FFL 539 #define THM_TMON0_INT_DATA__VALID_MASK 0x00000800L 540 #define THM_TMON0_INT_DATA__TEMP_MASK 0x00FFF000L 541 //THM_TMON0_DEBUG 542 #define THM_TMON0_DEBUG__DEBUG_RDI__SHIFT 0x0 543 #define THM_TMON0_DEBUG__DEBUG_Z__SHIFT 0x5 544 #define THM_TMON0_DEBUG__DEBUG_RDI_MASK 0x0000001FL 545 #define THM_TMON0_DEBUG__DEBUG_Z_MASK 0x0000FFE0L 546 //THM_TMON1_RDIL0_DATA 547 #define THM_TMON1_RDIL0_DATA__Z__SHIFT 0x0 548 #define THM_TMON1_RDIL0_DATA__VALID__SHIFT 0xb 549 #define THM_TMON1_RDIL0_DATA__TEMP__SHIFT 0xc 550 #define THM_TMON1_RDIL0_DATA__Z_MASK 0x000007FFL 551 #define THM_TMON1_RDIL0_DATA__VALID_MASK 0x00000800L 552 #define THM_TMON1_RDIL0_DATA__TEMP_MASK 0x00FFF000L 553 //THM_TMON1_RDIL1_DATA 554 #define THM_TMON1_RDIL1_DATA__Z__SHIFT 0x0 555 #define THM_TMON1_RDIL1_DATA__VALID__SHIFT 0xb 556 #define THM_TMON1_RDIL1_DATA__TEMP__SHIFT 0xc 557 #define THM_TMON1_RDIL1_DATA__Z_MASK 0x000007FFL 558 #define THM_TMON1_RDIL1_DATA__VALID_MASK 0x00000800L 559 #define THM_TMON1_RDIL1_DATA__TEMP_MASK 0x00FFF000L 560 //THM_TMON1_RDIL2_DATA 561 #define THM_TMON1_RDIL2_DATA__Z__SHIFT 0x0 562 #define THM_TMON1_RDIL2_DATA__VALID__SHIFT 0xb 563 #define THM_TMON1_RDIL2_DATA__TEMP__SHIFT 0xc 564 #define THM_TMON1_RDIL2_DATA__Z_MASK 0x000007FFL 565 #define THM_TMON1_RDIL2_DATA__VALID_MASK 0x00000800L 566 #define THM_TMON1_RDIL2_DATA__TEMP_MASK 0x00FFF000L 567 //THM_TMON1_RDIL3_DATA 568 #define THM_TMON1_RDIL3_DATA__Z__SHIFT 0x0 569 #define THM_TMON1_RDIL3_DATA__VALID__SHIFT 0xb 570 #define THM_TMON1_RDIL3_DATA__TEMP__SHIFT 0xc 571 #define THM_TMON1_RDIL3_DATA__Z_MASK 0x000007FFL 572 #define THM_TMON1_RDIL3_DATA__VALID_MASK 0x00000800L 573 #define THM_TMON1_RDIL3_DATA__TEMP_MASK 0x00FFF000L 574 //THM_TMON1_RDIL4_DATA 575 #define THM_TMON1_RDIL4_DATA__Z__SHIFT 0x0 576 #define THM_TMON1_RDIL4_DATA__VALID__SHIFT 0xb 577 #define THM_TMON1_RDIL4_DATA__TEMP__SHIFT 0xc 578 #define THM_TMON1_RDIL4_DATA__Z_MASK 0x000007FFL 579 #define THM_TMON1_RDIL4_DATA__VALID_MASK 0x00000800L 580 #define THM_TMON1_RDIL4_DATA__TEMP_MASK 0x00FFF000L 581 //THM_TMON1_RDIL5_DATA 582 #define THM_TMON1_RDIL5_DATA__Z__SHIFT 0x0 583 #define THM_TMON1_RDIL5_DATA__VALID__SHIFT 0xb 584 #define THM_TMON1_RDIL5_DATA__TEMP__SHIFT 0xc 585 #define THM_TMON1_RDIL5_DATA__Z_MASK 0x000007FFL 586 #define THM_TMON1_RDIL5_DATA__VALID_MASK 0x00000800L 587 #define THM_TMON1_RDIL5_DATA__TEMP_MASK 0x00FFF000L 588 //THM_TMON1_RDIL6_DATA 589 #define THM_TMON1_RDIL6_DATA__Z__SHIFT 0x0 590 #define THM_TMON1_RDIL6_DATA__VALID__SHIFT 0xb 591 #define THM_TMON1_RDIL6_DATA__TEMP__SHIFT 0xc 592 #define THM_TMON1_RDIL6_DATA__Z_MASK 0x000007FFL 593 #define THM_TMON1_RDIL6_DATA__VALID_MASK 0x00000800L 594 #define THM_TMON1_RDIL6_DATA__TEMP_MASK 0x00FFF000L 595 //THM_TMON1_RDIL7_DATA 596 #define THM_TMON1_RDIL7_DATA__Z__SHIFT 0x0 597 #define THM_TMON1_RDIL7_DATA__VALID__SHIFT 0xb 598 #define THM_TMON1_RDIL7_DATA__TEMP__SHIFT 0xc 599 #define THM_TMON1_RDIL7_DATA__Z_MASK 0x000007FFL 600 #define THM_TMON1_RDIL7_DATA__VALID_MASK 0x00000800L 601 #define THM_TMON1_RDIL7_DATA__TEMP_MASK 0x00FFF000L 602 //THM_TMON1_RDIL8_DATA 603 #define THM_TMON1_RDIL8_DATA__Z__SHIFT 0x0 604 #define THM_TMON1_RDIL8_DATA__VALID__SHIFT 0xb 605 #define THM_TMON1_RDIL8_DATA__TEMP__SHIFT 0xc 606 #define THM_TMON1_RDIL8_DATA__Z_MASK 0x000007FFL 607 #define THM_TMON1_RDIL8_DATA__VALID_MASK 0x00000800L 608 #define THM_TMON1_RDIL8_DATA__TEMP_MASK 0x00FFF000L 609 //THM_TMON1_RDIL9_DATA 610 #define THM_TMON1_RDIL9_DATA__Z__SHIFT 0x0 611 #define THM_TMON1_RDIL9_DATA__VALID__SHIFT 0xb 612 #define THM_TMON1_RDIL9_DATA__TEMP__SHIFT 0xc 613 #define THM_TMON1_RDIL9_DATA__Z_MASK 0x000007FFL 614 #define THM_TMON1_RDIL9_DATA__VALID_MASK 0x00000800L 615 #define THM_TMON1_RDIL9_DATA__TEMP_MASK 0x00FFF000L 616 //THM_TMON1_RDIL10_DATA 617 #define THM_TMON1_RDIL10_DATA__Z__SHIFT 0x0 618 #define THM_TMON1_RDIL10_DATA__VALID__SHIFT 0xb 619 #define THM_TMON1_RDIL10_DATA__TEMP__SHIFT 0xc 620 #define THM_TMON1_RDIL10_DATA__Z_MASK 0x000007FFL 621 #define THM_TMON1_RDIL10_DATA__VALID_MASK 0x00000800L 622 #define THM_TMON1_RDIL10_DATA__TEMP_MASK 0x00FFF000L 623 //THM_TMON1_RDIL11_DATA 624 #define THM_TMON1_RDIL11_DATA__Z__SHIFT 0x0 625 #define THM_TMON1_RDIL11_DATA__VALID__SHIFT 0xb 626 #define THM_TMON1_RDIL11_DATA__TEMP__SHIFT 0xc 627 #define THM_TMON1_RDIL11_DATA__Z_MASK 0x000007FFL 628 #define THM_TMON1_RDIL11_DATA__VALID_MASK 0x00000800L 629 #define THM_TMON1_RDIL11_DATA__TEMP_MASK 0x00FFF000L 630 //THM_TMON1_RDIL12_DATA 631 #define THM_TMON1_RDIL12_DATA__Z__SHIFT 0x0 632 #define THM_TMON1_RDIL12_DATA__VALID__SHIFT 0xb 633 #define THM_TMON1_RDIL12_DATA__TEMP__SHIFT 0xc 634 #define THM_TMON1_RDIL12_DATA__Z_MASK 0x000007FFL 635 #define THM_TMON1_RDIL12_DATA__VALID_MASK 0x00000800L 636 #define THM_TMON1_RDIL12_DATA__TEMP_MASK 0x00FFF000L 637 //THM_TMON1_RDIL13_DATA 638 #define THM_TMON1_RDIL13_DATA__Z__SHIFT 0x0 639 #define THM_TMON1_RDIL13_DATA__VALID__SHIFT 0xb 640 #define THM_TMON1_RDIL13_DATA__TEMP__SHIFT 0xc 641 #define THM_TMON1_RDIL13_DATA__Z_MASK 0x000007FFL 642 #define THM_TMON1_RDIL13_DATA__VALID_MASK 0x00000800L 643 #define THM_TMON1_RDIL13_DATA__TEMP_MASK 0x00FFF000L 644 //THM_TMON1_RDIL14_DATA 645 #define THM_TMON1_RDIL14_DATA__Z__SHIFT 0x0 646 #define THM_TMON1_RDIL14_DATA__VALID__SHIFT 0xb 647 #define THM_TMON1_RDIL14_DATA__TEMP__SHIFT 0xc 648 #define THM_TMON1_RDIL14_DATA__Z_MASK 0x000007FFL 649 #define THM_TMON1_RDIL14_DATA__VALID_MASK 0x00000800L 650 #define THM_TMON1_RDIL14_DATA__TEMP_MASK 0x00FFF000L 651 //THM_TMON1_RDIL15_DATA 652 #define THM_TMON1_RDIL15_DATA__Z__SHIFT 0x0 653 #define THM_TMON1_RDIL15_DATA__VALID__SHIFT 0xb 654 #define THM_TMON1_RDIL15_DATA__TEMP__SHIFT 0xc 655 #define THM_TMON1_RDIL15_DATA__Z_MASK 0x000007FFL 656 #define THM_TMON1_RDIL15_DATA__VALID_MASK 0x00000800L 657 #define THM_TMON1_RDIL15_DATA__TEMP_MASK 0x00FFF000L 658 //THM_TMON1_RDIR0_DATA 659 #define THM_TMON1_RDIR0_DATA__Z__SHIFT 0x0 660 #define THM_TMON1_RDIR0_DATA__VALID__SHIFT 0xb 661 #define THM_TMON1_RDIR0_DATA__TEMP__SHIFT 0xc 662 #define THM_TMON1_RDIR0_DATA__Z_MASK 0x000007FFL 663 #define THM_TMON1_RDIR0_DATA__VALID_MASK 0x00000800L 664 #define THM_TMON1_RDIR0_DATA__TEMP_MASK 0x00FFF000L 665 //THM_TMON1_RDIR1_DATA 666 #define THM_TMON1_RDIR1_DATA__Z__SHIFT 0x0 667 #define THM_TMON1_RDIR1_DATA__VALID__SHIFT 0xb 668 #define THM_TMON1_RDIR1_DATA__TEMP__SHIFT 0xc 669 #define THM_TMON1_RDIR1_DATA__Z_MASK 0x000007FFL 670 #define THM_TMON1_RDIR1_DATA__VALID_MASK 0x00000800L 671 #define THM_TMON1_RDIR1_DATA__TEMP_MASK 0x00FFF000L 672 //THM_TMON1_RDIR2_DATA 673 #define THM_TMON1_RDIR2_DATA__Z__SHIFT 0x0 674 #define THM_TMON1_RDIR2_DATA__VALID__SHIFT 0xb 675 #define THM_TMON1_RDIR2_DATA__TEMP__SHIFT 0xc 676 #define THM_TMON1_RDIR2_DATA__Z_MASK 0x000007FFL 677 #define THM_TMON1_RDIR2_DATA__VALID_MASK 0x00000800L 678 #define THM_TMON1_RDIR2_DATA__TEMP_MASK 0x00FFF000L 679 //THM_TMON1_RDIR3_DATA 680 #define THM_TMON1_RDIR3_DATA__Z__SHIFT 0x0 681 #define THM_TMON1_RDIR3_DATA__VALID__SHIFT 0xb 682 #define THM_TMON1_RDIR3_DATA__TEMP__SHIFT 0xc 683 #define THM_TMON1_RDIR3_DATA__Z_MASK 0x000007FFL 684 #define THM_TMON1_RDIR3_DATA__VALID_MASK 0x00000800L 685 #define THM_TMON1_RDIR3_DATA__TEMP_MASK 0x00FFF000L 686 //THM_TMON1_RDIR4_DATA 687 #define THM_TMON1_RDIR4_DATA__Z__SHIFT 0x0 688 #define THM_TMON1_RDIR4_DATA__VALID__SHIFT 0xb 689 #define THM_TMON1_RDIR4_DATA__TEMP__SHIFT 0xc 690 #define THM_TMON1_RDIR4_DATA__Z_MASK 0x000007FFL 691 #define THM_TMON1_RDIR4_DATA__VALID_MASK 0x00000800L 692 #define THM_TMON1_RDIR4_DATA__TEMP_MASK 0x00FFF000L 693 //THM_TMON1_RDIR5_DATA 694 #define THM_TMON1_RDIR5_DATA__Z__SHIFT 0x0 695 #define THM_TMON1_RDIR5_DATA__VALID__SHIFT 0xb 696 #define THM_TMON1_RDIR5_DATA__TEMP__SHIFT 0xc 697 #define THM_TMON1_RDIR5_DATA__Z_MASK 0x000007FFL 698 #define THM_TMON1_RDIR5_DATA__VALID_MASK 0x00000800L 699 #define THM_TMON1_RDIR5_DATA__TEMP_MASK 0x00FFF000L 700 //THM_TMON1_RDIR6_DATA 701 #define THM_TMON1_RDIR6_DATA__Z__SHIFT 0x0 702 #define THM_TMON1_RDIR6_DATA__VALID__SHIFT 0xb 703 #define THM_TMON1_RDIR6_DATA__TEMP__SHIFT 0xc 704 #define THM_TMON1_RDIR6_DATA__Z_MASK 0x000007FFL 705 #define THM_TMON1_RDIR6_DATA__VALID_MASK 0x00000800L 706 #define THM_TMON1_RDIR6_DATA__TEMP_MASK 0x00FFF000L 707 //THM_TMON1_RDIR7_DATA 708 #define THM_TMON1_RDIR7_DATA__Z__SHIFT 0x0 709 #define THM_TMON1_RDIR7_DATA__VALID__SHIFT 0xb 710 #define THM_TMON1_RDIR7_DATA__TEMP__SHIFT 0xc 711 #define THM_TMON1_RDIR7_DATA__Z_MASK 0x000007FFL 712 #define THM_TMON1_RDIR7_DATA__VALID_MASK 0x00000800L 713 #define THM_TMON1_RDIR7_DATA__TEMP_MASK 0x00FFF000L 714 //THM_TMON1_RDIR8_DATA 715 #define THM_TMON1_RDIR8_DATA__Z__SHIFT 0x0 716 #define THM_TMON1_RDIR8_DATA__VALID__SHIFT 0xb 717 #define THM_TMON1_RDIR8_DATA__TEMP__SHIFT 0xc 718 #define THM_TMON1_RDIR8_DATA__Z_MASK 0x000007FFL 719 #define THM_TMON1_RDIR8_DATA__VALID_MASK 0x00000800L 720 #define THM_TMON1_RDIR8_DATA__TEMP_MASK 0x00FFF000L 721 //THM_TMON1_RDIR9_DATA 722 #define THM_TMON1_RDIR9_DATA__Z__SHIFT 0x0 723 #define THM_TMON1_RDIR9_DATA__VALID__SHIFT 0xb 724 #define THM_TMON1_RDIR9_DATA__TEMP__SHIFT 0xc 725 #define THM_TMON1_RDIR9_DATA__Z_MASK 0x000007FFL 726 #define THM_TMON1_RDIR9_DATA__VALID_MASK 0x00000800L 727 #define THM_TMON1_RDIR9_DATA__TEMP_MASK 0x00FFF000L 728 //THM_TMON1_RDIR10_DATA 729 #define THM_TMON1_RDIR10_DATA__Z__SHIFT 0x0 730 #define THM_TMON1_RDIR10_DATA__VALID__SHIFT 0xb 731 #define THM_TMON1_RDIR10_DATA__TEMP__SHIFT 0xc 732 #define THM_TMON1_RDIR10_DATA__Z_MASK 0x000007FFL 733 #define THM_TMON1_RDIR10_DATA__VALID_MASK 0x00000800L 734 #define THM_TMON1_RDIR10_DATA__TEMP_MASK 0x00FFF000L 735 //THM_TMON1_RDIR11_DATA 736 #define THM_TMON1_RDIR11_DATA__Z__SHIFT 0x0 737 #define THM_TMON1_RDIR11_DATA__VALID__SHIFT 0xb 738 #define THM_TMON1_RDIR11_DATA__TEMP__SHIFT 0xc 739 #define THM_TMON1_RDIR11_DATA__Z_MASK 0x000007FFL 740 #define THM_TMON1_RDIR11_DATA__VALID_MASK 0x00000800L 741 #define THM_TMON1_RDIR11_DATA__TEMP_MASK 0x00FFF000L 742 //THM_TMON1_RDIR12_DATA 743 #define THM_TMON1_RDIR12_DATA__Z__SHIFT 0x0 744 #define THM_TMON1_RDIR12_DATA__VALID__SHIFT 0xb 745 #define THM_TMON1_RDIR12_DATA__TEMP__SHIFT 0xc 746 #define THM_TMON1_RDIR12_DATA__Z_MASK 0x000007FFL 747 #define THM_TMON1_RDIR12_DATA__VALID_MASK 0x00000800L 748 #define THM_TMON1_RDIR12_DATA__TEMP_MASK 0x00FFF000L 749 //THM_TMON1_RDIR13_DATA 750 #define THM_TMON1_RDIR13_DATA__Z__SHIFT 0x0 751 #define THM_TMON1_RDIR13_DATA__VALID__SHIFT 0xb 752 #define THM_TMON1_RDIR13_DATA__TEMP__SHIFT 0xc 753 #define THM_TMON1_RDIR13_DATA__Z_MASK 0x000007FFL 754 #define THM_TMON1_RDIR13_DATA__VALID_MASK 0x00000800L 755 #define THM_TMON1_RDIR13_DATA__TEMP_MASK 0x00FFF000L 756 //THM_TMON1_RDIR14_DATA 757 #define THM_TMON1_RDIR14_DATA__Z__SHIFT 0x0 758 #define THM_TMON1_RDIR14_DATA__VALID__SHIFT 0xb 759 #define THM_TMON1_RDIR14_DATA__TEMP__SHIFT 0xc 760 #define THM_TMON1_RDIR14_DATA__Z_MASK 0x000007FFL 761 #define THM_TMON1_RDIR14_DATA__VALID_MASK 0x00000800L 762 #define THM_TMON1_RDIR14_DATA__TEMP_MASK 0x00FFF000L 763 //THM_TMON1_RDIR15_DATA 764 #define THM_TMON1_RDIR15_DATA__Z__SHIFT 0x0 765 #define THM_TMON1_RDIR15_DATA__VALID__SHIFT 0xb 766 #define THM_TMON1_RDIR15_DATA__TEMP__SHIFT 0xc 767 #define THM_TMON1_RDIR15_DATA__Z_MASK 0x000007FFL 768 #define THM_TMON1_RDIR15_DATA__VALID_MASK 0x00000800L 769 #define THM_TMON1_RDIR15_DATA__TEMP_MASK 0x00FFF000L 770 //THM_TMON1_INT_DATA 771 #define THM_TMON1_INT_DATA__Z__SHIFT 0x0 772 #define THM_TMON1_INT_DATA__VALID__SHIFT 0xb 773 #define THM_TMON1_INT_DATA__TEMP__SHIFT 0xc 774 #define THM_TMON1_INT_DATA__Z_MASK 0x000007FFL 775 #define THM_TMON1_INT_DATA__VALID_MASK 0x00000800L 776 #define THM_TMON1_INT_DATA__TEMP_MASK 0x00FFF000L 777 //THM_TMON1_DEBUG 778 #define THM_TMON1_DEBUG__DEBUG_RDI__SHIFT 0x0 779 #define THM_TMON1_DEBUG__DEBUG_Z__SHIFT 0x5 780 #define THM_TMON1_DEBUG__DEBUG_RDI_MASK 0x0000001FL 781 #define THM_TMON1_DEBUG__DEBUG_Z_MASK 0x0000FFE0L 782 //THM_DIE1_TEMP 783 #define THM_DIE1_TEMP__TEMP__SHIFT 0x0 784 #define THM_DIE1_TEMP__VALID__SHIFT 0xb 785 #define THM_DIE1_TEMP__TEMP_MASK 0x000007FFL 786 #define THM_DIE1_TEMP__VALID_MASK 0x00000800L 787 //THM_DIE2_TEMP 788 #define THM_DIE2_TEMP__TEMP__SHIFT 0x0 789 #define THM_DIE2_TEMP__VALID__SHIFT 0xb 790 #define THM_DIE2_TEMP__TEMP_MASK 0x000007FFL 791 #define THM_DIE2_TEMP__VALID_MASK 0x00000800L 792 //THM_DIE3_TEMP 793 #define THM_DIE3_TEMP__TEMP__SHIFT 0x0 794 #define THM_DIE3_TEMP__VALID__SHIFT 0xb 795 #define THM_DIE3_TEMP__TEMP_MASK 0x000007FFL 796 #define THM_DIE3_TEMP__VALID_MASK 0x00000800L 797 //CG_MULT_THERMAL_CTRL 798 #define CG_MULT_THERMAL_CTRL__TS_FILTER__SHIFT 0x0 799 #define CG_MULT_THERMAL_CTRL__UNUSED__SHIFT 0x4 800 #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST__SHIFT 0x9 801 #define CG_MULT_THERMAL_CTRL__TEMP_SEL__SHIFT 0x14 802 #define CG_MULT_THERMAL_CTRL__TS_FILTER_MASK 0x0000000FL 803 #define CG_MULT_THERMAL_CTRL__UNUSED_MASK 0x000001F0L 804 #define CG_MULT_THERMAL_CTRL__THERMAL_RANGE_RST_MASK 0x00000200L 805 #define CG_MULT_THERMAL_CTRL__TEMP_SEL_MASK 0x0FF00000L 806 //CG_MULT_THERMAL_STATUS 807 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP__SHIFT 0x0 808 #define CG_MULT_THERMAL_STATUS__CTF_TEMP__SHIFT 0x9 809 #define CG_MULT_THERMAL_STATUS__ASIC_MAX_TEMP_MASK 0x000001FFL 810 #define CG_MULT_THERMAL_STATUS__CTF_TEMP_MASK 0x0003FE00L 811 //THM_TMON0_COEFF 812 #define THM_TMON0_COEFF__C_OFFSET__SHIFT 0x0 813 #define THM_TMON0_COEFF__D__SHIFT 0xb 814 #define THM_TMON0_COEFF__C_OFFSET_MASK 0x000007FFL 815 #define THM_TMON0_COEFF__D_MASK 0x0003F800L 816 //THM_TMON1_COEFF 817 #define THM_TMON1_COEFF__C_OFFSET__SHIFT 0x0 818 #define THM_TMON1_COEFF__D__SHIFT 0xb 819 #define THM_TMON1_COEFF__C_OFFSET_MASK 0x000007FFL 820 #define THM_TMON1_COEFF__D_MASK 0x0003F800L 821 //CG_FDO_CTRL0 822 #define CG_FDO_CTRL0__FDO_STATIC_DUTY__SHIFT 0x0 823 #define CG_FDO_CTRL0__FAN_SPINUP_DUTY__SHIFT 0x8 824 #define CG_FDO_CTRL0__FDO_PWM_MANUAL__SHIFT 0x10 825 #define CG_FDO_CTRL0__FDO_PWM_HYSTER__SHIFT 0x11 826 #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN__SHIFT 0x17 827 #define CG_FDO_CTRL0__FDO_PWM_RAMP__SHIFT 0x18 828 #define CG_FDO_CTRL0__FDO_STATIC_DUTY_MASK 0x000000FFL 829 #define CG_FDO_CTRL0__FAN_SPINUP_DUTY_MASK 0x0000FF00L 830 #define CG_FDO_CTRL0__FDO_PWM_MANUAL_MASK 0x00010000L 831 #define CG_FDO_CTRL0__FDO_PWM_HYSTER_MASK 0x007E0000L 832 #define CG_FDO_CTRL0__FDO_PWM_RAMP_EN_MASK 0x00800000L 833 #define CG_FDO_CTRL0__FDO_PWM_RAMP_MASK 0xFF000000L 834 //CG_FDO_CTRL1 835 #define CG_FDO_CTRL1__FMAX_DUTY100__SHIFT 0x0 836 #define CG_FDO_CTRL1__FMIN_DUTY__SHIFT 0x8 837 #define CG_FDO_CTRL1__M__SHIFT 0x10 838 #define CG_FDO_CTRL1__RESERVED__SHIFT 0x18 839 #define CG_FDO_CTRL1__FMAX_DUTY100_MASK 0x000000FFL 840 #define CG_FDO_CTRL1__FMIN_DUTY_MASK 0x0000FF00L 841 #define CG_FDO_CTRL1__M_MASK 0x00FF0000L 842 #define CG_FDO_CTRL1__RESERVED_MASK 0x3F000000L 843 //CG_FDO_CTRL2 844 #define CG_FDO_CTRL2__TMIN__SHIFT 0x0 845 #define CG_FDO_CTRL2__FAN_SPINUP_TIME__SHIFT 0x8 846 #define CG_FDO_CTRL2__FDO_PWM_MODE__SHIFT 0xb 847 #define CG_FDO_CTRL2__TMIN_HYSTER__SHIFT 0xe 848 #define CG_FDO_CTRL2__TMAX__SHIFT 0x11 849 #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 850 #define CG_FDO_CTRL2__TMIN_MASK 0x000000FFL 851 #define CG_FDO_CTRL2__FAN_SPINUP_TIME_MASK 0x00000700L 852 #define CG_FDO_CTRL2__FDO_PWM_MODE_MASK 0x00003800L 853 #define CG_FDO_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 854 #define CG_FDO_CTRL2__TMAX_MASK 0x01FE0000L 855 #define CG_FDO_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 856 //CG_TACH_CTRL 857 #define CG_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 858 #define CG_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 859 #define CG_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 860 #define CG_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 861 //CG_TACH_STATUS 862 #define CG_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 863 #define CG_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 864 //CG_THERMAL_STATUS 865 #define CG_THERMAL_STATUS__FDO_PWM_DUTY__SHIFT 0x9 866 #define CG_THERMAL_STATUS__FDO_PWM_DUTY_MASK 0x0001FE00L 867 //CG_PUMP_CTRL0 868 #define CG_PUMP_CTRL0__PUMP_STATIC_DUTY__SHIFT 0x0 869 #define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY__SHIFT 0x8 870 #define CG_PUMP_CTRL0__PUMP_PWM_MANUAL__SHIFT 0x10 871 #define CG_PUMP_CTRL0__PUMP_PWM_HYSTER__SHIFT 0x11 872 #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN__SHIFT 0x17 873 #define CG_PUMP_CTRL0__PUMP_PWM_RAMP__SHIFT 0x18 874 #define CG_PUMP_CTRL0__PUMP_STATIC_DUTY_MASK 0x000000FFL 875 #define CG_PUMP_CTRL0__PUMP_SPINUP_DUTY_MASK 0x0000FF00L 876 #define CG_PUMP_CTRL0__PUMP_PWM_MANUAL_MASK 0x00010000L 877 #define CG_PUMP_CTRL0__PUMP_PWM_HYSTER_MASK 0x007E0000L 878 #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_EN_MASK 0x00800000L 879 #define CG_PUMP_CTRL0__PUMP_PWM_RAMP_MASK 0xFF000000L 880 //CG_PUMP_CTRL1 881 #define CG_PUMP_CTRL1__PMAX_DUTY100__SHIFT 0x0 882 #define CG_PUMP_CTRL1__PMIN_DUTY__SHIFT 0x8 883 #define CG_PUMP_CTRL1__M__SHIFT 0x10 884 #define CG_PUMP_CTRL1__RESERVED__SHIFT 0x18 885 #define CG_PUMP_CTRL1__PMAX_DUTY100_MASK 0x000000FFL 886 #define CG_PUMP_CTRL1__PMIN_DUTY_MASK 0x0000FF00L 887 #define CG_PUMP_CTRL1__M_MASK 0x00FF0000L 888 #define CG_PUMP_CTRL1__RESERVED_MASK 0x3F000000L 889 //CG_PUMP_CTRL2 890 #define CG_PUMP_CTRL2__TMIN__SHIFT 0x0 891 #define CG_PUMP_CTRL2__PUMP_SPINUP_TIME__SHIFT 0x8 892 #define CG_PUMP_CTRL2__PUMP_PWM_MODE__SHIFT 0xb 893 #define CG_PUMP_CTRL2__TMIN_HYSTER__SHIFT 0xe 894 #define CG_PUMP_CTRL2__TMAX__SHIFT 0x11 895 #define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE__SHIFT 0x19 896 #define CG_PUMP_CTRL2__TMIN_MASK 0x000000FFL 897 #define CG_PUMP_CTRL2__PUMP_SPINUP_TIME_MASK 0x00000700L 898 #define CG_PUMP_CTRL2__PUMP_PWM_MODE_MASK 0x00003800L 899 #define CG_PUMP_CTRL2__TMIN_HYSTER_MASK 0x0001C000L 900 #define CG_PUMP_CTRL2__TMAX_MASK 0x01FE0000L 901 #define CG_PUMP_CTRL2__TACH_PWM_RESP_RATE_MASK 0xFE000000L 902 //CG_PUMP_TACH_CTRL 903 #define CG_PUMP_TACH_CTRL__EDGE_PER_REV__SHIFT 0x0 904 #define CG_PUMP_TACH_CTRL__TARGET_PERIOD__SHIFT 0x3 905 #define CG_PUMP_TACH_CTRL__EDGE_PER_REV_MASK 0x00000007L 906 #define CG_PUMP_TACH_CTRL__TARGET_PERIOD_MASK 0xFFFFFFF8L 907 //CG_PUMP_TACH_STATUS 908 #define CG_PUMP_TACH_STATUS__TACH_PERIOD__SHIFT 0x0 909 #define CG_PUMP_TACH_STATUS__TACH_PERIOD_MASK 0xFFFFFFFFL 910 //CG_PUMP_STATUS 911 #define CG_PUMP_STATUS__PUMP_PWM_DUTY__SHIFT 0x9 912 #define CG_PUMP_STATUS__PUMP_PWM_DUTY_MASK 0x0001FE00L 913 //THM_TCON_LOCAL0 914 #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis__SHIFT 0x1 915 #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis__SHIFT 0x2 916 #define THM_TCON_LOCAL0__TMON0_PwrDn_Dis_MASK 0x00000002L 917 #define THM_TCON_LOCAL0__TMON1_PwrDn_Dis_MASK 0x00000004L 918 //THM_TCON_LOCAL1 919 #define THM_TCON_LOCAL1__Turn_Off_TMON0__SHIFT 0x0 920 #define THM_TCON_LOCAL1__Turn_Off_TMON1__SHIFT 0x1 921 #define THM_TCON_LOCAL1__PowerDownTmon0__SHIFT 0x4 922 #define THM_TCON_LOCAL1__PowerDownTmon1__SHIFT 0x5 923 #define THM_TCON_LOCAL1__Turn_Off_TMON0_MASK 0x00000001L 924 #define THM_TCON_LOCAL1__Turn_Off_TMON1_MASK 0x00000002L 925 #define THM_TCON_LOCAL1__PowerDownTmon0_MASK 0x00000010L 926 #define THM_TCON_LOCAL1__PowerDownTmon1_MASK 0x00000020L 927 //THM_TCON_LOCAL2 928 #define THM_TCON_LOCAL2__TMON_init_delay__SHIFT 0x0 929 #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time__SHIFT 0x2 930 #define THM_TCON_LOCAL2__short_stagger_count__SHIFT 0x5 931 #define THM_TCON_LOCAL2__sbtsi_use_corrected__SHIFT 0x6 932 #define THM_TCON_LOCAL2__temp_read_skip_scale__SHIFT 0xa 933 #define THM_TCON_LOCAL2__skip_scale_correction__SHIFT 0xb 934 #define THM_TCON_LOCAL2__TMON_init_delay_MASK 0x00000003L 935 #define THM_TCON_LOCAL2__TMON_pwrup_stagger_time_MASK 0x0000000CL 936 #define THM_TCON_LOCAL2__short_stagger_count_MASK 0x00000020L 937 #define THM_TCON_LOCAL2__sbtsi_use_corrected_MASK 0x00000040L 938 #define THM_TCON_LOCAL2__temp_read_skip_scale_MASK 0x00000400L 939 #define THM_TCON_LOCAL2__skip_scale_correction_MASK 0x00000800L 940 //THM_TCON_LOCAL3 941 #define THM_TCON_LOCAL3__Global_TMAX__SHIFT 0x0 942 #define THM_TCON_LOCAL3__Global_TMAX_MASK 0x000007FFL 943 //THM_TCON_LOCAL4 944 #define THM_TCON_LOCAL4__Global_TMAX_ID__SHIFT 0x0 945 #define THM_TCON_LOCAL4__Global_TMAX_ID_MASK 0x000000FFL 946 //THM_TCON_LOCAL5 947 #define THM_TCON_LOCAL5__Global_TMIN__SHIFT 0x0 948 #define THM_TCON_LOCAL5__Global_TMIN_MASK 0x000007FFL 949 //THM_TCON_LOCAL6 950 #define THM_TCON_LOCAL6__Global_TMIN_ID__SHIFT 0x0 951 #define THM_TCON_LOCAL6__Global_TMIN_ID_MASK 0x000000FFL 952 //THM_TCON_LOCAL7 953 #define THM_TCON_LOCAL7__THERMID__SHIFT 0x0 954 #define THM_TCON_LOCAL7__THERMID_MASK 0x000000FFL 955 //THM_TCON_LOCAL8 956 #define THM_TCON_LOCAL8__THERMMAX__SHIFT 0x0 957 #define THM_TCON_LOCAL8__THERMMAX_MASK 0x000007FFL 958 //THM_TCON_LOCAL9 959 #define THM_TCON_LOCAL9__Tj_Max_TMON0__SHIFT 0x0 960 #define THM_TCON_LOCAL9__Tj_Max_TMON0_MASK 0x000007FFL 961 //THM_TCON_LOCAL10 962 #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID__SHIFT 0x0 963 #define THM_TCON_LOCAL10__TMON0_Tj_Max_RS_ID_MASK 0x000000FFL 964 //THM_TCON_LOCAL11 965 #define THM_TCON_LOCAL11__Tj_Max_TMON1__SHIFT 0x0 966 #define THM_TCON_LOCAL11__Tj_Max_TMON1_MASK 0x000007FFL 967 //THM_TCON_LOCAL12 968 #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID__SHIFT 0x0 969 #define THM_TCON_LOCAL12__TMON1_Tj_Max_RS_ID_MASK 0x000000FFL 970 //THM_TCON_LOCAL13 971 #define THM_TCON_LOCAL13__boot_done__SHIFT 0x0 972 #define THM_TCON_LOCAL13__boot_done_MASK 0x00000001L 973 //THM_BACO_CNTL 974 #define THM_BACO_CNTL__BACO_MODE__SHIFT 0x0 975 #define THM_BACO_CNTL__BACO_ISO_EN__SHIFT 0x1 976 #define THM_BACO_CNTL__BACO_PWROKRAW_CNTL__SHIFT 0x2 977 #define THM_BACO_CNTL__BACO_RESET_EN__SHIFT 0x3 978 #define THM_BACO_CNTL__BACO_SOC_VDCI_RESET__SHIFT 0x4 979 #define THM_BACO_CNTL__BACO_SMNCLK_MUX__SHIFT 0x5 980 #define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF__SHIFT 0x6 981 #define THM_BACO_CNTL__BACO_AEB_ISO_EN__SHIFT 0x7 982 #define THM_BACO_CNTL__BACO_EXIT__SHIFT 0x8 983 #define THM_BACO_CNTL__BACO_ANA_ISO_EN__SHIFT 0x9 984 #define THM_BACO_CNTL__BACO_SB_AXI_FENCE__SHIFT 0x1e 985 #define THM_BACO_CNTL__SOC_DOMAIN_IDLE__SHIFT 0x1f 986 #define THM_BACO_CNTL__BACO_MODE_MASK 0x00000001L 987 #define THM_BACO_CNTL__BACO_ISO_EN_MASK 0x00000002L 988 #define THM_BACO_CNTL__BACO_PWROKRAW_CNTL_MASK 0x00000004L 989 #define THM_BACO_CNTL__BACO_RESET_EN_MASK 0x00000008L 990 #define THM_BACO_CNTL__BACO_SOC_VDCI_RESET_MASK 0x00000010L 991 #define THM_BACO_CNTL__BACO_SMNCLK_MUX_MASK 0x00000020L 992 #define THM_BACO_CNTL__BACO_SOC_REFCLK_OFF_MASK 0x00000040L 993 #define THM_BACO_CNTL__BACO_AEB_ISO_EN_MASK 0x00000080L 994 #define THM_BACO_CNTL__BACO_EXIT_MASK 0x00000100L 995 #define THM_BACO_CNTL__BACO_ANA_ISO_EN_MASK 0x00000200L 996 #define THM_BACO_CNTL__BACO_SB_AXI_FENCE_MASK 0x40000000L 997 #define THM_BACO_CNTL__SOC_DOMAIN_IDLE_MASK 0x80000000L 998 //THM_BACO_TIMING0 999 #define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT__SHIFT 0x0 1000 #define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT__SHIFT 0x8 1001 #define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT__SHIFT 0x10 1002 #define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT__SHIFT 0x18 1003 #define THM_BACO_TIMING0__BACO_ISO_EXIT_CNT_MASK 0x000000FFL 1004 #define THM_BACO_TIMING0__BACO_PWROKRAW_EXIT_CNT_MASK 0x0000FF00L 1005 #define THM_BACO_TIMING0__BACO_RESET_EXIT_CNT_MASK 0x00FF0000L 1006 #define THM_BACO_TIMING0__BACO_VDCI_RESET_EXIT_CNT_MASK 0xFF000000L 1007 //THM_BACO_TIMING1 1008 #define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT__SHIFT 0x0 1009 #define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT__SHIFT 0x8 1010 #define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT__SHIFT 0x10 1011 #define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT__SHIFT 0x18 1012 #define THM_BACO_TIMING1__BACO_SMNCLK_EXIT_CNT_MASK 0x000000FFL 1013 #define THM_BACO_TIMING1__BACO_FENCE_EXIT_CNT_MASK 0x0000FF00L 1014 #define THM_BACO_TIMING1__BACO_REFCLK_EXIT_CNT_MASK 0x00FF0000L 1015 #define THM_BACO_TIMING1__BACO_MODE_EXIT_CNT_MASK 0xFF000000L 1016 //XTAL_CNTL 1017 #define XTAL_CNTL__PCIE_REFCLK_SWITCH__SHIFT 0x0 1018 #define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN__SHIFT 0x4 1019 #define XTAL_CNTL__CORE_XTAL_PWDN__SHIFT 0x8 1020 #define XTAL_CNTL__OSC_GAIN_EN__SHIFT 0xc 1021 #define XTAL_CNTL__PCIE_REFCLK_SWITCH_MASK 0x00000001L 1022 #define XTAL_CNTL__CORE_XTAL_CLKGEN_CLKEN_MASK 0x00000010L 1023 #define XTAL_CNTL__CORE_XTAL_PWDN_MASK 0x00000100L 1024 #define XTAL_CNTL__OSC_GAIN_EN_MASK 0x00007000L 1025 //SBTSI_REMOTE_TEMP 1026 #define SBTSI_REMOTE_TEMP__RemoteTcenSensor__SHIFT 0x0 1027 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId__SHIFT 0xb 1028 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid__SHIFT 0x13 1029 #define SBTSI_REMOTE_TEMP__RemoteTcenSensor_MASK 0x000007FFL 1030 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorId_MASK 0x0007F800L 1031 #define SBTSI_REMOTE_TEMP__RemoteTcenSensorValid_MASK 0x00080000L 1032 //SBRMI_CONTROL 1033 #define SBRMI_CONTROL__READ_CMD_INT_DIS__SHIFT 0x0 1034 #define SBRMI_CONTROL__DPD__SHIFT 0x1 1035 #define SBRMI_CONTROL__DbrdySts__SHIFT 0x2 1036 #define SBRMI_CONTROL__READ_CMD_INT_DIS_MASK 0x00000001L 1037 #define SBRMI_CONTROL__DPD_MASK 0x00000002L 1038 #define SBRMI_CONTROL__DbrdySts_MASK 0x00000004L 1039 //SBRMI_COMMAND 1040 #define SBRMI_COMMAND__Command__SHIFT 0x0 1041 #define SBRMI_COMMAND__WrDataLen__SHIFT 0x8 1042 #define SBRMI_COMMAND__RdDataLen__SHIFT 0x10 1043 #define SBRMI_COMMAND__CommandSent__SHIFT 0x18 1044 #define SBRMI_COMMAND__CommandNotSupported__SHIFT 0x19 1045 #define SBRMI_COMMAND__CommandAborted__SHIFT 0x1a 1046 #define SBRMI_COMMAND__Status__SHIFT 0x1c 1047 #define SBRMI_COMMAND__Command_MASK 0x000000FFL 1048 #define SBRMI_COMMAND__WrDataLen_MASK 0x0000FF00L 1049 #define SBRMI_COMMAND__RdDataLen_MASK 0x00FF0000L 1050 #define SBRMI_COMMAND__CommandSent_MASK 0x01000000L 1051 #define SBRMI_COMMAND__CommandNotSupported_MASK 0x02000000L 1052 #define SBRMI_COMMAND__CommandAborted_MASK 0x04000000L 1053 #define SBRMI_COMMAND__Status_MASK 0xF0000000L 1054 //SBRMI_WRITE_DATA0 1055 #define SBRMI_WRITE_DATA0__WrByte0__SHIFT 0x0 1056 #define SBRMI_WRITE_DATA0__WrByte1__SHIFT 0x8 1057 #define SBRMI_WRITE_DATA0__WrByte2__SHIFT 0x10 1058 #define SBRMI_WRITE_DATA0__WrByte3__SHIFT 0x18 1059 #define SBRMI_WRITE_DATA0__WrByte0_MASK 0x000000FFL 1060 #define SBRMI_WRITE_DATA0__WrByte1_MASK 0x0000FF00L 1061 #define SBRMI_WRITE_DATA0__WrByte2_MASK 0x00FF0000L 1062 #define SBRMI_WRITE_DATA0__WrByte3_MASK 0xFF000000L 1063 //SBRMI_WRITE_DATA1 1064 #define SBRMI_WRITE_DATA1__WrByte4__SHIFT 0x0 1065 #define SBRMI_WRITE_DATA1__WrByte5__SHIFT 0x8 1066 #define SBRMI_WRITE_DATA1__WrByte6__SHIFT 0x10 1067 #define SBRMI_WRITE_DATA1__WrByte7__SHIFT 0x18 1068 #define SBRMI_WRITE_DATA1__WrByte4_MASK 0x000000FFL 1069 #define SBRMI_WRITE_DATA1__WrByte5_MASK 0x0000FF00L 1070 #define SBRMI_WRITE_DATA1__WrByte6_MASK 0x00FF0000L 1071 #define SBRMI_WRITE_DATA1__WrByte7_MASK 0xFF000000L 1072 //SBRMI_WRITE_DATA2 1073 #define SBRMI_WRITE_DATA2__WrByte8__SHIFT 0x0 1074 #define SBRMI_WRITE_DATA2__WrByte9__SHIFT 0x8 1075 #define SBRMI_WRITE_DATA2__WrByte10__SHIFT 0x10 1076 #define SBRMI_WRITE_DATA2__WrByte11__SHIFT 0x18 1077 #define SBRMI_WRITE_DATA2__WrByte8_MASK 0x000000FFL 1078 #define SBRMI_WRITE_DATA2__WrByte9_MASK 0x0000FF00L 1079 #define SBRMI_WRITE_DATA2__WrByte10_MASK 0x00FF0000L 1080 #define SBRMI_WRITE_DATA2__WrByte11_MASK 0xFF000000L 1081 //SBRMI_READ_DATA0 1082 #define SBRMI_READ_DATA0__RdByte0__SHIFT 0x0 1083 #define SBRMI_READ_DATA0__RdByte1__SHIFT 0x8 1084 #define SBRMI_READ_DATA0__RdByte2__SHIFT 0x10 1085 #define SBRMI_READ_DATA0__RdByte3__SHIFT 0x18 1086 #define SBRMI_READ_DATA0__RdByte0_MASK 0x000000FFL 1087 #define SBRMI_READ_DATA0__RdByte1_MASK 0x0000FF00L 1088 #define SBRMI_READ_DATA0__RdByte2_MASK 0x00FF0000L 1089 #define SBRMI_READ_DATA0__RdByte3_MASK 0xFF000000L 1090 //SBRMI_READ_DATA1 1091 #define SBRMI_READ_DATA1__RdByte4__SHIFT 0x0 1092 #define SBRMI_READ_DATA1__RdByte5__SHIFT 0x8 1093 #define SBRMI_READ_DATA1__RdByte6__SHIFT 0x10 1094 #define SBRMI_READ_DATA1__RdByte7__SHIFT 0x18 1095 #define SBRMI_READ_DATA1__RdByte4_MASK 0x000000FFL 1096 #define SBRMI_READ_DATA1__RdByte5_MASK 0x0000FF00L 1097 #define SBRMI_READ_DATA1__RdByte6_MASK 0x00FF0000L 1098 #define SBRMI_READ_DATA1__RdByte7_MASK 0xFF000000L 1099 //SBRMI_CORE_EN_NUMBER 1100 #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum__SHIFT 0x0 1101 #define SBRMI_CORE_EN_NUMBER__EnabledCoreNum_MASK 0x0000007FL 1102 //SBRMI_CORE_EN_STATUS0 1103 #define SBRMI_CORE_EN_STATUS0__CoreEnStat0__SHIFT 0x0 1104 #define SBRMI_CORE_EN_STATUS0__CoreEnStat0_MASK 0xFFFFFFFFL 1105 //SBRMI_CORE_EN_STATUS1 1106 #define SBRMI_CORE_EN_STATUS1__CoreEnStat1__SHIFT 0x0 1107 #define SBRMI_CORE_EN_STATUS1__CoreEnStat1_MASK 0xFFFFFFFFL 1108 //SBRMI_APIC_STATUS0 1109 #define SBRMI_APIC_STATUS0__APICStat0__SHIFT 0x0 1110 #define SBRMI_APIC_STATUS0__APICStat0_MASK 0xFFFFFFFFL 1111 //SBRMI_APIC_STATUS1 1112 #define SBRMI_APIC_STATUS1__APICStat1__SHIFT 0x0 1113 #define SBRMI_APIC_STATUS1__APICStat1_MASK 0xFFFFFFFFL 1114 //SBRMI_MCE_STATUS0 1115 #define SBRMI_MCE_STATUS0__MceStat0__SHIFT 0x0 1116 #define SBRMI_MCE_STATUS0__MceStat0_MASK 0xFFFFFFFFL 1117 //SBRMI_MCE_STATUS1 1118 #define SBRMI_MCE_STATUS1__MceStat1__SHIFT 0x0 1119 #define SBRMI_MCE_STATUS1__MceStat1_MASK 0xFFFFFFFFL 1120 //SMBUS_CNTL0 1121 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE__SHIFT 0x0 1122 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR__SHIFT 0x1 1123 #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE__SHIFT 0x8 1124 #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES__SHIFT 0x10 1125 #define SMBUS_CNTL0__THM_READY__SHIFT 0x14 1126 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_OVERRIDE_MASK 0x00000001L 1127 #define SMBUS_CNTL0__SMB_DEFAULT_SLV_ADDR_MASK 0x000000FEL 1128 #define SMBUS_CNTL0__SMB_CPL_DUMMY_BYTE_MASK 0x0000FF00L 1129 #define SMBUS_CNTL0__SMB_NOTIFY_ARP_MAX_TIMES_MASK 0x00070000L 1130 #define SMBUS_CNTL0__THM_READY_MASK 0x00100000L 1131 //SMBUS_CNTL1 1132 #define SMBUS_CNTL1__SMB_TIMEOUT_EN__SHIFT 0x0 1133 #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN__SHIFT 0x1 1134 #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN__SHIFT 0x9 1135 #define SMBUS_CNTL1__SMB_TIMEOUT_EN_MASK 0x00000001L 1136 #define SMBUS_CNTL1__SMB_BLK_WR_CMD_EN_MASK 0x000001FEL 1137 #define SMBUS_CNTL1__SMB_BLK_RD_CMD_EN_MASK 0x0001FE00L 1138 //SMBUS_BLKWR_CMD_CTRL0 1139 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0__SHIFT 0x0 1140 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1__SHIFT 0x8 1141 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2__SHIFT 0x10 1142 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3__SHIFT 0x18 1143 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD0_MASK 0x000000FFL 1144 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD1_MASK 0x0000FF00L 1145 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD2_MASK 0x00FF0000L 1146 #define SMBUS_BLKWR_CMD_CTRL0__SMB_BLK_WR_CMD3_MASK 0xFF000000L 1147 //SMBUS_BLKWR_CMD_CTRL1 1148 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4__SHIFT 0x0 1149 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5__SHIFT 0x8 1150 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6__SHIFT 0x10 1151 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7__SHIFT 0x18 1152 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD4_MASK 0x000000FFL 1153 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD5_MASK 0x0000FF00L 1154 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD6_MASK 0x00FF0000L 1155 #define SMBUS_BLKWR_CMD_CTRL1__SMB_BLK_WR_CMD7_MASK 0xFF000000L 1156 //SMBUS_BLKRD_CMD_CTRL0 1157 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0__SHIFT 0x0 1158 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1__SHIFT 0x8 1159 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2__SHIFT 0x10 1160 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3__SHIFT 0x18 1161 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD0_MASK 0x000000FFL 1162 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD1_MASK 0x0000FF00L 1163 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD2_MASK 0x00FF0000L 1164 #define SMBUS_BLKRD_CMD_CTRL0__SMB_BLK_RD_CMD3_MASK 0xFF000000L 1165 //SMBUS_BLKRD_CMD_CTRL1 1166 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4__SHIFT 0x0 1167 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5__SHIFT 0x8 1168 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6__SHIFT 0x10 1169 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7__SHIFT 0x18 1170 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD4_MASK 0x000000FFL 1171 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD5_MASK 0x0000FF00L 1172 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD6_MASK 0x00FF0000L 1173 #define SMBUS_BLKRD_CMD_CTRL1__SMB_BLK_RD_CMD7_MASK 0xFF000000L 1174 //SMBUS_TIMING_CNTL0 1175 #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN__SHIFT 0x0 1176 #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN__SHIFT 0x16 1177 #define SMBUS_TIMING_CNTL0__SMB_TIMEOUT_MARGIN_MASK 0x003FFFFFL 1178 #define SMBUS_TIMING_CNTL0__SMB_FILTER_LEVEL_CONVERT_MARGIN_MASK 0x3FC00000L 1179 //SMBUS_TIMING_CNTL1 1180 #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN__SHIFT 0x0 1181 #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN__SHIFT 0x5 1182 #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN__SHIFT 0xb 1183 #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN__SHIFT 0x14 1184 #define SMBUS_TIMING_CNTL1__SMB_DAT_SETUP_TIME_MARGIN_MASK 0x0000001FL 1185 #define SMBUS_TIMING_CNTL1__SMB_DAT_HOLD_TIME_MARGIN_MASK 0x000007E0L 1186 #define SMBUS_TIMING_CNTL1__SMB_START_AND_STOP_TIMING_MARGIN_MASK 0x000FF800L 1187 #define SMBUS_TIMING_CNTL1__SMB_BUS_FREE_MARGIN_MASK 0x3FF00000L 1188 //SMBUS_TIMING_CNTL2 1189 #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN__SHIFT 0x0 1190 #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN__SHIFT 0xd 1191 #define SMBUS_TIMING_CNTL2__SMB_SMBCLK_HIGHMAX_MARGIN_MASK 0x00001FFFL 1192 #define SMBUS_TIMING_CNTL2__SMBCLK_LEVEL_CTRL_MARGIN_MASK 0x07FFE000L 1193 //SMBUS_TRIGGER_CNTL 1194 #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER__SHIFT 0x0 1195 #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER__SHIFT 0x8 1196 #define SMBUS_TRIGGER_CNTL__SMB_SOFT_RESET_TRIGGER_MASK 0x00000001L 1197 #define SMBUS_TRIGGER_CNTL__SMB_NOTIFY_ARP_TRIGGER_MASK 0x00000100L 1198 //SMBUS_UDID_CNTL0 1199 #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED__SHIFT 0x0 1200 #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN__SHIFT 0x1f 1201 #define SMBUS_UDID_CNTL0__SMB_PRBS_INI_SEED_MASK 0x7FFFFFFFL 1202 #define SMBUS_UDID_CNTL0__SMB_SRST_REGEN_UDID_EN_MASK 0x80000000L 1203 //SMBUS_UDID_CNTL1 1204 #define SMBUS_UDID_CNTL1__SMB_UDID_31_0__SHIFT 0x0 1205 #define SMBUS_UDID_CNTL1__SMB_UDID_31_0_MASK 0xFFFFFFFFL 1206 //SMBUS_UDID_CNTL2 1207 #define SMBUS_UDID_CNTL2__PEC_SUPPORTED__SHIFT 0x0 1208 #define SMBUS_UDID_CNTL2__UDID_VERSION__SHIFT 0x1 1209 #define SMBUS_UDID_CNTL2__SMBUS_VERSION__SHIFT 0x4 1210 #define SMBUS_UDID_CNTL2__OEM__SHIFT 0x8 1211 #define SMBUS_UDID_CNTL2__ASF__SHIFT 0x9 1212 #define SMBUS_UDID_CNTL2__IPMI__SHIFT 0xa 1213 #define SMBUS_UDID_CNTL2__PEC_SUPPORTED_MASK 0x00000001L 1214 #define SMBUS_UDID_CNTL2__UDID_VERSION_MASK 0x0000000EL 1215 #define SMBUS_UDID_CNTL2__SMBUS_VERSION_MASK 0x000000F0L 1216 #define SMBUS_UDID_CNTL2__OEM_MASK 0x00000100L 1217 #define SMBUS_UDID_CNTL2__ASF_MASK 0x00000200L 1218 #define SMBUS_UDID_CNTL2__IPMI_MASK 0x00000400L 1219 //SMBUS_BACO_DUMMY 1220 #define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA__SHIFT 0x0 1221 #define SMBUS_BACO_DUMMY__BACO_DUMMY_DATA_MASK 0xFFFFFFFFL 1222 //SMBUS_BACO_ADDR_RANGE0_LOW 1223 #define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW__SHIFT 0x0 1224 #define SMBUS_BACO_ADDR_RANGE0_LOW__BACO_ADDR_RANGE0_LOW_MASK 0x000FFFFFL 1225 //SMBUS_BACO_ADDR_RANGE0_HIGH 1226 #define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH__SHIFT 0x0 1227 #define SMBUS_BACO_ADDR_RANGE0_HIGH__BACO_ADDR_RANGE0_HIGH_MASK 0x000FFFFFL 1228 //SMBUS_BACO_ADDR_RANGE1_LOW 1229 #define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW__SHIFT 0x0 1230 #define SMBUS_BACO_ADDR_RANGE1_LOW__BACO_ADDR_RANGE1_LOW_MASK 0x000FFFFFL 1231 //SMBUS_BACO_ADDR_RANGE1_HIGH 1232 #define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH__SHIFT 0x0 1233 #define SMBUS_BACO_ADDR_RANGE1_HIGH__BACO_ADDR_RANGE1_HIGH_MASK 0x000FFFFFL 1234 //SMBUS_BACO_ADDR_RANGE2_LOW 1235 #define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW__SHIFT 0x0 1236 #define SMBUS_BACO_ADDR_RANGE2_LOW__BACO_ADDR_RANGE2_LOW_MASK 0x000FFFFFL 1237 //SMBUS_BACO_ADDR_RANGE2_HIGH 1238 #define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH__SHIFT 0x0 1239 #define SMBUS_BACO_ADDR_RANGE2_HIGH__BACO_ADDR_RANGE2_HIGH_MASK 0x000FFFFFL 1240 //SMBUS_BACO_ADDR_RANGE3_LOW 1241 #define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW__SHIFT 0x0 1242 #define SMBUS_BACO_ADDR_RANGE3_LOW__BACO_ADDR_RANGE3_LOW_MASK 0x000FFFFFL 1243 //SMBUS_BACO_ADDR_RANGE3_HIGH 1244 #define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH__SHIFT 0x0 1245 #define SMBUS_BACO_ADDR_RANGE3_HIGH__BACO_ADDR_RANGE3_HIGH_MASK 0x000FFFFFL 1246 //SMBUS_BACO_ADDR_RANGE4_LOW 1247 #define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW__SHIFT 0x0 1248 #define SMBUS_BACO_ADDR_RANGE4_LOW__BACO_ADDR_RANGE4_LOW_MASK 0x000FFFFFL 1249 //SMBUS_BACO_ADDR_RANGE4_HIGH 1250 #define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH__SHIFT 0x0 1251 #define SMBUS_BACO_ADDR_RANGE4_HIGH__BACO_ADDR_RANGE4_HIGH_MASK 0x000FFFFFL 1252 //THM_GPIO_MACO_EN_CTRL 1253 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL__SHIFT 0x0 1254 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD__SHIFT 0x1 1255 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU__SHIFT 0x2 1256 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN__SHIFT 0x3 1257 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0__SHIFT 0x4 1258 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1__SHIFT 0x5 1259 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN__SHIFT 0x6 1260 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0__SHIFT 0x7 1261 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1__SHIFT 0x8 1262 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE__SHIFT 0x10 1263 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE__SHIFT 0x11 1264 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE__SHIFT 0x12 1265 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_A__SHIFT 0x13 1266 #define THM_GPIO_MACO_EN_CTRL__Y__SHIFT 0x1f 1267 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_TXIMPSEL_MASK 0x00000001L 1268 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_PD_MASK 0x00000002L 1269 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_PU_MASK 0x00000004L 1270 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_SCHMEN_MASK 0x00000008L 1271 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_S0_MASK 0x00000010L 1272 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_S1_MASK 0x00000020L 1273 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXEN_MASK 0x00000040L 1274 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL0_MASK 0x00000080L 1275 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_RXSEL1_MASK 0x00000100L 1276 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_OVERRIDE_MASK 0x00010000L 1277 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_OE_MASK 0x00020000L 1278 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_OVERRIDE_MASK 0x00040000L 1279 #define THM_GPIO_MACO_EN_CTRL__MACO_EN_A_MASK 0x00080000L 1280 #define THM_GPIO_MACO_EN_CTRL__Y_MASK 0x80000000L 1281 //THM_BACO_TIMING2 1282 #define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT__SHIFT 0x0 1283 #define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT__SHIFT 0x8 1284 #define THM_BACO_TIMING2__BACO_EXIT_CNT__SHIFT 0x10 1285 #define THM_BACO_TIMING2__BACO_AEB_ISO_EXIT_CNT_MASK 0x000000FFL 1286 #define THM_BACO_TIMING2__BACO_ANA_ISO_EXIT_CNT_MASK 0x0000FF00L 1287 #define THM_BACO_TIMING2__BACO_EXIT_CNT_MASK 0x00FF0000L 1288 //THM_BACO_TIMING 1289 #define THM_BACO_TIMING__BACO_RESET_DELAY__SHIFT 0x0 1290 #define THM_BACO_TIMING__BACO_RESET_DELAY_MASK 0x0000FFFFL 1291 //THM_TMON0_REMOTE_START 1292 #define THM_TMON0_REMOTE_START__DATA__SHIFT 0x0 1293 #define THM_TMON0_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1294 //THM_TMON0_REMOTE_END 1295 #define THM_TMON0_REMOTE_END__DATA__SHIFT 0x0 1296 #define THM_TMON0_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1297 //THM_TMON1_REMOTE_START 1298 #define THM_TMON1_REMOTE_START__DATA__SHIFT 0x0 1299 #define THM_TMON1_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1300 //THM_TMON1_REMOTE_END 1301 #define THM_TMON1_REMOTE_END__DATA__SHIFT 0x0 1302 #define THM_TMON1_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1303 //THM_TMON2_REMOTE_START 1304 #define THM_TMON2_REMOTE_START__DATA__SHIFT 0x0 1305 #define THM_TMON2_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1306 //THM_TMON2_REMOTE_END 1307 #define THM_TMON2_REMOTE_END__DATA__SHIFT 0x0 1308 #define THM_TMON2_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1309 //THM_TMON3_REMOTE_START 1310 #define THM_TMON3_REMOTE_START__DATA__SHIFT 0x0 1311 #define THM_TMON3_REMOTE_START__DATA_MASK 0xFFFFFFFFL 1312 //THM_TMON3_REMOTE_END 1313 #define THM_TMON3_REMOTE_END__DATA__SHIFT 0x0 1314 #define THM_TMON3_REMOTE_END__DATA_MASK 0xFFFFFFFFL 1315 1316 #endif 1317
Indexes created Wed Oct 01 07:09:59 GMT 2025