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      1 /*	$NetBSD: i8253reg.h,v 1.9 2005/12/11 12:21:26 christos Exp $	*/
      2 
      3 /*-
      4  * Copyright (c) 1993 The Regents of the University of California.
      5  * All rights reserved.
      6  *
      7  * Redistribution and use in source and binary forms, with or without
      8  * modification, are permitted provided that the following conditions
      9  * are met:
     10  * 1. Redistributions of source code must retain the above copyright
     11  *    notice, this list of conditions and the following disclaimer.
     12  * 2. Redistributions in binary form must reproduce the above copyright
     13  *    notice, this list of conditions and the following disclaimer in the
     14  *    documentation and/or other materials provided with the distribution.
     15  * 3. Neither the name of the University nor the names of its contributors
     16  *    may be used to endorse or promote products derived from this software
     17  *    without specific prior written permission.
     18  *
     19  * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND
     20  * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
     21  * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
     22  * ARE DISCLAIMED.  IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE
     23  * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
     24  * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
     25  * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
     26  * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
     27  * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
     28  * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
     29  * SUCH DAMAGE.
     30  */
     31 
     32 /*
     33  * Register definitions for the Intel 8253 Programmable Interval Timer.
     34  *
     35  * This chip has three independent 16-bit down counters that can be
     36  * read on the fly.  There are three mode registers and three countdown
     37  * registers.  The countdown registers are addressed directly, via the
     38  * first three I/O ports.  The three mode registers are accessed via
     39  * the fourth I/O port, with two bits in the mode byte indicating the
     40  * register.  (Why are hardware interfaces always so braindead?).
     41  *
     42  * To write a value into the countdown register, the mode register
     43  * is first programmed with a command indicating the which byte of
     44  * the two byte register is to be modified.  The three possibilities
     45  * are load msb (TMR_MR_MSB), load lsb (TMR_MR_LSB), or load lsb then
     46  * msb (TMR_MR_BOTH).
     47  *
     48  * To read the current value ("on the fly") from the countdown register,
     49  * you write a "latch" command into the mode register, then read the stable
     50  * value from the corresponding I/O port.  For example, you write
     51  * TMR_MR_LATCH into the corresponding mode register.  Presumably,
     52  * after doing this, a write operation to the I/O port would result
     53  * in undefined behavior (but hopefully not fry the chip).
     54  * Reading in this manner has no side effects.
     55  *
     56  * The outputs of the three timers are connected as follows:
     57  *
     58  *	 timer 0 -> irq 0
     59  *	 timer 1 -> DMA chan 0 (for dram refresh)
     60  * 	 timer 2 -> speaker (via keyboard controller)
     61  *
     62  * Timer 0 is used to call hardclock.
     63  * Timer 2 is used to generate console beeps.
     64  */
     65 
     66 /*
     67  * Frequency of all three count-down timers; (TIMER_FREQ/freq) is the
     68  * appropriate count to generate a frequency of freq Hz.
     69  */
     70 #ifndef TIMER_FREQ
     71 #define	TIMER_FREQ	1193182
     72 #endif
     73 #define TIMER_DIV(x) ((TIMER_FREQ+(x)/2)/(x))
     74 
     75 /*
     76  * Macros for specifying values to be written into a mode register.
     77  */
     78 #define	TIMER_CNTR0	0	/* timer 0 counter port */
     79 #define	TIMER_CNTR1	1	/* timer 1 counter port */
     80 #define	TIMER_CNTR2	2	/* timer 2 counter port */
     81 #define	TIMER_MODE	3	/* timer mode port */
     82 #define		TIMER_SEL0	0x00	/* select counter 0 */
     83 #define		TIMER_SEL1	0x40	/* select counter 1 */
     84 #define		TIMER_SEL2	0x80	/* select counter 2 */
     85 #define		TIMER_INTTC	0x00	/* mode 0, intr on terminal cnt */
     86 #define		TIMER_ONESHOT	0x02	/* mode 1, one shot */
     87 #define		TIMER_RATEGEN	0x04	/* mode 2, rate generator */
     88 #define		TIMER_SQWAVE	0x06	/* mode 3, square wave */
     89 #define		TIMER_SWSTROBE	0x08	/* mode 4, s/w triggered strobe */
     90 #define		TIMER_HWSTROBE	0x0a	/* mode 5, h/w triggered strobe */
     91 #define		TIMER_LATCH	0x00	/* latch counter for reading */
     92 #define		TIMER_LSB	0x10	/* r/w counter LSB */
     93 #define		TIMER_MSB	0x20	/* r/w counter MSB */
     94 #define		TIMER_16BIT	0x30	/* r/w counter 16 bits, LSB first */
     95 #define		TIMER_BCD	0x01	/* count in BCD */
     96 
     97