1 /* $NetBSD: vaddrs.h,v 1.11 2001/12/10 23:10:34 uwe Exp $ */ 2 3 /* 4 * Copyright (c) 1996 5 * The President and Fellows of Harvard College. All rights reserved. 6 * Copyright (c) 1992, 1993 7 * The Regents of the University of California. All rights reserved. 8 * 9 * This software was developed by the Computer Systems Engineering group 10 * at Lawrence Berkeley Laboratory under DARPA contract BG 91-66 and 11 * contributed to Berkeley. 12 * 13 * All advertising materials mentioning features or use of this software 14 * must display the following acknowledgement: 15 * This product includes software developed by the University of 16 * California, Lawrence Berkeley Laboratory. 17 * 18 * Redistribution and use in source and binary forms, with or without 19 * modification, are permitted provided that the following conditions 20 * are met: 21 * 1. Redistributions of source code must retain the above copyright 22 * notice, this list of conditions and the following disclaimer. 23 * 2. Redistributions in binary form must reproduce the above copyright 24 * notice, this list of conditions and the following disclaimer in the 25 * documentation and/or other materials provided with the distribution. 26 * 3. All advertising materials mentioning features or use of this software 27 * must display the following acknowledgement: 28 * This product includes software developed by the University of 29 * California, Berkeley and its contributors. 30 * This product includes software developed by Harvard University. 31 * 4. Neither the name of the University nor the names of its contributors 32 * may be used to endorse or promote products derived from this software 33 * without specific prior written permission. 34 * 35 * THIS SOFTWARE IS PROVIDED BY THE REGENTS AND CONTRIBUTORS ``AS IS'' AND 36 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 37 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 38 * ARE DISCLAIMED. IN NO EVENT SHALL THE REGENTS OR CONTRIBUTORS BE LIABLE 39 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 40 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 41 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 42 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 43 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 44 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 45 * SUCH DAMAGE. 46 * 47 * @(#)vaddrs.h 8.1 (Berkeley) 6/11/93 48 */ 49 50 /* 51 * Special (fixed) virtual addresses on the SPARC. 52 * 53 * IO virtual space begins at 0xfe000000 (a segment boundary) and 54 * continues up to the DMVA edge at 0xff000000. (The upper all-1s 55 * byte is special since some of the hardware supplies this to pad 56 * a 24-bit address space out to 32 bits. This is a legacy of the 57 * IBM PC AT bus, actually, just so you know who to blame.) 58 * 59 * We reserve several pages at the base of our IO virtual space 60 * for `oft-used' devices which must be present anyway in order to 61 * configure. In particular, we want the counter-timer register and 62 * the Zilog ZSCC serial port chips to be mapped at fixed VAs to make 63 * microtime() and the zs hardware interrupt handlers faster. 64 * 65 * [sun4/sun4c:] 66 * Ideally, we should map the interrupt enable register here as well, 67 * but that would require allocating pmegs in locore.s, so instead we 68 * use one of the two `wasted' pages at KERNBASE+_MAXNBPG (see locore.s). 69 */ 70 71 #ifndef IODEV_0 72 #define IODEV_0 0xfe000000 /* must match VM_MAX_KERNEL_ADDRESS */ 73 74 #define _MAXNBPG 8192 /* fixed VAs, independent of actual NBPG */ 75 #define _MAXNCPU 4 /* fixed VA allocation allows 4 CPUs */ 76 77 /* [4m:] interrupt and counter registers take (1 + NCPU) pages. */ 78 79 #define TIMERREG_VA (IODEV_0) 80 #define COUNTERREG_VA ( TIMERREG_VA + _MAXNBPG*_MAXNCPU) /* [4m] */ 81 #define ZS0_VA (COUNTERREG_VA + _MAXNBPG) 82 #define ZS1_VA ( ZS0_VA + _MAXNBPG) 83 #define AUXREG_VA ( ZS1_VA + _MAXNBPG) 84 #define TMPMAP_VA ( AUXREG_VA + _MAXNBPG) 85 #define MSGBUF_VA ( TMPMAP_VA + _MAXNBPG) 86 #define INTRREG_VA ( MSGBUF_VA + _MAXNBPG) /* [4/4c] */ 87 #define MSIIEP_PCIC_VA ( MSGBUF_VA + _MAXNBPG) /* [IIep] */ 88 #define PI_INTR_VA ( MSGBUF_VA + _MAXNBPG) /* [4m] */ 89 #define SI_INTR_VA ( PI_INTR_VA + _MAXNBPG*_MAXNCPU) /* [4m] */ 90 #define IODEV_BASE ( SI_INTR_VA + _MAXNBPG) 91 #define IODEV_END 0xff000000 /* 16 MB of iospace */ 92 93 /* 94 * DVMA range for 24 bit devices. 95 */ 96 #define D24_DVMA_BASE 0xff000000 97 #define D24_DVMA_END VME4_DVMA_BASE 98 99 /* 100 * DMA on sun4 VME devices use the last MB of virtual space, which 101 * is mapped by hardware onto the first MB of VME space. 102 * The DVMA area ends before the PROM mappings appear in the address space. 103 */ 104 #define VME4_DVMA_BASE 0xfff00000 105 #define VME4_DVMA_END 0xfffc0000 106 107 /* 108 * The next constant defines the amount of reserved DVMA space on the 109 * IOMMU in sun4m machines. The amount of space *must* be a multiple 110 * of 16MB, and thus (((u_int)0) - IOMMU_DVMA_BASE) must be divisible 111 * by 16*1024*1024! Note that pagetables must be allocated at a cost 112 * of 1k per MB of DVMA space, plus severe alignment restrictions. So 113 * don't make IOMMU_DVMA_BASE too low (max space = 2G). 114 * 115 * Also note that the IOMMU DVMA range must include the D24 DVMA range 116 * defined above to be able to map legacy (sbus) devices that have 117 * their upper address bits hardwired to 0xff. 118 */ 119 #define IOMMU_DVMA_BASE 0xfc000000 /* can change subject to above rule */ 120 /* 121 * We could use all of DVMA space up to 0x100000000, but we cannot 122 * represent that number in an `unsigned long' which is necessary 123 * for extent(9). So we leave the very last page unused. 124 */ 125 #define IOMMU_DVMA_END 0xfffff000 /* one page short of the end of space */ 126 127 /* 128 * Virtual address of the per cpu `cpu_softc' structure. 129 */ 130 #define CPUINFO_VA (KERNBASE+8192) 131 132 #endif /* IODEV_0 */ 133
Indexes created Sat Sep 20 22:09:52 GMT 2025