1 /* $NetBSD: dcn20_mmhubbub.h,v 1.2 2021/12/18 23:45:03 riastradh Exp $ */ 2 3 /* 4 * Copyright 2012-15 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: AMD 25 * 26 */ 27 28 #ifndef __DC_MCIF_WB_DCN20_H__ 29 #define __DC_MCIF_WB_DCN20_H__ 30 31 #define TO_DCN20_MMHUBBUB(mcif_wb_base) \ 32 container_of(mcif_wb_base, struct dcn20_mmhubbub, base) 33 34 /* DCN */ 35 #define BASE_INNER(seg) \ 36 DCE_BASE__INST0_SEG ## seg 37 38 #define BASE(seg) \ 39 BASE_INNER(seg) 40 41 #define SR(reg_name)\ 42 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 43 mm ## reg_name 44 45 #define SRI(reg_name, block, id)\ 46 .reg_name = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 47 mm ## block ## id ## _ ## reg_name 48 49 #define SRI2(reg_name, block, id)\ 50 .reg_name = BASE(mm ## reg_name ## _BASE_IDX) + \ 51 mm ## reg_name 52 53 #define SRII(reg_name, block, id)\ 54 .reg_name[id] = BASE(mm ## block ## id ## _ ## reg_name ## _BASE_IDX) + \ 55 mm ## block ## id ## _ ## reg_name 56 57 #define SF(reg_name, field_name, post_fix)\ 58 .field_name = reg_name ## __ ## field_name ## post_fix 59 60 61 #define MCIF_WB_COMMON_REG_LIST_DCN2_0(inst) \ 62 SRI(MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB, inst),\ 63 SRI(MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB, inst),\ 64 SRI(MCIF_WB_BUFMGR_STATUS, MCIF_WB, inst),\ 65 SRI(MCIF_WB_BUF_PITCH, MCIF_WB, inst),\ 66 SRI(MCIF_WB_BUF_1_STATUS, MCIF_WB, inst),\ 67 SRI(MCIF_WB_BUF_1_STATUS2, MCIF_WB, inst),\ 68 SRI(MCIF_WB_BUF_2_STATUS, MCIF_WB, inst),\ 69 SRI(MCIF_WB_BUF_2_STATUS2, MCIF_WB, inst),\ 70 SRI(MCIF_WB_BUF_3_STATUS, MCIF_WB, inst),\ 71 SRI(MCIF_WB_BUF_3_STATUS2, MCIF_WB, inst),\ 72 SRI(MCIF_WB_BUF_4_STATUS, MCIF_WB, inst),\ 73 SRI(MCIF_WB_BUF_4_STATUS2, MCIF_WB, inst),\ 74 SRI(MCIF_WB_ARBITRATION_CONTROL, MCIF_WB, inst),\ 75 SRI(MCIF_WB_SCLK_CHANGE, MCIF_WB, inst),\ 76 SRI(MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB, inst),\ 77 SRI(MCIF_WB_TEST_DEBUG_DATA, MCIF_WB, inst),\ 78 SRI(MCIF_WB_BUF_1_ADDR_Y, MCIF_WB, inst),\ 79 SRI(MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB, inst),\ 80 SRI(MCIF_WB_BUF_1_ADDR_C, MCIF_WB, inst),\ 81 SRI(MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB, inst),\ 82 SRI(MCIF_WB_BUF_2_ADDR_Y, MCIF_WB, inst),\ 83 SRI(MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB, inst),\ 84 SRI(MCIF_WB_BUF_2_ADDR_C, MCIF_WB, inst),\ 85 SRI(MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB, inst),\ 86 SRI(MCIF_WB_BUF_3_ADDR_Y, MCIF_WB, inst),\ 87 SRI(MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB, inst),\ 88 SRI(MCIF_WB_BUF_3_ADDR_C, MCIF_WB, inst),\ 89 SRI(MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB, inst),\ 90 SRI(MCIF_WB_BUF_4_ADDR_Y, MCIF_WB, inst),\ 91 SRI(MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB, inst),\ 92 SRI(MCIF_WB_BUF_4_ADDR_C, MCIF_WB, inst),\ 93 SRI(MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB, inst),\ 94 SRI(MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB, inst),\ 95 SRI(MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, MCIF_WB, inst),\ 96 SRI(MCIF_WB_NB_PSTATE_CONTROL, MCIF_WB, inst),\ 97 SRI(MCIF_WB_WATERMARK, MCIF_WB, inst),\ 98 SRI(MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB, inst),\ 99 SRI(MCIF_WB_WARM_UP_CNTL, MCIF_WB, inst),\ 100 SRI(MCIF_WB_SELF_REFRESH_CONTROL, MCIF_WB, inst),\ 101 SRI(MULTI_LEVEL_QOS_CTRL, MCIF_WB, inst),\ 102 SRI(MCIF_WB_SECURITY_LEVEL, MCIF_WB, inst),\ 103 SRI(MCIF_WB_BUF_LUMA_SIZE, MCIF_WB, inst),\ 104 SRI(MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB, inst),\ 105 SRI(MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB, inst),\ 106 SRI(MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB, inst),\ 107 SRI(MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB, inst),\ 108 SRI(MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB, inst),\ 109 SRI(MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB, inst),\ 110 SRI(MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB, inst),\ 111 SRI(MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB, inst),\ 112 SRI(MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB, inst),\ 113 SRI(MCIF_WB_BUF_1_RESOLUTION, MCIF_WB, inst),\ 114 SRI(MCIF_WB_BUF_2_RESOLUTION, MCIF_WB, inst),\ 115 SRI(MCIF_WB_BUF_3_RESOLUTION, MCIF_WB, inst),\ 116 SRI(MCIF_WB_BUF_4_RESOLUTION, MCIF_WB, inst),\ 117 SRI(SMU_WM_CONTROL, WBIF, inst) 118 119 #define MCIF_WB_COMMON_MASK_SH_LIST_DCN2_0(mask_sh) \ 120 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_ENABLE, mask_sh),\ 121 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_EN, mask_sh),\ 122 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_INT_ACK, mask_sh),\ 123 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_SLICE_INT_EN, mask_sh),\ 124 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN, mask_sh),\ 125 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUFMGR_SW_LOCK, mask_sh),\ 126 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_P_VMID, mask_sh),\ 127 SF(MCIF_WB0_MCIF_WB_BUFMGR_SW_CONTROL, MCIF_WB_BUF_ADDR_FENCE_EN, mask_sh),\ 128 SF(MCIF_WB0_MCIF_WB_BUFMGR_CUR_LINE_R, MCIF_WB_BUFMGR_CUR_LINE_R, mask_sh),\ 129 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_VCE_INT_STATUS, mask_sh),\ 130 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_INT_STATUS, mask_sh),\ 131 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS, mask_sh),\ 132 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_BUF, mask_sh),\ 133 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_BUFTAG, mask_sh),\ 134 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_CUR_LINE_L, mask_sh),\ 135 SF(MCIF_WB0_MCIF_WB_BUFMGR_STATUS, MCIF_WB_BUFMGR_NEXT_BUF, mask_sh),\ 136 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_LUMA_PITCH, mask_sh),\ 137 SF(MCIF_WB0_MCIF_WB_BUF_PITCH, MCIF_WB_BUF_CHROMA_PITCH, mask_sh),\ 138 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_ACTIVE, mask_sh),\ 139 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SW_LOCKED, mask_sh),\ 140 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_VCE_LOCKED, mask_sh),\ 141 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_OVERFLOW, mask_sh),\ 142 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_DISABLE, mask_sh),\ 143 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_MODE, mask_sh),\ 144 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_BUFTAG, mask_sh),\ 145 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_NXT_BUF, mask_sh),\ 146 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FIELD, mask_sh),\ 147 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_CUR_LINE_L, mask_sh),\ 148 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_LONG_LINE_ERROR, mask_sh),\ 149 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_SHORT_LINE_ERROR, mask_sh),\ 150 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS, MCIF_WB_BUF_1_FRAME_LENGTH_ERROR, mask_sh),\ 151 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_CUR_LINE_R, mask_sh),\ 152 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_NEW_CONTENT, mask_sh),\ 153 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_COLOR_DEPTH, mask_sh),\ 154 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ_BLACK_PIXEL, mask_sh),\ 155 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_TMZ, mask_sh),\ 156 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_Y_OVERRUN, mask_sh),\ 157 SF(MCIF_WB0_MCIF_WB_BUF_1_STATUS2, MCIF_WB_BUF_1_C_OVERRUN, mask_sh),\ 158 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_ACTIVE, mask_sh),\ 159 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SW_LOCKED, mask_sh),\ 160 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_VCE_LOCKED, mask_sh),\ 161 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_OVERFLOW, mask_sh),\ 162 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_DISABLE, mask_sh),\ 163 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_MODE, mask_sh),\ 164 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_BUFTAG, mask_sh),\ 165 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_NXT_BUF, mask_sh),\ 166 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FIELD, mask_sh),\ 167 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_CUR_LINE_L, mask_sh),\ 168 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_LONG_LINE_ERROR, mask_sh),\ 169 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_SHORT_LINE_ERROR, mask_sh),\ 170 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS, MCIF_WB_BUF_2_FRAME_LENGTH_ERROR, mask_sh),\ 171 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_CUR_LINE_R, mask_sh),\ 172 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_NEW_CONTENT, mask_sh),\ 173 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_COLOR_DEPTH, mask_sh),\ 174 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ_BLACK_PIXEL, mask_sh),\ 175 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_TMZ, mask_sh),\ 176 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_Y_OVERRUN, mask_sh),\ 177 SF(MCIF_WB0_MCIF_WB_BUF_2_STATUS2, MCIF_WB_BUF_2_C_OVERRUN, mask_sh),\ 178 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_ACTIVE, mask_sh),\ 179 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SW_LOCKED, mask_sh),\ 180 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_VCE_LOCKED, mask_sh),\ 181 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_OVERFLOW, mask_sh),\ 182 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_DISABLE, mask_sh),\ 183 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_MODE, mask_sh),\ 184 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_BUFTAG, mask_sh),\ 185 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_NXT_BUF, mask_sh),\ 186 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FIELD, mask_sh),\ 187 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_CUR_LINE_L, mask_sh),\ 188 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_LONG_LINE_ERROR, mask_sh),\ 189 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_SHORT_LINE_ERROR, mask_sh),\ 190 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS, MCIF_WB_BUF_3_FRAME_LENGTH_ERROR, mask_sh),\ 191 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_CUR_LINE_R, mask_sh),\ 192 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_NEW_CONTENT, mask_sh),\ 193 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_COLOR_DEPTH, mask_sh),\ 194 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ_BLACK_PIXEL, mask_sh),\ 195 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_TMZ, mask_sh),\ 196 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_Y_OVERRUN, mask_sh),\ 197 SF(MCIF_WB0_MCIF_WB_BUF_3_STATUS2, MCIF_WB_BUF_3_C_OVERRUN, mask_sh),\ 198 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_ACTIVE, mask_sh),\ 199 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SW_LOCKED, mask_sh),\ 200 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_VCE_LOCKED, mask_sh),\ 201 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_OVERFLOW, mask_sh),\ 202 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_DISABLE, mask_sh),\ 203 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_MODE, mask_sh),\ 204 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_BUFTAG, mask_sh),\ 205 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_NXT_BUF, mask_sh),\ 206 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FIELD, mask_sh),\ 207 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_CUR_LINE_L, mask_sh),\ 208 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_LONG_LINE_ERROR, mask_sh),\ 209 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_SHORT_LINE_ERROR, mask_sh),\ 210 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS, MCIF_WB_BUF_4_FRAME_LENGTH_ERROR, mask_sh),\ 211 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_CUR_LINE_R, mask_sh),\ 212 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_NEW_CONTENT, mask_sh),\ 213 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_COLOR_DEPTH, mask_sh),\ 214 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ_BLACK_PIXEL, mask_sh),\ 215 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_TMZ, mask_sh),\ 216 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_Y_OVERRUN, mask_sh),\ 217 SF(MCIF_WB0_MCIF_WB_BUF_4_STATUS2, MCIF_WB_BUF_4_C_OVERRUN, mask_sh),\ 218 SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_CLIENT_ARBITRATION_SLICE, mask_sh),\ 219 SF(MCIF_WB0_MCIF_WB_ARBITRATION_CONTROL, MCIF_WB_TIME_PER_PIXEL, mask_sh),\ 220 SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, WM_CHANGE_ACK_FORCE_ON, mask_sh),\ 221 SF(MCIF_WB0_MCIF_WB_SCLK_CHANGE, MCIF_WB_CLI_WATERMARK_MASK, mask_sh),\ 222 SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_INDEX, MCIF_WB_TEST_DEBUG_INDEX, mask_sh),\ 223 SF(MCIF_WB0_MCIF_WB_TEST_DEBUG_DATA, MCIF_WB_TEST_DEBUG_DATA, mask_sh),\ 224 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y, MCIF_WB_BUF_1_ADDR_Y, mask_sh),\ 225 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_OFFSET, MCIF_WB_BUF_1_ADDR_Y_OFFSET, mask_sh),\ 226 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C, MCIF_WB_BUF_1_ADDR_C, mask_sh),\ 227 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_OFFSET, MCIF_WB_BUF_1_ADDR_C_OFFSET, mask_sh),\ 228 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y, MCIF_WB_BUF_2_ADDR_Y, mask_sh),\ 229 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_OFFSET, MCIF_WB_BUF_2_ADDR_Y_OFFSET, mask_sh),\ 230 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C, MCIF_WB_BUF_2_ADDR_C, mask_sh),\ 231 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_OFFSET, MCIF_WB_BUF_2_ADDR_C_OFFSET, mask_sh),\ 232 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y, MCIF_WB_BUF_3_ADDR_Y, mask_sh),\ 233 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_OFFSET, MCIF_WB_BUF_3_ADDR_Y_OFFSET, mask_sh),\ 234 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C, MCIF_WB_BUF_3_ADDR_C, mask_sh),\ 235 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_OFFSET, MCIF_WB_BUF_3_ADDR_C_OFFSET, mask_sh),\ 236 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y, MCIF_WB_BUF_4_ADDR_Y, mask_sh),\ 237 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_OFFSET, MCIF_WB_BUF_4_ADDR_Y_OFFSET, mask_sh),\ 238 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C, MCIF_WB_BUF_4_ADDR_C, mask_sh),\ 239 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_OFFSET, MCIF_WB_BUF_4_ADDR_C_OFFSET, mask_sh),\ 240 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK_IGNORE, mask_sh),\ 241 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_EN, mask_sh),\ 242 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_INT_ACK, mask_sh),\ 243 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_SLICE_INT_EN, mask_sh),\ 244 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_VCE_LOCK, mask_sh),\ 245 SF(MCIF_WB0_MCIF_WB_BUFMGR_VCE_CONTROL, MCIF_WB_BUFMGR_SLICE_SIZE, mask_sh),\ 246 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_LATENCY_WATERMARK, NB_PSTATE_CHANGE_REFRESH_WATERMARK, mask_sh),\ 247 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_URGENT_DURING_REQUEST, mask_sh),\ 248 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_FORCE_ON, mask_sh),\ 249 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_ALLOW_FOR_URGENT, mask_sh),\ 250 SF(MCIF_WB0_MCIF_WB_NB_PSTATE_CONTROL, NB_PSTATE_CHANGE_WATERMARK_MASK, mask_sh),\ 251 SF(MCIF_WB0_MCIF_WB_WATERMARK, MCIF_WB_CLI_WATERMARK, mask_sh),\ 252 SF(MCIF_WB0_MCIF_WB_CLOCK_GATER_CONTROL, MCIF_WB_CLI_CLOCK_GATER_OVERRIDE, mask_sh),\ 253 SF(MCIF_WB0_MCIF_WB_WARM_UP_CNTL, MCIF_WB_PITCH_SIZE_WARMUP, mask_sh),\ 254 SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, DIS_REFRESH_UNDER_NBPREQ, mask_sh),\ 255 SF(MCIF_WB0_MCIF_WB_SELF_REFRESH_CONTROL, PERFRAME_SELF_REFRESH, mask_sh),\ 256 SF(MCIF_WB0_MULTI_LEVEL_QOS_CTRL, MAX_SCALED_TIME_TO_URGENT, mask_sh),\ 257 SF(MCIF_WB0_MCIF_WB_SECURITY_LEVEL, MCIF_WB_SECURITY_LEVEL, mask_sh),\ 258 SF(MCIF_WB0_MCIF_WB_BUF_LUMA_SIZE, MCIF_WB_BUF_LUMA_SIZE, mask_sh),\ 259 SF(MCIF_WB0_MCIF_WB_BUF_CHROMA_SIZE, MCIF_WB_BUF_CHROMA_SIZE, mask_sh),\ 260 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_Y_HIGH, MCIF_WB_BUF_1_ADDR_Y_HIGH, mask_sh),\ 261 SF(MCIF_WB0_MCIF_WB_BUF_1_ADDR_C_HIGH, MCIF_WB_BUF_1_ADDR_C_HIGH, mask_sh),\ 262 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_Y_HIGH, MCIF_WB_BUF_2_ADDR_Y_HIGH, mask_sh),\ 263 SF(MCIF_WB0_MCIF_WB_BUF_2_ADDR_C_HIGH, MCIF_WB_BUF_2_ADDR_C_HIGH, mask_sh),\ 264 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_Y_HIGH, MCIF_WB_BUF_3_ADDR_Y_HIGH, mask_sh),\ 265 SF(MCIF_WB0_MCIF_WB_BUF_3_ADDR_C_HIGH, MCIF_WB_BUF_3_ADDR_C_HIGH, mask_sh),\ 266 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_Y_HIGH, MCIF_WB_BUF_4_ADDR_Y_HIGH, mask_sh),\ 267 SF(MCIF_WB0_MCIF_WB_BUF_4_ADDR_C_HIGH, MCIF_WB_BUF_4_ADDR_C_HIGH, mask_sh),\ 268 SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_WIDTH, mask_sh),\ 269 SF(MCIF_WB0_MCIF_WB_BUF_1_RESOLUTION, MCIF_WB_BUF_1_RESOLUTION_HEIGHT, mask_sh),\ 270 SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_WIDTH, mask_sh),\ 271 SF(MCIF_WB0_MCIF_WB_BUF_2_RESOLUTION, MCIF_WB_BUF_2_RESOLUTION_HEIGHT, mask_sh),\ 272 SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_WIDTH, mask_sh),\ 273 SF(MCIF_WB0_MCIF_WB_BUF_3_RESOLUTION, MCIF_WB_BUF_3_RESOLUTION_HEIGHT, mask_sh),\ 274 SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_WIDTH, mask_sh),\ 275 SF(MCIF_WB0_MCIF_WB_BUF_4_RESOLUTION, MCIF_WB_BUF_4_RESOLUTION_HEIGHT, mask_sh),\ 276 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_SEL, mask_sh),\ 277 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_REQ, mask_sh),\ 278 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_DIS, mask_sh),\ 279 SF(WBIF0_SMU_WM_CONTROL, MCIF_WB0_WM_CHG_ACK_INT_STATUS, mask_sh) 280 281 #define MCIF_WB_REG_FIELD_LIST_DCN2_0(type) \ 282 type MCIF_WB_BUFMGR_ENABLE;\ 283 type MCIF_WB_BUFMGR_SW_INT_EN;\ 284 type MCIF_WB_BUFMGR_SW_INT_ACK;\ 285 type MCIF_WB_BUFMGR_SW_SLICE_INT_EN;\ 286 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_EN;\ 287 type MCIF_WB_BUFMGR_SW_LOCK;\ 288 type MCIF_WB_P_VMID;\ 289 type MCIF_WB_BUF_ADDR_FENCE_EN;\ 290 type MCIF_WB_BUFMGR_CUR_LINE_R;\ 291 type MCIF_WB_BUFMGR_VCE_INT_STATUS;\ 292 type MCIF_WB_BUFMGR_SW_INT_STATUS;\ 293 type MCIF_WB_BUFMGR_SW_OVERRUN_INT_STATUS;\ 294 type MCIF_WB_BUFMGR_CUR_BUF;\ 295 type MCIF_WB_BUFMGR_BUFTAG;\ 296 type MCIF_WB_BUFMGR_CUR_LINE_L;\ 297 type MCIF_WB_BUFMGR_NEXT_BUF;\ 298 type MCIF_WB_BUF_LUMA_PITCH;\ 299 type MCIF_WB_BUF_CHROMA_PITCH;\ 300 type MCIF_WB_BUF_1_ACTIVE;\ 301 type MCIF_WB_BUF_1_SW_LOCKED;\ 302 type MCIF_WB_BUF_1_VCE_LOCKED;\ 303 type MCIF_WB_BUF_1_OVERFLOW;\ 304 type MCIF_WB_BUF_1_DISABLE;\ 305 type MCIF_WB_BUF_1_MODE;\ 306 type MCIF_WB_BUF_1_BUFTAG;\ 307 type MCIF_WB_BUF_1_NXT_BUF;\ 308 type MCIF_WB_BUF_1_FIELD;\ 309 type MCIF_WB_BUF_1_CUR_LINE_L;\ 310 type MCIF_WB_BUF_1_LONG_LINE_ERROR;\ 311 type MCIF_WB_BUF_1_SHORT_LINE_ERROR;\ 312 type MCIF_WB_BUF_1_FRAME_LENGTH_ERROR;\ 313 type MCIF_WB_BUF_1_CUR_LINE_R;\ 314 type MCIF_WB_BUF_1_NEW_CONTENT;\ 315 type MCIF_WB_BUF_1_COLOR_DEPTH;\ 316 type MCIF_WB_BUF_1_TMZ_BLACK_PIXEL;\ 317 type MCIF_WB_BUF_1_TMZ;\ 318 type MCIF_WB_BUF_1_Y_OVERRUN;\ 319 type MCIF_WB_BUF_1_C_OVERRUN;\ 320 type MCIF_WB_BUF_2_ACTIVE;\ 321 type MCIF_WB_BUF_2_SW_LOCKED;\ 322 type MCIF_WB_BUF_2_VCE_LOCKED;\ 323 type MCIF_WB_BUF_2_OVERFLOW;\ 324 type MCIF_WB_BUF_2_DISABLE;\ 325 type MCIF_WB_BUF_2_MODE;\ 326 type MCIF_WB_BUF_2_BUFTAG;\ 327 type MCIF_WB_BUF_2_NXT_BUF;\ 328 type MCIF_WB_BUF_2_FIELD;\ 329 type MCIF_WB_BUF_2_CUR_LINE_L;\ 330 type MCIF_WB_BUF_2_LONG_LINE_ERROR;\ 331 type MCIF_WB_BUF_2_SHORT_LINE_ERROR;\ 332 type MCIF_WB_BUF_2_FRAME_LENGTH_ERROR;\ 333 type MCIF_WB_BUF_2_CUR_LINE_R;\ 334 type MCIF_WB_BUF_2_NEW_CONTENT;\ 335 type MCIF_WB_BUF_2_COLOR_DEPTH;\ 336 type MCIF_WB_BUF_2_TMZ_BLACK_PIXEL;\ 337 type MCIF_WB_BUF_2_TMZ;\ 338 type MCIF_WB_BUF_2_Y_OVERRUN;\ 339 type MCIF_WB_BUF_2_C_OVERRUN;\ 340 type MCIF_WB_BUF_3_ACTIVE;\ 341 type MCIF_WB_BUF_3_SW_LOCKED;\ 342 type MCIF_WB_BUF_3_VCE_LOCKED;\ 343 type MCIF_WB_BUF_3_OVERFLOW;\ 344 type MCIF_WB_BUF_3_DISABLE;\ 345 type MCIF_WB_BUF_3_MODE;\ 346 type MCIF_WB_BUF_3_BUFTAG;\ 347 type MCIF_WB_BUF_3_NXT_BUF;\ 348 type MCIF_WB_BUF_3_FIELD;\ 349 type MCIF_WB_BUF_3_CUR_LINE_L;\ 350 type MCIF_WB_BUF_3_LONG_LINE_ERROR;\ 351 type MCIF_WB_BUF_3_SHORT_LINE_ERROR;\ 352 type MCIF_WB_BUF_3_FRAME_LENGTH_ERROR;\ 353 type MCIF_WB_BUF_3_CUR_LINE_R;\ 354 type MCIF_WB_BUF_3_NEW_CONTENT;\ 355 type MCIF_WB_BUF_3_COLOR_DEPTH;\ 356 type MCIF_WB_BUF_3_TMZ_BLACK_PIXEL;\ 357 type MCIF_WB_BUF_3_TMZ;\ 358 type MCIF_WB_BUF_3_Y_OVERRUN;\ 359 type MCIF_WB_BUF_3_C_OVERRUN;\ 360 type MCIF_WB_BUF_4_ACTIVE;\ 361 type MCIF_WB_BUF_4_SW_LOCKED;\ 362 type MCIF_WB_BUF_4_VCE_LOCKED;\ 363 type MCIF_WB_BUF_4_OVERFLOW;\ 364 type MCIF_WB_BUF_4_DISABLE;\ 365 type MCIF_WB_BUF_4_MODE;\ 366 type MCIF_WB_BUF_4_BUFTAG;\ 367 type MCIF_WB_BUF_4_NXT_BUF;\ 368 type MCIF_WB_BUF_4_FIELD;\ 369 type MCIF_WB_BUF_4_CUR_LINE_L;\ 370 type MCIF_WB_BUF_4_LONG_LINE_ERROR;\ 371 type MCIF_WB_BUF_4_SHORT_LINE_ERROR;\ 372 type MCIF_WB_BUF_4_FRAME_LENGTH_ERROR;\ 373 type MCIF_WB_BUF_4_CUR_LINE_R;\ 374 type MCIF_WB_BUF_4_NEW_CONTENT;\ 375 type MCIF_WB_BUF_4_COLOR_DEPTH;\ 376 type MCIF_WB_BUF_4_TMZ_BLACK_PIXEL;\ 377 type MCIF_WB_BUF_4_TMZ;\ 378 type MCIF_WB_BUF_4_Y_OVERRUN;\ 379 type MCIF_WB_BUF_4_C_OVERRUN;\ 380 type MCIF_WB_CLIENT_ARBITRATION_SLICE;\ 381 type MCIF_WB_TIME_PER_PIXEL;\ 382 type WM_CHANGE_ACK_FORCE_ON;\ 383 type MCIF_WB_CLI_WATERMARK_MASK;\ 384 type MCIF_WB_TEST_DEBUG_INDEX;\ 385 type MCIF_WB_TEST_DEBUG_DATA;\ 386 type MCIF_WB_BUF_1_ADDR_Y;\ 387 type MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ 388 type MCIF_WB_BUF_1_ADDR_C;\ 389 type MCIF_WB_BUF_1_ADDR_C_OFFSET;\ 390 type MCIF_WB_BUF_2_ADDR_Y;\ 391 type MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ 392 type MCIF_WB_BUF_2_ADDR_C;\ 393 type MCIF_WB_BUF_2_ADDR_C_OFFSET;\ 394 type MCIF_WB_BUF_3_ADDR_Y;\ 395 type MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ 396 type MCIF_WB_BUF_3_ADDR_C;\ 397 type MCIF_WB_BUF_3_ADDR_C_OFFSET;\ 398 type MCIF_WB_BUF_4_ADDR_Y;\ 399 type MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ 400 type MCIF_WB_BUF_4_ADDR_C;\ 401 type MCIF_WB_BUF_4_ADDR_C_OFFSET;\ 402 type MCIF_WB_BUFMGR_VCE_LOCK_IGNORE;\ 403 type MCIF_WB_BUFMGR_VCE_INT_EN;\ 404 type MCIF_WB_BUFMGR_VCE_INT_ACK;\ 405 type MCIF_WB_BUFMGR_VCE_SLICE_INT_EN;\ 406 type MCIF_WB_BUFMGR_VCE_LOCK;\ 407 type MCIF_WB_BUFMGR_SLICE_SIZE;\ 408 type NB_PSTATE_CHANGE_REFRESH_WATERMARK;\ 409 type NB_PSTATE_CHANGE_URGENT_DURING_REQUEST;\ 410 type NB_PSTATE_CHANGE_FORCE_ON;\ 411 type NB_PSTATE_ALLOW_FOR_URGENT;\ 412 type NB_PSTATE_CHANGE_WATERMARK_MASK;\ 413 type MCIF_WB_CLI_WATERMARK;\ 414 type MCIF_WB_CLI_CLOCK_GATER_OVERRIDE;\ 415 type MCIF_WB_PITCH_SIZE_WARMUP;\ 416 type DIS_REFRESH_UNDER_NBPREQ;\ 417 type PERFRAME_SELF_REFRESH;\ 418 type MAX_SCALED_TIME_TO_URGENT;\ 419 type MCIF_WB_SECURITY_LEVEL;\ 420 type MCIF_WB_BUF_LUMA_SIZE;\ 421 type MCIF_WB_BUF_CHROMA_SIZE;\ 422 type MCIF_WB_BUF_1_ADDR_Y_HIGH;\ 423 type MCIF_WB_BUF_1_ADDR_C_HIGH;\ 424 type MCIF_WB_BUF_2_ADDR_Y_HIGH;\ 425 type MCIF_WB_BUF_2_ADDR_C_HIGH;\ 426 type MCIF_WB_BUF_3_ADDR_Y_HIGH;\ 427 type MCIF_WB_BUF_3_ADDR_C_HIGH;\ 428 type MCIF_WB_BUF_4_ADDR_Y_HIGH;\ 429 type MCIF_WB_BUF_4_ADDR_C_HIGH;\ 430 type MCIF_WB_BUF_1_RESOLUTION_WIDTH;\ 431 type MCIF_WB_BUF_1_RESOLUTION_HEIGHT;\ 432 type MCIF_WB_BUF_2_RESOLUTION_WIDTH;\ 433 type MCIF_WB_BUF_2_RESOLUTION_HEIGHT;\ 434 type MCIF_WB_BUF_3_RESOLUTION_WIDTH;\ 435 type MCIF_WB_BUF_3_RESOLUTION_HEIGHT;\ 436 type MCIF_WB_BUF_4_RESOLUTION_WIDTH;\ 437 type MCIF_WB_BUF_4_RESOLUTION_HEIGHT;\ 438 type MCIF_WB0_WM_CHG_SEL;\ 439 type MCIF_WB0_WM_CHG_REQ;\ 440 type MCIF_WB0_WM_CHG_ACK_INT_DIS;\ 441 type MCIF_WB0_WM_CHG_ACK_INT_STATUS 442 443 #define MCIF_WB_REG_VARIABLE_LIST_DCN2_0 \ 444 uint32_t MCIF_WB_BUFMGR_SW_CONTROL;\ 445 uint32_t MCIF_WB_BUFMGR_CUR_LINE_R;\ 446 uint32_t MCIF_WB_BUFMGR_STATUS;\ 447 uint32_t MCIF_WB_BUF_PITCH;\ 448 uint32_t MCIF_WB_BUF_1_STATUS;\ 449 uint32_t MCIF_WB_BUF_1_STATUS2;\ 450 uint32_t MCIF_WB_BUF_2_STATUS;\ 451 uint32_t MCIF_WB_BUF_2_STATUS2;\ 452 uint32_t MCIF_WB_BUF_3_STATUS;\ 453 uint32_t MCIF_WB_BUF_3_STATUS2;\ 454 uint32_t MCIF_WB_BUF_4_STATUS;\ 455 uint32_t MCIF_WB_BUF_4_STATUS2;\ 456 uint32_t MCIF_WB_ARBITRATION_CONTROL;\ 457 uint32_t MCIF_WB_SCLK_CHANGE;\ 458 uint32_t MCIF_WB_TEST_DEBUG_INDEX;\ 459 uint32_t MCIF_WB_TEST_DEBUG_DATA;\ 460 uint32_t MCIF_WB_BUF_1_ADDR_Y;\ 461 uint32_t MCIF_WB_BUF_1_ADDR_Y_OFFSET;\ 462 uint32_t MCIF_WB_BUF_1_ADDR_C;\ 463 uint32_t MCIF_WB_BUF_1_ADDR_C_OFFSET;\ 464 uint32_t MCIF_WB_BUF_2_ADDR_Y;\ 465 uint32_t MCIF_WB_BUF_2_ADDR_Y_OFFSET;\ 466 uint32_t MCIF_WB_BUF_2_ADDR_C;\ 467 uint32_t MCIF_WB_BUF_2_ADDR_C_OFFSET;\ 468 uint32_t MCIF_WB_BUF_3_ADDR_Y;\ 469 uint32_t MCIF_WB_BUF_3_ADDR_Y_OFFSET;\ 470 uint32_t MCIF_WB_BUF_3_ADDR_C;\ 471 uint32_t MCIF_WB_BUF_3_ADDR_C_OFFSET;\ 472 uint32_t MCIF_WB_BUF_4_ADDR_Y;\ 473 uint32_t MCIF_WB_BUF_4_ADDR_Y_OFFSET;\ 474 uint32_t MCIF_WB_BUF_4_ADDR_C;\ 475 uint32_t MCIF_WB_BUF_4_ADDR_C_OFFSET;\ 476 uint32_t MCIF_WB_BUFMGR_VCE_CONTROL;\ 477 uint32_t MCIF_WB_NB_PSTATE_LATENCY_WATERMARK;\ 478 uint32_t MCIF_WB_NB_PSTATE_CONTROL;\ 479 uint32_t MCIF_WB_WATERMARK;\ 480 uint32_t MCIF_WB_CLOCK_GATER_CONTROL;\ 481 uint32_t MCIF_WB_WARM_UP_CNTL;\ 482 uint32_t MCIF_WB_SELF_REFRESH_CONTROL;\ 483 uint32_t MULTI_LEVEL_QOS_CTRL;\ 484 uint32_t MCIF_WB_SECURITY_LEVEL;\ 485 uint32_t MCIF_WB_BUF_LUMA_SIZE;\ 486 uint32_t MCIF_WB_BUF_CHROMA_SIZE;\ 487 uint32_t MCIF_WB_BUF_1_ADDR_Y_HIGH;\ 488 uint32_t MCIF_WB_BUF_1_ADDR_C_HIGH;\ 489 uint32_t MCIF_WB_BUF_2_ADDR_Y_HIGH;\ 490 uint32_t MCIF_WB_BUF_2_ADDR_C_HIGH;\ 491 uint32_t MCIF_WB_BUF_3_ADDR_Y_HIGH;\ 492 uint32_t MCIF_WB_BUF_3_ADDR_C_HIGH;\ 493 uint32_t MCIF_WB_BUF_4_ADDR_Y_HIGH;\ 494 uint32_t MCIF_WB_BUF_4_ADDR_C_HIGH;\ 495 uint32_t MCIF_WB_BUF_1_RESOLUTION;\ 496 uint32_t MCIF_WB_BUF_2_RESOLUTION;\ 497 uint32_t MCIF_WB_BUF_3_RESOLUTION;\ 498 uint32_t MCIF_WB_BUF_4_RESOLUTION;\ 499 uint32_t SMU_WM_CONTROL 500 501 struct dcn20_mmhubbub_registers { 502 MCIF_WB_REG_VARIABLE_LIST_DCN2_0; 503 }; 504 505 506 struct dcn20_mmhubbub_mask { 507 MCIF_WB_REG_FIELD_LIST_DCN2_0(uint32_t); 508 }; 509 510 struct dcn20_mmhubbub_shift { 511 MCIF_WB_REG_FIELD_LIST_DCN2_0(uint8_t); 512 }; 513 514 struct dcn20_mmhubbub { 515 struct mcif_wb base; 516 const struct dcn20_mmhubbub_registers *mcif_wb_regs; 517 const struct dcn20_mmhubbub_shift *mcif_wb_shift; 518 const struct dcn20_mmhubbub_mask *mcif_wb_mask; 519 }; 520 521 void mmhubbub2_config_mcif_irq(struct mcif_wb *mcif_wb, 522 struct mcif_irq_params *params); 523 524 void mmhubbub2_enable_mcif(struct mcif_wb *mcif_wb); 525 526 void mmhubbub2_disable_mcif(struct mcif_wb *mcif_wb); 527 528 void mcifwb2_dump_frame(struct mcif_wb *mcif_wb, 529 struct mcif_buf_params *mcif_params, 530 enum dwb_scaler_mode out_format, 531 unsigned int dest_width, 532 unsigned int dest_height, 533 struct mcif_wb_frame_dump_info *dump_info, 534 unsigned char *luma_buffer, 535 unsigned char *chroma_buffer, 536 unsigned char *dest_luma_buffer, 537 unsigned char *dest_chroma_buffer); 538 539 void dcn20_mmhubbub_construct(struct dcn20_mmhubbub *mcif_wb20, 540 struct dc_context *ctx, 541 const struct dcn20_mmhubbub_registers *mcif_wb_regs, 542 const struct dcn20_mmhubbub_shift *mcif_wb_shift, 543 const struct dcn20_mmhubbub_mask *mcif_wb_mask, 544 int inst); 545 546 #endif 547
Indexes created Sun Sep 28 16:09:52 GMT 2025