1 /* $NetBSD: tx3912videoreg.h,v 1.6 2008/04/28 20:23:21 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2000 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * TOSHIBA TMPR3912/05, Philips PR31700 Video module register 33 */ 34 #define TX3912_VIDEOCTRL1_REG 0x28 35 #define TX3912_VIDEOCTRL2_REG 0x2c 36 #define TX3912_VIDEOCTRL3_REG 0x30 37 #define TX3912_VIDEOCTRL4_REG 0x34 38 #define TX3912_VIDEOCTRL5_REG 0x38 39 #define TX3912_VIDEOCTRL6_REG 0x3c 40 #define TX3912_VIDEOCTRL7_REG 0x40 41 #define TX3912_VIDEOCTRL8_REG 0x44 42 #define TX3912_VIDEOCTRL9_REG 0x48 43 #define TX3912_VIDEOCTRL10_REG 0x4c 44 #define TX3912_VIDEOCTRL11_REG 0x50 45 #define TX3912_VIDEOCTRL12_REG 0x54 46 #define TX3912_VIDEOCTRL13_REG 0x58 47 #define TX3912_VIDEOCTRL14_REG 0x5c 48 49 #define TX3912_FRAMEBUFFER_ALIGNMENT 16 50 #define TX3912_FRAMEBUFFER_BOUNDARY 0x100000 51 #define TX3912_FRAMEBUFFER_MAX (2048 * 1024 * 8) 52 53 /* 54 * Video Control 1 Register 55 */ 56 /* R */ 57 #define TX3912_VIDEOCTRL1_LINECNT_SHIFT 22 58 #define TX3912_VIDEOCTRL1_LINECNT_MASK 0x3ff 59 #define TX3912_VIDEOCTRL1_LINECNT(cr) \ 60 (((cr) >> TX3912_VIDEOCTRL1_LINECNT_SHIFT) & \ 61 TX3912_VIDEOCTRL1_LINECNT_MASK) 62 /* R/W */ 63 #define TX3912_VIDEOCTRL1_LOADDLY 0x00200000 64 /* R/W */ 65 /* 66 * CP Rate = 36.864MHz / (BAUDVAL * 2 + 2) 67 */ 68 #define TX3912_VIDEOCTRL1_BAUDVAL_SHIFT 16 69 #define TX3912_VIDEOCTRL1_BAUDVAL_MASK 0x1f 70 #define TX3912_VIDEOCTRL1_BAUDVAL(cr) \ 71 (((cr) >> TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 72 TX3912_VIDEOCTRL1_BAUDVAL_MASK) 73 #define TX3912_VIDEOCTRL1_BAUDVAL_SET(cr, val) \ 74 ((cr) | (((val) << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT) & \ 75 (TX3912_VIDEOCTRL1_BAUDVAL_MASK << TX3912_VIDEOCTRL1_BAUDVAL_SHIFT))) 76 77 /* R/W */ 78 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT 9 79 #define TX3912_VIDEOCTRL1_VIDDONEVAL_MASK 0x7f 80 #define TX3912_VIDEOCTRL1_VIDDONEVAL(cr) \ 81 (((cr) >> TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 82 TX3912_VIDEOCTRL1_VIDDONEVAL_MASK) 83 #define TX3912_VIDEOCTRL1_VIDDONEVAL_SET(cr, val) \ 84 ((cr) | (((val) << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT) & \ 85 (TX3912_VIDEOCTRL1_VIDDONEVAL_MASK << TX3912_VIDEOCTRL1_VIDDONEVAL_SHIFT))) 86 /* R/W */ 87 #define TX3912_VIDEOCTRL1_ENFREEZEFRAME 0x00000100 88 /* R/W */ 89 #define TX3912_VIDEOCTRL1_BITSEL_SHIFT 6 90 #define TX3912_VIDEOCTRL1_BITSEL_MASK 0x3 91 #define TX3912_VIDEOCTRL1_BITSEL(cr) \ 92 (((cr) >> TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 93 TX3912_VIDEOCTRL1_BITSEL_MASK) 94 #define TX3912_VIDEOCTRL1_BITSEL_CLR(cr) \ 95 ((cr) &= ~(TX3912_VIDEOCTRL1_BITSEL_MASK << \ 96 TX3912_VIDEOCTRL1_BITSEL_SHIFT)) 97 #define TX3912_VIDEOCTRL1_BITSEL_SET(cr, val) \ 98 ((cr) | (((val) << TX3912_VIDEOCTRL1_BITSEL_SHIFT) & \ 99 (TX3912_VIDEOCTRL1_BITSEL_MASK << TX3912_VIDEOCTRL1_BITSEL_SHIFT))) 100 #define TX3912_VIDEOCTRL1_BITSEL_8BITCOLOR 0x3 101 #define TX3912_VIDEOCTRL1_BITSEL_4BITGREYSCALE 0x2 102 #define TX3912_VIDEOCTRL1_BITSEL_2BITGREYSCALE 0x1 103 #define TX3912_VIDEOCTRL1_BITSEL_MONOCHROME 0x0 104 /* R/W */ 105 #define TX3912_VIDEOCTRL1_DISPSPLIT 0x00000020 106 #define TX3912_VIDEOCTRL1_DISP8 0x00000010 107 #define TX3912_VIDEOCTRL1_DFMODE 0x00000008 108 #define TX3912_VIDEOCTRL1_INVVID 0x00000004 109 #define TX3912_VIDEOCTRL1_DISPON 0x00000002 110 #define TX3912_VIDEOCTRL1_ENVID 0x00000001 111 112 /* 113 * Video Control 2 Register 114 */ 115 /* W */ 116 #define TX3912_VIDEOCTRL2_VIDRATE_SHIFT 22 117 #define TX3912_VIDEOCTRL2_VIDRATE_MASK 0x3ff 118 #define TX3912_VIDEOCTRL2_VIDRATE(cr) \ 119 (((cr) >> TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 120 TX3912_VIDEOCTRL2_VIDRATE_MASK) 121 #define TX3912_VIDEOCTRL2_VIDRATE_SET(cr, val) \ 122 ((cr) | (((val) << TX3912_VIDEOCTRL2_VIDRATE_SHIFT) & \ 123 (TX3912_VIDEOCTRL2_VIDRATE_MASK << TX3912_VIDEOCTRL2_VIDRATE_SHIFT))) 124 125 /* W */ 126 /* 127 * HORZVAL = (HorzSize4 - 1) for 4bit split or non-split LCD 128 * HORZVAL = (HorzSize8 - 1) for 8bit non-split LCD 129 */ 130 #define TX3912_VIDEOCTRL2_HORZVAL_SHIFT 12 131 #define TX3912_VIDEOCTRL2_HORZVAL_MASK 0x1ff 132 #define TX3912_VIDEOCTRL2_HORZVAL(cr) \ 133 (((cr) >> TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 134 TX3912_VIDEOCTRL2_HORZVAL_MASK) 135 #define TX3912_VIDEOCTRL2_HORZVAL_SET(cr, val) \ 136 ((cr) | (((val) << TX3912_VIDEOCTRL2_HORZVAL_SHIFT) & \ 137 (TX3912_VIDEOCTRL2_HORZVAL_MASK << TX3912_VIDEOCTRL2_HORZVAL_SHIFT))) 138 139 /* W */ 140 /* 141 * LINEVAL = (# of Lines - 1) for a non-split LCD 142 * LINEVAL = (# of Lins2 - 1) for a split LCD 143 */ 144 #define TX3912_VIDEOCTRL2_LINEVAL_SHIFT 0 145 #define TX3912_VIDEOCTRL2_LINEVAL_MASK 0x3ff 146 #define TX3912_VIDEOCTRL2_LINEVAL(cr) \ 147 (((cr) >> TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 148 TX3912_VIDEOCTRL2_LINEVAL_MASK) 149 #define TX3912_VIDEOCTRL2_LINEVAL_SET(cr, val) \ 150 ((cr) | (((val) << TX3912_VIDEOCTRL2_LINEVAL_SHIFT) & \ 151 (TX3912_VIDEOCTRL2_LINEVAL_MASK << TX3912_VIDEOCTRL2_LINEVAL_SHIFT))) 152 153 /* 154 * Video Control 3 Register 155 */ 156 /* W */ 157 #define TX3912_VIDEOCTRL3_VIDBANK_SHIFT 20 158 #define TX3912_VIDEOCTRL3_VIDBANK_MASK 0xfff 159 #define TX3912_VIDEOCTRL3_VIDBANK(cr) \ 160 (((cr) >> TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 161 TX3912_VIDEOCTRL3_VIDBANK_MASK) 162 #define TX3912_VIDEOCTRL3_VIDBANK_SET(cr, val) \ 163 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBANK_SHIFT) & \ 164 (TX3912_VIDEOCTRL3_VIDBANK_MASK << TX3912_VIDEOCTRL3_VIDBANK_SHIFT))) 165 166 /* W */ 167 #define TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT 4 168 #define TX3912_VIDEOCTRL3_VIDBASEHI_MASK 0xffff 169 #define TX3912_VIDEOCTRL3_VIDBASEHI(cr) \ 170 (((cr) >> TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 171 TX3912_VIDEOCTRL3_VIDBASEHI_MASK) 172 #define TX3912_VIDEOCTRL3_VIDBASEHI_SET(cr, val) \ 173 ((cr) | (((val) << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT) & \ 174 (TX3912_VIDEOCTRL3_VIDBASEHI_MASK << TX3912_VIDEOCTRL3_VIDBASEHI_SHIFT))) 175 176 177 /* 178 * Video Control 4 Register 179 */ 180 /* W */ 181 /* 182 * DF Rate = LineRate / (DFVAL + 1) 183 */ 184 #define TX3912_VIDEOCTRL4_DFVAL_SHIFT 24 185 #define TX3912_VIDEOCTRL4_DFVAL_MASK 0xff 186 #define TX3912_VIDEOCTRL4_DFVAL(cr) \ 187 (((cr) >> TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 188 TX3912_VIDEOCTRL4_DFVAL_MASK) 189 #define TX3912_VIDEOCTRL4_DFVAL_SET(cr, val) \ 190 ((cr) | (((val) << TX3912_VIDEOCTRL4_DFVAL_SHIFT) & \ 191 (TX3912_VIDEOCTRL4_DFVAL_MASK << TX3912_VIDEOCTRL4_DFVAL_SHIFT))) 192 193 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT 20 194 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK 0xf 195 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL(cr) \ 196 (((cr) >> TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 197 TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK) 198 #define TX3912_VIDEOCTRL4_FRAMEMASKVAL_SET(cr, val) \ 199 ((cr) | (((val) << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT) & \ 200 (TX3912_VIDEOCTRL4_FRAMEMASKVAL_MASK << TX3912_VIDEOCTRL4_FRAMEMASKVAL_SHIFT))) 201 202 #define TX3912_VIDEOCTRL4_VIDBASELO_SHIFT 4 203 #define TX3912_VIDEOCTRL4_VIDBASELO_MASK 0xffff 204 #define TX3912_VIDEOCTRL4_VIDBASELO(cr) \ 205 (((cr) >> TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 206 TX3912_VIDEOCTRL4_VIDBASELO_MASK) 207 #define TX3912_VIDEOCTRL4_VIDBASELO_SET(cr, val) \ 208 ((cr) | (((val) << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT) & \ 209 (TX3912_VIDEOCTRL4_VIDBASELO_MASK << TX3912_VIDEOCTRL4_VIDBASELO_SHIFT))) 210 211 /* 212 * Video Control 5 Register 213 */ 214 /* W */ 215 /* 216 * TX3912_VIDEOCTRL5_REDSEL (31:0) 217 */ 218 219 /* 220 * Video Control 6 Register 221 */ 222 /* W */ 223 /* 224 * TX3912_VIDEOCTRL6_GREENSEL (31:0) 225 */ 226 227 /* 228 * Video Control 7 Register 229 */ 230 /* W */ 231 /* 232 * TX3912_VIDEOCTRL6_BLUESEL (31:0) 233 */ 234 235 /* 236 * Video Control 8 Register 237 */ 238 /* W */ 239 /* 240 * 2_3 means `2 out of 3' 241 */ 242 #define TX3912_VIDEOCTRL8_PAT2_3_SHIFT 0 243 #define TX3912_VIDEOCTRL8_PAT2_3_MASK 0xfff 244 #define TX3912_VIDEOCTRL8_PAT2_3(cr) \ 245 (((cr) >> TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 246 TX3912_VIDEOCTRL8_PAT2_3_MASK) 247 #define TX3912_VIDEOCTRL8_PAT2_3_SET(cr, val) \ 248 ((cr) | (((val) << TX3912_VIDEOCTRL8_PAT2_3_SHIFT) & \ 249 (TX3912_VIDEOCTRL8_PAT2_3_MASK << TX3912_VIDEOCTRL8_PAT2_3_SHIFT))) 250 251 /* 252 * Video Control 9 Register 253 */ 254 /* W */ 255 #define TX3912_VIDEOCTRL9_PAT3_4_SHIFT 16 256 #define TX3912_VIDEOCTRL9_PAT3_4_MASK 0xffff 257 #define TX3912_VIDEOCTRL9_PAT3_4(cr) \ 258 (((cr) >> TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 259 TX3912_VIDEOCTRL9_PAT3_4_MASK) 260 #define TX3912_VIDEOCTRL9_PAT3_4_SET(cr, val) \ 261 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT3_4_SHIFT) & \ 262 (TX3912_VIDEOCTRL9_PAT3_4_MASK << TX3912_VIDEOCTRL9_PAT3_4_SHIFT))) 263 /* W */ 264 #define TX3912_VIDEOCTRL9_PAT2_4_SHIFT 0 265 #define TX3912_VIDEOCTRL9_PAT2_4_MASK 0xffff 266 #define TX3912_VIDEOCTRL9_PAT2_4(cr) \ 267 (((cr) >> TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 268 TX3912_VIDEOCTRL9_PAT2_4_MASK) 269 #define TX3912_VIDEOCTRL9_PAT2_4_SET(cr, val) \ 270 ((cr) | (((val) << TX3912_VIDEOCTRL9_PAT2_4_SHIFT) & \ 271 (TX3912_VIDEOCTRL9_PAT2_4_MASK << TX3912_VIDEOCTRL9_PAT2_4_SHIFT))) 272 273 /* 274 * Video Control 10 Register 275 */ 276 /* W */ 277 #define TX3912_VIDEOCTRL10_PAT4_5_SHIFT 0 278 #define TX3912_VIDEOCTRL10_PAT4_5_MASK 0xfffff 279 #define TX3912_VIDEOCTRL10_PAT4_5(cr) \ 280 (((cr) >> TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 281 TX3912_VIDEOCTRL10_PAT4_5_MASK) 282 #define TX3912_VIDEOCTRL10_PAT4_5_SET(cr, val) \ 283 ((cr) | (((val) << TX3912_VIDEOCTRL10_PAT4_5_SHIFT) & \ 284 (TX3912_VIDEOCTRL10_PAT4_5_MASK << TX3912_VIDEOCTRL10_PAT4_5_SHIFT))) 285 286 /* 287 * Video Control 11 Register 288 */ 289 /* W */ 290 #define TX3912_VIDEOCTRL11_PAT3_5_SHIFT 0 291 #define TX3912_VIDEOCTRL11_PAT3_5_MASK 0xfffff 292 #define TX3912_VIDEOCTRL11_PAT3_5(cr) \ 293 (((cr) >> TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 294 TX3912_VIDEOCTRL11_PAT3_5_MASK) 295 #define TX3912_VIDEOCTRL11_PAT3_5_SET(cr, val) \ 296 ((cr) | (((val) << TX3912_VIDEOCTRL11_PAT3_5_SHIFT) & \ 297 (TX3912_VIDEOCTRL11_PAT3_5_MASK << TX3912_VIDEOCTRL11_PAT3_5_SHIFT))) 298 299 /* 300 * Video Control 12 Register 301 */ 302 /* W */ 303 #define TX3912_VIDEOCTRL12_PAT6_7_SHIFT 0 304 #define TX3912_VIDEOCTRL12_PAT6_7_MASK 0xfffffff 305 #define TX3912_VIDEOCTRL12_PAT6_7(cr) \ 306 (((cr) >> TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 307 TX3912_VIDEOCTRL12_PAT6_7_MASK) 308 #define TX3912_VIDEOCTRL12_PAT6_7_SET(cr, val) \ 309 ((cr) | (((val) << TX3912_VIDEOCTRL12_PAT6_7_SHIFT) & \ 310 (TX3912_VIDEOCTRL12_PAT6_7_MASK << TX3912_VIDEOCTRL12_PAT6_7_SHIFT))) 311 312 /* 313 * Video Control 13 Register 314 */ 315 /* W */ 316 #define TX3912_VIDEOCTRL13_PAT5_7_SHIFT 0 317 #define TX3912_VIDEOCTRL13_PAT5_7_MASK 0xfffffff 318 #define TX3912_VIDEOCTRL13_PAT5_7(cr) \ 319 (((cr) >> TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 320 TX3912_VIDEOCTRL13_PAT5_7_MASK) 321 #define TX3912_VIDEOCTRL13_PAT5_7_SET(cr, val) \ 322 ((cr) | (((val) << TX3912_VIDEOCTRL13_PAT5_7_SHIFT) & \ 323 (TX3912_VIDEOCTRL13_PAT5_7_MASK << TX3912_VIDEOCTRL13_PAT5_7_SHIFT))) 324 325 /* 326 * Video Control 14 Register 327 */ 328 /* W */ 329 #define TX3912_VIDEOCTRL14_PAT4_7_SHIFT 0 330 #define TX3912_VIDEOCTRL14_PAT4_7_MASK 0xfffffff 331 #define TX3912_VIDEOCTRL14_PAT4_7(cr) \ 332 (((cr) >> TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 333 TX3912_VIDEOCTRL14_PAT4_7_MASK) 334 #define TX3912_VIDEOCTRL14_PAT4_7_SET(cr, val) \ 335 ((cr) | (((val) << TX3912_VIDEOCTRL14_PAT4_7_SHIFT) & \ 336 (TX3912_VIDEOCTRL14_PAT4_7_MASK << TX3912_VIDEOCTRL14_PAT4_7_SHIFT))) 337 338 /* 339 * Default dither pattern 340 */ 341 #define P0000 0x0 342 #define P0001 0x1 343 #define P0010 0x2 344 #define P0011 0x3 345 #define P0100 0x4 346 #define P0101 0x5 347 #define P0110 0x6 348 #define P0111 0x7 349 #define P1000 0x8 350 #define P1001 0x9 351 #define P1010 0xa 352 #define P1011 0xb 353 #define P1100 0xc 354 #define P1101 0xd 355 #define P1110 0xe 356 #define P1111 0xf 357 358 #define DITHER_PATTERN(p0, p1, p2, p3, p4, p5, p6) \ 359 (((p0) << 24) | ((p1) << 20) | ((p2) << 16) | ((p3) << 12) | \ 360 ((p4) << 8) | ((p5) << 4) || (p6)) 361 362 #define TX3912_VIDEOCTRL8_PAT2_3_DEFAULT \ 363 DITHER_PATTERN(0, 0, 0, 0, P0111, P1101, P1010) 364 #define TX3912_VIDEOCTRL9_PAT3_4_DEFAULT \ 365 DITHER_PATTERN(0, 0, 0, P0111, P1101, P1011, P1110) 366 #define TX3912_VIDEOCTRL9_PAT2_4_DEFAULT \ 367 DITHER_PATTERN(0, 0, 0, P1010, P0101, P1010, P0101) 368 #define TX3912_VIDEOCTRL10_PAT4_5_DEFAULT \ 369 DITHER_PATTERN(0, 0, P0111, P1101, P1111, P1011, P1110) 370 #define TX3912_VIDEOCTRL11_PAT3_5_DEFAULT \ 371 DITHER_PATTERN(0, 0, P0111, P1010, P0101, P1010, P1101) 372 #define TX3912_VIDEOCTRL12_PAT6_7_DEFAULT \ 373 DITHER_PATTERN(P1111, P1011, P1111, P1101, P1111, P1110, P0111) 374 #define TX3912_VIDEOCTRL13_PAT5_7_DEFAULT \ 375 DITHER_PATTERN(P0111, P1011, P0101, P1010, P1101, P1110, P1111) 376 #define TX3912_VIDEOCTRL14_PAT4_7_DEFAULT \ 377 DITHER_PATTERN(P1011, P1001, P1101, P1100, P0110, P0110, P0011) 378 379 /* dither duty cycle : pre-dithered data nible mapping */ 380 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1 15 381 #define TX3912_VIDEO_DITHER_DUTYCYCLE_6_7 14 382 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_5 13 383 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_4 12 384 #define TX3912_VIDEO_DITHER_DUTYCYCLE_5_7 11 385 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_3 10 386 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_5 9 387 #define TX3912_VIDEO_DITHER_DUTYCYCLE_4_7 8 388 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_4 7 389 #define TX3912_VIDEO_DITHER_DUTYCYCLE_3_7 6 390 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_5 5 391 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_3 4 392 #define TX3912_VIDEO_DITHER_DUTYCYCLE_2_7 3 393 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_5 2 394 #define TX3912_VIDEO_DITHER_DUTYCYCLE_1_7 1 395 #define TX3912_VIDEO_DITHER_DUTYCYCLE_0 0 396
Indexes created Thu Sep 25 02:09:54 GMT 2025