1 /* $NetBSD: tx39uartreg.h,v 1.3 2008/04/28 20:23:22 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by UCHIYAMA Yasushi. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 /* 32 * Toshiba TX3912/3922 UART module 33 */ 34 35 #define TX39_UARTACTRL1_REG 0x0b0 36 #define TX39_UARTACTRL2_REG 0x0b4 37 #define TX39_UARTADMACTRL1_REG 0x0b8 38 #define TX39_UARTADMACTRL2_REG 0x0bc 39 #define TX39_UARTADMACNT_REG 0x0c0 40 #define TX39_UARTATXHOLD_REG 0x0c4 41 #define TX39_UARTARXHOLD_REG 0x0c4 42 43 #define TX39_UARTBCTRL1_REG 0x0c8 44 #define TX39_UARTBCTRL2_REG 0x0cc 45 #define TX39_UARTBDMACTRL1_REG 0x0d0 46 #define TX39_UARTBDMACTRL2_REG 0x0d4 47 #define TX39_UARTBDMACNT_REG 0x0d8 48 #define TX39_UARTBTXHOLD_REG 0x0dc 49 #define TX39_UARTBRXHOLD_REG 0x0dc 50 51 #define TX39_UARTA_REG_START 0x0b0 52 #define TX39_UARTB_REG_START 0x0c8 53 #define TX39_UARTCTRL1_REG(x) \ 54 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START)) 55 #define TX39_UARTCTRL2_REG(x) \ 56 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 4) 57 #define TX39_UARTDMACTRL1_REG(x) \ 58 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 8) 59 #define TX39_UARTDMACTRL2_REG(x) \ 60 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 12) 61 #define TX39_UARTDMACNT_REG(x) \ 62 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 16) 63 #define TX39_UARTTXHOLD_REG(x) \ 64 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 65 #define TX39_UARTRXHOLD_REG(x) \ 66 (((x) ? TX39_UARTB_REG_START : TX39_UARTA_REG_START) + 20) 67 68 /* 69 * UART Control 1 Register 70 */ 71 /* R */ 72 #define TX39_UARTCTRL1_UARTON 0x80000000 73 #define TX39_UARTCTRL1_EMPTY 0x40000000 74 #define TX39_UARTCTRL1_PRXHOLDFULL 0x20000000 75 #define TX39_UARTCTRL1_RXHOLDFULL 0x10000000 76 /* R/W */ 77 #define TX39_UARTCTRL1_ENDMARX 0x00008000 78 #define TX39_UARTCTRL1_ENDMATX 0x00004000 79 #define TX39_UARTCTRL1_TESTMODE 0x00002000 80 #define TX39_UARTCTRL1_ENBREAHALT 0x00001000 81 #define TX39_UARTCTRL1_ENDMATEST 0x00000800 82 #define TX39_UARTCTRL1_ENDMALOOP 0x00000400 83 #define TX39_UARTCTRL1_PULSEOPT2 0x00000200 84 #define TX39_UARTCTRL1_PULSEOPT1 0x00000100 85 #define TX39_UARTCTRL1_DTINVERT 0x00000080 86 #define TX39_UARTCTRL1_DISTXD 0x00000040 87 #define TX39_UARTCTRL1_TWOSTOP 0x00000020 88 #define TX39_UARTCTRL1_LOOPBACK 0x00000010 89 #define TX39_UARTCTRL1_BIT7 0x00000008 90 #define TX39_UARTCTRL1_EVENPARITY 0x00000004 91 #define TX39_UARTCTRL1_ENPARITY 0x00000002 92 #define TX39_UARTCTRL1_ENUART 0x00000001 93 94 /* 95 * UART Control 2 Register 96 */ 97 /* W */ 98 /* 99 * BaudRate = UART Clock Hz / ((BAUDRATE + 1) * 16) 100 */ 101 #define TX3922_UARTCLOCKHZ 9216000 102 #define TX3912_UARTCLOCKHZ 3686400 103 104 #define TX39_UARTCTRL2_BAUDRATE_SHIFT 0 105 106 #define TX3912_UARTCTRL2_BAUDRATE_MASK 0x3ff 107 #define TX3922_UARTCTRL2_BAUDRATE_MASK 0x7ff 108 109 #ifdef TX391X 110 #define TX39_UARTCLOCKHZ TX3912_UARTCLOCKHZ 111 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3912_UARTCTRL2_BAUDRATE_MASK 112 #elif defined TX392X 113 #define TX39_UARTCLOCKHZ TX3922_UARTCLOCKHZ 114 #define TX39_UARTCTRL2_BAUDRATE_MASK TX3922_UARTCTRL2_BAUDRATE_MASK 115 #endif 116 117 #define TX39_UARTCTRL2_BAUDRATE_SET(cr, val) \ 118 ((cr) | (((val) << TX39_UARTCTRL2_BAUDRATE_SHIFT) & \ 119 (TX39_UARTCTRL2_BAUDRATE_MASK << TX39_UARTCTRL2_BAUDRATE_SHIFT))) 120 121 /* 122 * UART DMA Control 1 Register 123 */ 124 /* W */ 125 #define TX39_UARTDMACTRL1_DMASTARTVAL_MASK 0xfffffffc 126 #define TX39_UARTDMACTRL1_DMASTARTVAL_SET(cr, val) \ 127 ((cr) | ((val) & TX39_UARTDMACTRL1_DMASTARTVAL_MASK)) 128 129 /* 130 * UART DMA Control 2 Register 131 */ 132 /* W */ 133 #define TX39_UARTDMACTRL2_DMALENGTH_MASK 0x0000ffff 134 #define TX39_UARTDMACTRL2_DMALENGTH_SET(cr, val) \ 135 ((cr) | ((val) & TX39_UARTDMACTRL1_DMALENGTH_MASK)) 136 137 /* 138 * UART DMA Count Register 139 */ 140 /* R */ 141 #define TX39_UARTDMACNT_DMACNT_SHIFT 0 142 #define TX39_UARTDMACNT_DMACNT_MASK 0xffff 143 #define TX39_UARTDMACNT_DMACNT(cr) \ 144 ((cr) & TX39_UARTDMACNT_DMACNT_MASK) 145 146 /* 147 * UART Transmit Holding Register 148 */ 149 /* W */ 150 #define TX39_UARTTXHOLD_BREAK 0x00000100 151 #define TX39_UARTTXHOLD_TXDATA_SHIFT 0 152 #define TX39_UARTTXHOLD_TXDATA_MASK 0x000000ff 153 #define TX39_UARTTXHOLD_TXDATA_SET(cr, val) \ 154 ((cr) | ((val) & TX39_UARTTXHOLD_TXDATA_MASK)) 155 156 /* 157 * UART Receiver Holding Register 158 */ 159 /* R */ 160 #define TX39_UARTRXHOLD_RXDATA_SHIFT 0 161 #define TX39_UARTRXHOLD_RXDATA_MASK 0x000000ff 162 #define TX39_UARTRXHOLD_RXDATA(cr) \ 163 ((cr) & TX39_UARTRXHOLD_RXDATA_MASK) 164
Indexes created Tue Sep 23 02:09:52 GMT 2025