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    Searched defs:TargetReg (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
MipsNaClELFStreamer.cpp 186 unsigned TargetReg = Inst.getOperand(1).getReg();
187 emitMask(TargetReg, IndirectBranchMaskReg, STI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsSEInstrInfo.cpp 888 // indirect jump to TargetReg
896 Register TargetReg = I->getOperand(1).getReg();
904 .addReg(TargetReg)
907 .addReg(TargetReg)
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86SpeculativeLoadHardening.cpp 993 unsigned TargetReg;
1024 TargetReg = TI.getOperand(0).getReg();
1044 TargetAddrSSA.AddAvailableValue(&MBB, TargetReg);
1111 Register TargetReg = MRI->createVirtualRegister(&X86::GR64RegClass);
1116 TII->get(X86::MOV64ri32), TargetReg)
1124 TargetReg)
1136 TargetAddrSSA.AddAvailableValue(Pred, TargetReg);
1144 unsigned TargetReg = TargetAddrSSA.GetValueInMiddleOfBlock(&MBB);
1155 .addReg(TargetReg, RegState::Kill)
1174 .addReg(TargetReg, RegState::Kill
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