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    Searched defs:Tmp3 (Results 1 - 11 of 11) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
IntrinsicLowering.cpp 73 Value *Tmp3 = Builder.CreateShl(V, ConstantInt::get(V->getType(), 8),
79 Tmp3 = Builder.CreateAnd(Tmp3,
85 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or1");
101 Value* Tmp3 = Builder.CreateLShr(V,
126 Tmp3 = Builder.CreateAnd(Tmp3,
136 Tmp4 = Builder.CreateOr(Tmp4, Tmp3, "bswap.or3");
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
LegalizeDAG.cpp 365 SDValue Tmp3 = Idx;
384 SDValue StackPtr2 = TLI.getVectorElementPointer(DAG, StackPtr, VT, Tmp3);
1654 SDValue Tmp3 = Node->getOperand(2);
1664 Align Alignment = cast<ConstantSDNode>(Tmp3)->getAlignValue();
2670 SDValue Tmp1, Tmp2, Tmp3, Tmp4;
3489 Tmp3 = Node->getOperand(2);
3492 Tmp2, Tmp3,
3497 Tmp2, Tmp3, ISD::SETNE);
3560 Tmp3 = Tmp2;
3562 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp2.getValueType(), Tmp2
    [all...]
LegalizeFloatTypes.cpp 1820 SDValue Tmp1, Tmp2, Tmp3, OutputChain;
1827 Tmp3 = DAG.getNode(ISD::AND, dl, Tmp1.getValueType(), Tmp1, Tmp2);
1836 NewLHS = DAG.getNode(ISD::OR, dl, Tmp1.getValueType(), Tmp1, Tmp3);
  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Utils/
IntegerDivision.cpp 124 // ; %tmp3 = xor i32 %tmp1, %divisor
125 // ; %u_dvsr = sub nsw i32 %tmp3, %tmp1
134 Value *Tmp3 = Builder.CreateXor(Tmp1, Divisor);
135 Value *U_Dvsr = Builder.CreateSub(Tmp3, Tmp1);
278 // ; %tmp3 = lshr i32 %dividend, %sr_1
282 Value *Tmp3 = Builder.CreateLShr(Dividend, SR_1);
289 // ; %r_1 = phi i32 [ %tmp3, %preheader ], [ %r, %do-while ]
349 // ; %r_1 = phi i32 [ %tmp3, %preheader ], [ %r, %do-while ]
350 R_1->addIncoming(Tmp3, Preheader);
  /src/external/apache2/llvm/dist/clang/lib/CodeGen/
CGExprComplex.cpp 857 llvm::Value *Tmp3 = Builder.CreateAdd(Tmp1, Tmp2); // ac+bd
868 DSTr = Builder.CreateUDiv(Tmp3, Tmp6);
871 DSTr = Builder.CreateSDiv(Tmp3, Tmp6);
  /src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
NVPTXISelLowering.cpp 2399 SDValue Tmp3 = ST->getValue();
2400 assert(Tmp3.getValueType() == MVT::i1 && "Custom lowering for i1 store only");
2401 Tmp3 = DAG.getNode(ISD::ZERO_EXTEND, dl, MVT::i16, Tmp3);
2403 DAG.getTruncStore(Tmp1, dl, Tmp3, Tmp2, ST->getPointerInfo(), MVT::i8,
  /src/external/apache2/llvm/dist/llvm/lib/Target/VE/
VEISelLowering.cpp 1895 // lea.sl %Tmp3, Symbol@gotoff_hi(%Tmp2, %s15) ; %s15 is GOT
1896 // ld %Result, 0(%Tmp3)
1897 Register Tmp3 = MRI.createVirtualRegister(RC);
1905 BuildMI(MBB, I, DL, TII->get(VE::LEASLrri), Tmp3)
1910 .addReg(Tmp3, getKillRegState(true))
  /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
MipsISelLowering.cpp 2294 SDValue Tmp3 =
2299 Chain = DAG.getStore(VAListLoad.getValue(1), DL, Tmp3, VAListPtr,
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86ISelDAGToDAG.cpp 3733 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3734 if (tryFoldLoad(Node, N0.getNode(), Input, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3736 Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Control, Input.getOperand(0)};
3769 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3770 if (MayFoldLoad && tryFoldLoad(Node, N1, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3771 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
3802 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4;
3803 if (MayFoldLoad && tryFoldLoad(Node, N2, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4)) {
3804 SDValue Ops[] = { N0, Tmp0, Tmp1, Tmp2, Tmp3, Tmp4, Imm,
4070 SDValue Tmp0, Tmp1, Tmp2, Tmp3, Tmp4
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIISelLowering.cpp 3274 SDValue Tmp3 = Op.getOperand(2);
3286 MaybeAlign Alignment = cast<ConstantSDNode>(Tmp3)->getMaybeAlignValue();
9877 SDValue Tmp3 = DAG.getNode(ExtOp, SL, NVT, Op1);
9879 SDValue Med3 = DAG.getNode(Med3Opc, SL, NVT, Tmp1, Tmp2, Tmp3);
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCISelLowering.cpp 8737 SDValue Tmp3 = DAG.getNode(PPCISD::SRL, dl, VT, Lo, Tmp1);
8738 SDValue Tmp4 = DAG.getNode(ISD::OR , dl, VT, Tmp2, Tmp3);
8766 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
8767 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
8794 SDValue Tmp3 = DAG.getNode(PPCISD::SHL, dl, VT, Hi, Tmp1);
8795 SDValue Tmp4 = DAG.getNode(ISD::OR, dl, VT, Tmp2, Tmp3);
11251 // and tmp3, tmp, mask
11252 // or tmp4, tmp3, tmp2

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