| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCAsmPrinter.cpp | 61 MCInst TmpInst;
62 MCInstLowering.Lower(MI, TmpInst);
63 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/BPF/ |
| BPFAsmPrinter.cpp | 141 MCInst TmpInst;
143 if (!BTF || !BTF->InstLower(MI, TmpInst)) {
145 MCInstLowering.Lower(MI, TmpInst);
147 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| LanaiAsmPrinter.cpp | 175 MCInst TmpInst;
176 MCInstLowering.Lower(MI, TmpInst);
177 TmpInst.setOpcode(Lanai::BT);
178 OutStreamer->emitInstruction(TmpInst, STI);
192 MCInst TmpInst;
193 MCInstLowering.Lower(MI, TmpInst);
194 OutStreamer->emitInstruction(TmpInst, STI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| MSP430AsmPrinter.cpp | 154 MCInst TmpInst;
155 MCInstLowering.Lower(MI, TmpInst);
156 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/ |
| RISCVMCCodeEmitter.cpp | 112 MCInst TmpInst;
135 TmpInst = MCInstBuilder(RISCV::AUIPC)
138 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
144 TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
147 TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
148 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
182 MCInst TmpInst = MCInstBuilder(RISCV::ADD)
186 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/XCore/ |
| XCoreAsmPrinter.cpp | 287 MCInst TmpInst;
288 MCInstLowering.Lower(MI, TmpInst);
290 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| AMDGPUMCInstLower.cpp | 298 MCInst TmpInst;
299 MCInstLowering.lower(MI, TmpInst);
300 EmitToStreamer(*OutStreamer, TmpInst);
319 InstEmitter->encodeInstruction(TmpInst, CodeStream, Fixups, STI);
333 InstPrinter.printInst(&TmpInst, 0, StringRef(), STI, DisasmStream);
341 TmpInst, CodeStream, Fixups, MF->getSubtarget<MCSubtargetInfo>());
389 MCInst TmpInst;
390 MCInstLowering.lower(MI, TmpInst);
391 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/ |
| SparcAsmPrinter.cpp | 266 MCInst TmpInst;
267 LowerSparcMachineInstrToMCInst(&*I, TmpInst, *this);
268 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/VE/ |
| VEAsmPrinter.cpp | 349 MCInst TmpInst;
350 LowerVEMachineInstrToMCInst(&*I, TmpInst, *this);
351 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| HexagonAsmPrinter.cpp | 334 MCInst TmpInst;
336 TmpInst.setOpcode(Hexagon::L2_loadrdgp);
337 TmpInst.addOperand(Reg);
338 TmpInst.addOperand(MCOperand::createExpr(
340 MappedInst = TmpInst;
350 MCInst TmpInst;
352 TmpInst.setOpcode(Hexagon::L2_loadrigp);
353 TmpInst.addOperand(Reg);
354 TmpInst.addOperand(MCOperand::createExpr(HexagonMCExpr::create(
356 MappedInst = TmpInst;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/ |
| MipsMCCodeEmitter.cpp | 161 MCInst TmpInst = MI;
168 LowerLargeShift(TmpInst);
179 LowerCompactBranch(TmpInst);
183 uint32_t Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
188 const unsigned Opcode = TmpInst.getOpcode();
211 TmpInst.setOpcode (NewOpcode);
212 Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
222 const MCInstrDesc &Desc = MCII.get(TmpInst.getOpcode());
|
| MipsTargetStreamer.cpp | 171 MCInst TmpInst;
172 TmpInst.setOpcode(Opcode);
173 TmpInst.addOperand(MCOperand::createReg(Reg0));
174 TmpInst.setLoc(IDLoc);
175 getStreamer().emitInstruction(TmpInst, *STI);
180 MCInst TmpInst;
181 TmpInst.setOpcode(Opcode);
182 TmpInst.addOperand(MCOperand::createReg(Reg0));
183 TmpInst.addOperand(Op1);
184 TmpInst.setLoc(IDLoc)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyAsmPrinter.cpp | 526 MCInst TmpInst;
527 MCInstLowering.lower(MI, TmpInst);
528 EmitToStreamer(*OutStreamer, TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| RDFLiveness.cpp | 240 std::vector<NodeId> TmpInst;
243 TmpInst.insert(TmpInst.end(), Bucket.rbegin(), Bucket.rend());
270 for (NodeId T : TmpInst) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| AArch64AsmPrinter.cpp | 1207 MCInst TmpInst;
1208 TmpInst.setOpcode(AArch64::MOVIv16b_ns);
1209 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1210 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm()));
1211 EmitToStreamer(*OutStreamer, TmpInst);
1246 MCInst TmpInst;
1247 TmpInst.setOpcode(AArch64::BR);
1248 TmpInst.addOperand(MCOperand::createReg(MI->getOperand(0).getReg()));
1249 EmitToStreamer(*OutStreamer, TmpInst);
1255 MCInst TmpInst;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Disassembler/ |
| AMDGPUDisassembler.cpp | 390 MCInst TmpInst;
393 if (decodeInstruction(Table, TmpInst, Inst, Address, this, STI)) {
394 MI = TmpInst;
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/AsmParser/ |
| SparcAsmParser.cpp | 594 MCInst TmpInst;
596 TmpInst.setLoc(IDLoc);
597 TmpInst.setOpcode(SP::SETHIi);
598 TmpInst.addOperand(MCRegOp);
599 TmpInst.addOperand(MCOperand::createExpr(Expr));
600 Instructions.push_back(TmpInst);
615 MCInst TmpInst;
621 TmpInst.setLoc(IDLoc);
622 TmpInst.setOpcode(SP::ORri);
623 TmpInst.addOperand(MCRegOp)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86MCInstLower.cpp | 2612 MCInst TmpInst;
2613 MCInstLowering.Lower(MI, TmpInst);
2621 SMShadowTracker.count(TmpInst, getSubtargetInfo(), CodeEmitter.get());
2626 OutStreamer->emitInstruction(TmpInst, getSubtargetInfo());
2630 EmitAndCountInstruction(TmpInst);
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/ |
| HexagonAsmParser.cpp | 1236 MCInst TmpInst;
1237 TmpInst.setOpcode(opCode);
1238 TmpInst.addOperand(Rdd);
1239 TmpInst.addOperand(MO1);
1240 TmpInst.addOperand(MO2);
1242 return TmpInst;
1389 MCInst TmpInst;
1392 TmpInst.setOpcode(Hexagon::C2_cmpeq);
1393 TmpInst.addOperand(Pd);
1394 TmpInst.addOperand(Rt)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/ |
| PPCAsmParser.cpp | 753 MCInst TmpInst;
754 TmpInst.setOpcode((Opcode == PPC::DCBTx || Opcode == PPC::DCBTT) ?
756 TmpInst.addOperand(MCOperand::createImm(
758 TmpInst.addOperand(Inst.getOperand(0));
759 TmpInst.addOperand(Inst.getOperand(1));
760 Inst = TmpInst;
765 MCInst TmpInst;
766 TmpInst.setOpcode(PPC::DCBT);
767 TmpInst.addOperand(Inst.getOperand(2));
768 TmpInst.addOperand(Inst.getOperand(0))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| PPCAsmPrinter.cpp | 626 MCInst TmpInst;
756 LowerPPCMachineInstrToMCInst(MI, TmpInst, *this);
758 unsigned PICR = TmpInst.getOperand(0).getReg();
781 TmpInst.setOpcode(PPC::LWZ);
788 const MCOperand TR = TmpInst.getOperand(1);
789 const MCOperand PICR = TmpInst.getOperand(0);
792 TmpInst.getOperand(1) =
794 TmpInst.getOperand(0) = TR;
795 TmpInst.getOperand(2) = PICR;
796 EmitToStreamer(*OutStreamer, TmpInst);
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/AsmParser/ |
| X86AsmParser.cpp | 3693 MCInst TmpInst;
3694 TmpInst.setOpcode(NewOpc);
3695 TmpInst.addOperand(Inst.getOperand(0));
3696 TmpInst.addOperand(Inst.getOperand(1));
3697 Inst = TmpInst;
3746 MCInst TmpInst;
3747 TmpInst.setOpcode(NewOpc);
3749 TmpInst.addOperand(Inst.getOperand(i));
3750 Inst = TmpInst;
3759 MCInst TmpInst;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/AsmParser/ |
| ARMAsmParser.cpp | 8679 MCInst TmpInst;
8680 TmpInst.setOpcode(Opcode);
8681 TmpInst.addOperand(Inst.getOperand(0));
8682 TmpInst.addOperand(Inst.getOperand(1));
8683 TmpInst.addOperand(Inst.getOperand(1));
8684 TmpInst.addOperand(MCOperand::createReg(0));
8685 TmpInst.addOperand(MCOperand::createImm(0));
8686 TmpInst.addOperand(Inst.getOperand(2));
8687 TmpInst.addOperand(Inst.getOperand(3));
8688 Inst = TmpInst;
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/AsmParser/ |
| MipsAsmParser.cpp | 5055 MCInst TmpInst;
|
