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    Searched defs:Ty1 (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
ARMRegisterBankInfo.cpp 404 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
408 assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
411 unsigned Size = Ty1.getSizeInBits();
425 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
427 if (Ty.getSizeInBits() != 64 || Ty1.getSizeInBits() != 32 ||
440 LLT Ty1 = MRI.getType(MI.getOperand(1).getReg());
442 if (Ty.getSizeInBits() != 32 || Ty1.getSizeInBits() != 32 ||
  /src/external/apache2/llvm/dist/llvm/lib/Target/X86/
X86RegisterBankInfo.cpp 216 const LLT Ty1 = MRI.getType(Op1.getReg());
221 OpRegBankIdx[1] = getPartialMappingIdx(Ty1, /* isFP */ SecondArgIsFP);
225 LLT Ty1 = MRI.getType(MI.getOperand(2).getReg());
228 assert(Ty1.getSizeInBits() == Ty2.getSizeInBits() &&
231 unsigned Size = Ty1.getSizeInBits();
235 auto FpRegBank = getPartialMappingIdx(Ty1, /* isFP */ true);
245 const LLT Ty1 = MRI.getType(Op1.getReg());
248 Ty1.getSizeInBits() == 128 && Opc == TargetOpcode::G_TRUNC;
251 (Ty1.getSizeInBits() == 32 || Ty1.getSizeInBits() == 64) &
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  /src/external/apache2/llvm/dist/llvm/lib/Transforms/Vectorize/
SLPVectorizer.cpp 435 Type *Ty1 = cast<Instruction>(VL[Cnt])->getOperand(0)->getType();
436 if (Ty0 == Ty1) {
3168 Type *Ty1 = VL0->getOperand(1)->getType();
3172 (Op->getType() != Ty1 &&

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