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      1 /*-
      2  * Copyright (c) 2012 The NetBSD Foundation, Inc.
      3  * All rights reserved.
      4  *
      5  * This code is derived from software contributed to The NetBSD Foundation
      6  * by Paul Fleischer <paul (at) xpg.dk>
      7  *
      8  * Redistribution and use in source and binary forms, with or without
      9  * modification, are permitted provided that the following conditions
     10  * are met:
     11  * 1. Redistributions of source code must retain the above copyright
     12  *    notice, this list of conditions and the following disclaimer.
     13  * 2. Redistributions in binary form must reproduce the above copyright
     14  *    notice, this list of conditions and the following disclaimer in the
     15  *    documentation and/or other materials provided with the distribution.
     16  *
     17  * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS
     18  * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED
     19  * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR
     20  * PURPOSE ARE DISCLAIMED.  IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS
     21  * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
     22  * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
     23  * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
     24  * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
     25  * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
     26  * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
     27  * POSSIBILITY OF SUCH DAMAGE.
     28  */
     29 #ifndef _DEV_IC_UDA1341REG_H_
     30 #define _DEV_IC_UDA1341REG_H_
     31 
     32 #define UDA1341_L3_ADDR_DEVICE	0x14 /* Address of the UDA1341 on the L3 bus */
     33 #define UDA1341_L3_ADDR_DATA0	0x00
     34 #define UDA1341_L3_ADDR_DATA1	0x01
     35 #define UDA1341_L3_ADDR_STATUS	0x02
     36 
     37 /* Status address has two "banks", 0 and 1.
     38    The bank is selected as bit 7 of the data written.
     39  */
     40 #define UDA1341_L3_STATUS0	(0<<7)
     41 #define UDA1341_L3_STATUS1	(1<<7)
     42 
     43 /** Status bank 0 **/
     44 #define UDA1341_L3_STATUS0_RST		(1<<6)
     45 
     46 /* System clock selection (bit 4 and 5) */
     47 #define UDA1341_L3_STATUS0_SC_512	(0<<4)
     48 #define	UDA1341_L3_STATUS0_SC_384	(1<<4)
     49 #define	UDA1341_L3_STATUS0_SC_256	(2<<4)
     50 #define UDA1341_L3_STATUS0_SC_NA	(3<<4)
     51 #define UDA1341_L3_STATUS0_SC_SHIFT	4
     52 
     53 /* Interface format (bit 1, 2, 3)*/
     54 #define UDA1341_L3_STATUS0_IF_I2S	(0<<1)
     55 #define UDA1341_L3_STATUS0_IF_LSB16	(1<<1)
     56 #define UDA1341_L3_STATUS0_IF_LSB18	(2<<1)
     57 #define UDA1341_L3_STATUS0_IF_LSB20	(3<<1)
     58 #define UDA1341_L3_STATUS0_IF_MSB	(4<<1)
     59 #define UDA1341_L3_STATUS0_IF_LSB16_MSB	(5<<1)
     60 #define UDA1341_L3_STATUS0_IF_LSB18_MSB	(6<<1)
     61 #define UDA1341_L3_STATUS0_IF_LSB20_MSB (7<<1)
     62 #define UDA1341_L3_STATUS0_IF_SHIFT	1
     63 
     64 /* DC-Filtering */
     65 #define UDA1341_L3_STATUS0_DC_FILTERING (1<<0)
     66 
     67 /** Status bank 1**/
     68 
     69 /* Output and Input Gain*/
     70 #define UDA1341_L3_STATUS1_OGS_6DB	(1<<6)
     71 #define UDA1341_L3_STATUS1_IGS_6DB	(1<<5)
     72 
     73 /* DAC and ADC polarity inversion */
     74 #define UDA1341_L3_STATUS1_PAD_INV	(1<<4)
     75 #define UDA1341_L3_STATUS1_PDA_INV	(1<<3)
     76 
     77 /* Double speed playback */
     78 #define UDA1341_L3_STATUS1_DS		(1<<2)
     79 
     80 /* Power Control */
     81 #define UDA1341_L3_STATUS1_PC_ADC	(1<<1)
     82 #define UDA1341_L3_STATUS1_PC_DAC	(1<<0)
     83 
     84 /*** DATA0 ***/
     85 /*
     86  * Data0 has five banks: three for direct control, and two for extended access.
     87  */
     88 #define UDA1341_L3_DATA0_VOLUME		(0<<6)
     89 #define UDA1341_L3_DATA0_VOLUME_MASK	(0x3F)
     90 
     91 #define UDA1341_L3_DATA0_BASS_TREBLE	(1<<6)
     92 #define UDA1341_L3_DATA0_BASS_SHIFT	2
     93 #define UDA1341_L3_DATA0_BASS_MASK	0x3C
     94 #define UDA1341_L3_DATA0_TREBLE_SHIFT	0
     95 #define UDA1341_L3_DATA0_TREBLE_MASK	0x03
     96 
     97 #define UDA1341_L3_DATA0_SOUNDC		(2<<6)
     98 #define UDA1341_L3_DATA0_SOUNDC_DE_MASK (0x18)
     99 #define UDA1341_L3_DATA0_SOUNDC_DE_SHIFT 3
    100 #define UDA1341_L3_DATA0_SOUNDC_MUTE	(1<<2)
    101 #define UDA1341_L3_DATA0_SOUNDC_MODE_MASK (0x03)
    102 
    103 #define UDA1341_L3_DATA0_EA		((3<<6)|0<<5)
    104 #define UDA1341_L3_DATA0_ED		((3<<6)|1<<5)
    105 
    106 #define UDA1341_L3_DATA0_MA_MASK	(0x1F)
    107 #define UDA1341_L3_DATA0_MB_MASK	(0x1F)
    108 
    109 #define UDA1341_L3_DATA0_MS_MASK	(0x1C)
    110 #define UDA1341_L3_DATA0_MS_SHIFT	2
    111 
    112 #define UDA1341_L3_DATA0_MM_MASK	(0x03)
    113 
    114 #define UDA1341_L3_DATA0_AGC_SHIFT	4
    115 #define UDA1341_L3_DATA0_AGC_MASK	(0x10)
    116 
    117 #define UDA1341_L3_DATA0_IG_LOW_MASK	(0x03)
    118 #define UDA1341_L3_DATA0_IG_HIGH_MASK	(0x1F)
    119 
    120 #define UDA1341_L3_DATA0_AL_MASK	(0x03)
    121 #endif
    122