1 /* $NetBSD: vcn_1_0_sh_mask.h,v 1.2 2021/12/18 23:45:24 riastradh Exp $ */ 2 3 /* 4 * Copyright (C) 2017 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included 14 * in all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS 17 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN 20 * AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN 21 * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. 22 */ 23 #ifndef _vcn_1_0_SH_MASK_HEADER 24 #define _vcn_1_0_SH_MASK_HEADER 25 26 27 // addressBlock: uvd_uvd_pg_dec 28 //UVD_PGFSM_CONFIG 29 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG__SHIFT 0x0 30 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG__SHIFT 0x2 31 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG__SHIFT 0x4 32 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG__SHIFT 0x6 33 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG__SHIFT 0x8 34 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG__SHIFT 0xa 35 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG__SHIFT 0xc 36 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG__SHIFT 0xe 37 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG__SHIFT 0x10 38 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG__SHIFT 0x12 39 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG__SHIFT 0x14 40 #define UVD_PGFSM_CONFIG__UVDM_PWR_CONFIG_MASK 0x00000003L 41 #define UVD_PGFSM_CONFIG__UVDU_PWR_CONFIG_MASK 0x0000000CL 42 #define UVD_PGFSM_CONFIG__UVDF_PWR_CONFIG_MASK 0x00000030L 43 #define UVD_PGFSM_CONFIG__UVDC_PWR_CONFIG_MASK 0x000000C0L 44 #define UVD_PGFSM_CONFIG__UVDB_PWR_CONFIG_MASK 0x00000300L 45 #define UVD_PGFSM_CONFIG__UVDIL_PWR_CONFIG_MASK 0x00000C00L 46 #define UVD_PGFSM_CONFIG__UVDIR_PWR_CONFIG_MASK 0x00003000L 47 #define UVD_PGFSM_CONFIG__UVDTD_PWR_CONFIG_MASK 0x0000C000L 48 #define UVD_PGFSM_CONFIG__UVDTE_PWR_CONFIG_MASK 0x00030000L 49 #define UVD_PGFSM_CONFIG__UVDE_PWR_CONFIG_MASK 0x000C0000L 50 #define UVD_PGFSM_CONFIG__UVDW_PWR_CONFIG_MASK 0x00300000L 51 //UVD_PGFSM_STATUS 52 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS__SHIFT 0x0 53 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS__SHIFT 0x2 54 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS__SHIFT 0x4 55 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS__SHIFT 0x6 56 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS__SHIFT 0x8 57 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS__SHIFT 0xa 58 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS__SHIFT 0xc 59 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS__SHIFT 0xe 60 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS__SHIFT 0x10 61 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS__SHIFT 0x12 62 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS__SHIFT 0x14 63 #define UVD_PGFSM_STATUS__UVDM_PWR_STATUS_MASK 0x00000003L 64 #define UVD_PGFSM_STATUS__UVDU_PWR_STATUS_MASK 0x0000000CL 65 #define UVD_PGFSM_STATUS__UVDF_PWR_STATUS_MASK 0x00000030L 66 #define UVD_PGFSM_STATUS__UVDC_PWR_STATUS_MASK 0x000000C0L 67 #define UVD_PGFSM_STATUS__UVDB_PWR_STATUS_MASK 0x00000300L 68 #define UVD_PGFSM_STATUS__UVDIL_PWR_STATUS_MASK 0x00000C00L 69 #define UVD_PGFSM_STATUS__UVDIR_PWR_STATUS_MASK 0x00003000L 70 #define UVD_PGFSM_STATUS__UVDTD_PWR_STATUS_MASK 0x0000C000L 71 #define UVD_PGFSM_STATUS__UVDTE_PWR_STATUS_MASK 0x00030000L 72 #define UVD_PGFSM_STATUS__UVDE_PWR_STATUS_MASK 0x000C0000L 73 #define UVD_PGFSM_STATUS__UVDW_PWR_STATUS_MASK 0x00300000L 74 //UVD_POWER_STATUS 75 #define UVD_POWER_STATUS__UVD_POWER_STATUS__SHIFT 0x0 76 #define UVD_POWER_STATUS__UVD_PG_MODE__SHIFT 0x2 77 #define UVD_POWER_STATUS__UVD_CG_MODE__SHIFT 0x4 78 #define UVD_POWER_STATUS__UVD_PG_EN__SHIFT 0x8 79 #define UVD_POWER_STATUS__RBC_SNOOP_DIS__SHIFT 0x9 80 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS__SHIFT 0xa 81 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS__SHIFT 0xb 82 #define UVD_POWER_STATUS__UVD_POWER_STATUS_MASK 0x00000003L 83 #define UVD_POWER_STATUS__UVD_PG_MODE_MASK 0x00000004L 84 #define UVD_POWER_STATUS__UVD_CG_MODE_MASK 0x00000030L 85 #define UVD_POWER_STATUS__UVD_PG_EN_MASK 0x00000100L 86 #define UVD_POWER_STATUS__RBC_SNOOP_DIS_MASK 0x00000200L 87 #define UVD_POWER_STATUS__JRBC_SNOOP_DIS_MASK 0x00000400L 88 #define UVD_POWER_STATUS__SW_RB_SNOOP_DIS_MASK 0x00000800L 89 //CC_UVD_HARVESTING 90 #define CC_UVD_HARVESTING__UVD_DISABLE__SHIFT 0x1 91 #define CC_UVD_HARVESTING__UVD_DISABLE_MASK 0x00000002L 92 //UVD_DPG_LMA_CTL 93 #define UVD_DPG_LMA_CTL__READ_WRITE__SHIFT 0x0 94 #define UVD_DPG_LMA_CTL__MASK_EN__SHIFT 0x1 95 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT__SHIFT 0x2 96 #define UVD_DPG_LMA_CTL__SRAM_SEL__SHIFT 0x4 97 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR__SHIFT 0x10 98 #define UVD_DPG_LMA_CTL__READ_WRITE_MASK 0x00000001L 99 #define UVD_DPG_LMA_CTL__MASK_EN_MASK 0x00000002L 100 #define UVD_DPG_LMA_CTL__ADDR_AUTO_INCREMENT_MASK 0x00000004L 101 #define UVD_DPG_LMA_CTL__SRAM_SEL_MASK 0x00000010L 102 #define UVD_DPG_LMA_CTL__READ_WRITE_ADDR_MASK 0xFFFF0000L 103 //UVD_DPG_PAUSE 104 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ__SHIFT 0x0 105 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK__SHIFT 0x1 106 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ__SHIFT 0x2 107 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK__SHIFT 0x3 108 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_REQ_MASK 0x00000001L 109 #define UVD_DPG_PAUSE__JPEG_PAUSE_DPG_ACK_MASK 0x00000002L 110 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_REQ_MASK 0x00000004L 111 #define UVD_DPG_PAUSE__NJ_PAUSE_DPG_ACK_MASK 0x00000008L 112 //UVD_SCRATCH1 113 #define UVD_SCRATCH1__SCRATCH1_DATA__SHIFT 0x0 114 #define UVD_SCRATCH1__SCRATCH1_DATA_MASK 0xFFFFFFFFL 115 //UVD_SCRATCH2 116 #define UVD_SCRATCH2__SCRATCH2_DATA__SHIFT 0x0 117 #define UVD_SCRATCH2__SCRATCH2_DATA_MASK 0xFFFFFFFFL 118 //UVD_SCRATCH3 119 #define UVD_SCRATCH3__SCRATCH3_DATA__SHIFT 0x0 120 #define UVD_SCRATCH3__SCRATCH3_DATA_MASK 0xFFFFFFFFL 121 //UVD_SCRATCH4 122 #define UVD_SCRATCH4__SCRATCH4_DATA__SHIFT 0x0 123 #define UVD_SCRATCH4__SCRATCH4_DATA_MASK 0xFFFFFFFFL 124 //UVD_SCRATCH5 125 #define UVD_SCRATCH5__SCRATCH5_DATA__SHIFT 0x0 126 #define UVD_SCRATCH5__SCRATCH5_DATA_MASK 0xFFFFFFFFL 127 //UVD_SCRATCH6 128 #define UVD_SCRATCH6__SCRATCH6_DATA__SHIFT 0x0 129 #define UVD_SCRATCH6__SCRATCH6_DATA_MASK 0xFFFFFFFFL 130 //UVD_SCRATCH7 131 #define UVD_SCRATCH7__SCRATCH7_DATA__SHIFT 0x0 132 #define UVD_SCRATCH7__SCRATCH7_DATA_MASK 0xFFFFFFFFL 133 //UVD_SCRATCH8 134 #define UVD_SCRATCH8__SCRATCH8_DATA__SHIFT 0x0 135 #define UVD_SCRATCH8__SCRATCH8_DATA_MASK 0xFFFFFFFFL 136 //UVD_SCRATCH9 137 #define UVD_SCRATCH9__SCRATCH9_DATA__SHIFT 0x0 138 #define UVD_SCRATCH9__SCRATCH9_DATA_MASK 0xFFFFFFFFL 139 //UVD_SCRATCH10 140 #define UVD_SCRATCH10__SCRATCH10_DATA__SHIFT 0x0 141 #define UVD_SCRATCH10__SCRATCH10_DATA_MASK 0xFFFFFFFFL 142 //UVD_SCRATCH11 143 #define UVD_SCRATCH11__SCRATCH11_DATA__SHIFT 0x0 144 #define UVD_SCRATCH11__SCRATCH11_DATA_MASK 0xFFFFFFFFL 145 //UVD_SCRATCH12 146 #define UVD_SCRATCH12__SCRATCH12_DATA__SHIFT 0x0 147 #define UVD_SCRATCH12__SCRATCH12_DATA_MASK 0xFFFFFFFFL 148 //UVD_SCRATCH13 149 #define UVD_SCRATCH13__SCRATCH13_DATA__SHIFT 0x0 150 #define UVD_SCRATCH13__SCRATCH13_DATA_MASK 0xFFFFFFFFL 151 //UVD_SCRATCH14 152 #define UVD_SCRATCH14__SCRATCH14_DATA__SHIFT 0x0 153 #define UVD_SCRATCH14__SCRATCH14_DATA_MASK 0xFFFFFFFFL 154 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW 155 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 156 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 157 //UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH 158 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 159 #define UVD_DPG_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 160 //UVD_DPG_VCPU_CACHE_OFFSET0 161 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 162 #define UVD_DPG_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x01FFFFFFL 163 164 165 // addressBlock: uvd_uvdgendec 166 //UVD_LCM_CGC_CNTRL 167 #define UVD_LCM_CGC_CNTRL__FORCE_OFF__SHIFT 0x12 168 #define UVD_LCM_CGC_CNTRL__FORCE_ON__SHIFT 0x13 169 #define UVD_LCM_CGC_CNTRL__OFF_DELAY__SHIFT 0x14 170 #define UVD_LCM_CGC_CNTRL__ON_DELAY__SHIFT 0x1c 171 #define UVD_LCM_CGC_CNTRL__FORCE_OFF_MASK 0x00040000L 172 #define UVD_LCM_CGC_CNTRL__FORCE_ON_MASK 0x00080000L 173 #define UVD_LCM_CGC_CNTRL__OFF_DELAY_MASK 0x0FF00000L 174 #define UVD_LCM_CGC_CNTRL__ON_DELAY_MASK 0xF0000000L 175 176 177 // addressBlock: uvd_uvdnpdec 178 //UVD_JPEG_CNTL 179 #define UVD_JPEG_CNTL__SOFT_RESET__SHIFT 0x0 180 #define UVD_JPEG_CNTL__REQUEST_EN__SHIFT 0x1 181 #define UVD_JPEG_CNTL__ERR_RST_EN__SHIFT 0x2 182 #define UVD_JPEG_CNTL__HUFF_SPEED_EN__SHIFT 0x3 183 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS__SHIFT 0x4 184 #define UVD_JPEG_CNTL__DBG_MUX_SEL__SHIFT 0x8 185 #define UVD_JPEG_CNTL__SOFT_RESET_MASK 0x00000001L 186 #define UVD_JPEG_CNTL__REQUEST_EN_MASK 0x00000002L 187 #define UVD_JPEG_CNTL__ERR_RST_EN_MASK 0x00000004L 188 #define UVD_JPEG_CNTL__HUFF_SPEED_EN_MASK 0x00000008L 189 #define UVD_JPEG_CNTL__HUFF_SPEED_STATUS_MASK 0x00000010L 190 #define UVD_JPEG_CNTL__DBG_MUX_SEL_MASK 0x00007F00L 191 //UVD_JPEG_RB_BASE 192 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF__SHIFT 0x0 193 #define UVD_JPEG_RB_BASE__RB_BASE__SHIFT 0x6 194 #define UVD_JPEG_RB_BASE__RB_BYTE_OFF_MASK 0x0000003FL 195 #define UVD_JPEG_RB_BASE__RB_BASE_MASK 0xFFFFFFC0L 196 //UVD_JPEG_RB_WPTR 197 #define UVD_JPEG_RB_WPTR__RB_WPTR__SHIFT 0x4 198 #define UVD_JPEG_RB_WPTR__RB_WPTR_MASK 0x3FFFFFF0L 199 //UVD_JPEG_RB_RPTR 200 #define UVD_JPEG_RB_RPTR__RB_RPTR__SHIFT 0x4 201 #define UVD_JPEG_RB_RPTR__RB_RPTR_MASK 0x3FFFFFF0L 202 //UVD_JPEG_RB_SIZE 203 #define UVD_JPEG_RB_SIZE__RB_SIZE__SHIFT 0x4 204 #define UVD_JPEG_RB_SIZE__RB_SIZE_MASK 0x3FFFFFF0L 205 //UVD_JPEG_ADDR_CONFIG 206 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 207 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 208 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 209 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 210 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 211 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 212 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 213 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 214 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 215 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 216 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 217 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 218 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 219 #define UVD_JPEG_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 220 #define UVD_JPEG_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 221 #define UVD_JPEG_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 222 #define UVD_JPEG_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 223 #define UVD_JPEG_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 224 #define UVD_JPEG_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 225 #define UVD_JPEG_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 226 #define UVD_JPEG_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 227 #define UVD_JPEG_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 228 #define UVD_JPEG_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 229 #define UVD_JPEG_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 230 #define UVD_JPEG_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 231 #define UVD_JPEG_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 232 //UVD_JPEG_GPCOM_CMD 233 #define UVD_JPEG_GPCOM_CMD__CMD_SEND__SHIFT 0x0 234 #define UVD_JPEG_GPCOM_CMD__CMD__SHIFT 0x1 235 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE__SHIFT 0x1f 236 #define UVD_JPEG_GPCOM_CMD__CMD_SEND_MASK 0x00000001L 237 #define UVD_JPEG_GPCOM_CMD__CMD_MASK 0x7FFFFFFEL 238 #define UVD_JPEG_GPCOM_CMD__CMD_SOURCE_MASK 0x80000000L 239 //UVD_JPEG_GPCOM_DATA0 240 #define UVD_JPEG_GPCOM_DATA0__DATA0__SHIFT 0x0 241 #define UVD_JPEG_GPCOM_DATA0__DATA0_MASK 0xFFFFFFFFL 242 //UVD_JPEG_GPCOM_DATA1 243 #define UVD_JPEG_GPCOM_DATA1__DATA1__SHIFT 0x0 244 #define UVD_JPEG_GPCOM_DATA1__DATA1_MASK 0xFFFFFFFFL 245 //UVD_JPEG_JRB_BASE_LO 246 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO__SHIFT 0x6 247 #define UVD_JPEG_JRB_BASE_LO__JRB_BASE_LO_MASK 0xFFFFFFC0L 248 //UVD_JPEG_JRB_BASE_HI 249 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI__SHIFT 0x0 250 #define UVD_JPEG_JRB_BASE_HI__JRB_BASE_HI_MASK 0xFFFFFFFFL 251 //UVD_JPEG_JRB_SIZE 252 #define UVD_JPEG_JRB_SIZE__JRB_SIZE__SHIFT 0x4 253 #define UVD_JPEG_JRB_SIZE__JRB_SIZE_MASK 0x007FFFF0L 254 //UVD_JPEG_JRB_RPTR 255 #define UVD_JPEG_JRB_RPTR__JRB_RPTR__SHIFT 0x4 256 #define UVD_JPEG_JRB_RPTR__JRB_RPTR_MASK 0x007FFFF0L 257 //UVD_JPEG_JRB_WPTR 258 #define UVD_JPEG_JRB_WPTR__JRB_WPTR__SHIFT 0x4 259 #define UVD_JPEG_JRB_WPTR__JRB_WPTR_MASK 0x007FFFF0L 260 //UVD_JPEG_UV_ADDR_CONFIG 261 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 262 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 263 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 264 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 265 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 266 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 267 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 268 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 269 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 270 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 271 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 272 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 273 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 274 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 275 #define UVD_JPEG_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 276 #define UVD_JPEG_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 277 #define UVD_JPEG_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 278 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 279 #define UVD_JPEG_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 280 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 281 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 282 #define UVD_JPEG_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 283 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 284 #define UVD_JPEG_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 285 #define UVD_JPEG_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 286 #define UVD_JPEG_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 287 //UVD_SEMA_ADDR_LOW 288 #define UVD_SEMA_ADDR_LOW__ADDR_26_3__SHIFT 0x0 289 #define UVD_SEMA_ADDR_LOW__ADDR_26_3_MASK 0x00FFFFFFL 290 //UVD_SEMA_ADDR_HIGH 291 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27__SHIFT 0x0 292 #define UVD_SEMA_ADDR_HIGH__ADDR_47_27_MASK 0x001FFFFFL 293 //UVD_SEMA_CMD 294 #define UVD_SEMA_CMD__REQ_CMD__SHIFT 0x0 295 #define UVD_SEMA_CMD__WR_PHASE__SHIFT 0x4 296 #define UVD_SEMA_CMD__MODE__SHIFT 0x6 297 #define UVD_SEMA_CMD__VMID_EN__SHIFT 0x7 298 #define UVD_SEMA_CMD__VMID__SHIFT 0x8 299 #define UVD_SEMA_CMD__REQ_CMD_MASK 0x0000000FL 300 #define UVD_SEMA_CMD__WR_PHASE_MASK 0x00000030L 301 #define UVD_SEMA_CMD__MODE_MASK 0x00000040L 302 #define UVD_SEMA_CMD__VMID_EN_MASK 0x00000080L 303 #define UVD_SEMA_CMD__VMID_MASK 0x00000F00L 304 //UVD_GPCOM_VCPU_CMD 305 #define UVD_GPCOM_VCPU_CMD__CMD_SEND__SHIFT 0x0 306 #define UVD_GPCOM_VCPU_CMD__CMD__SHIFT 0x1 307 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE__SHIFT 0x1f 308 #define UVD_GPCOM_VCPU_CMD__CMD_SEND_MASK 0x00000001L 309 #define UVD_GPCOM_VCPU_CMD__CMD_MASK 0x7FFFFFFEL 310 #define UVD_GPCOM_VCPU_CMD__CMD_SOURCE_MASK 0x80000000L 311 //UVD_GPCOM_VCPU_DATA0 312 #define UVD_GPCOM_VCPU_DATA0__DATA0__SHIFT 0x0 313 #define UVD_GPCOM_VCPU_DATA0__DATA0_MASK 0xFFFFFFFFL 314 //UVD_GPCOM_VCPU_DATA1 315 #define UVD_GPCOM_VCPU_DATA1__DATA1__SHIFT 0x0 316 #define UVD_GPCOM_VCPU_DATA1__DATA1_MASK 0xFFFFFFFFL 317 //UVD_ENGINE_CNTL 318 #define UVD_ENGINE_CNTL__ENGINE_START_MASK 0x1 319 #define UVD_ENGINE_CNTL__ENGINE_START__SHIFT 0x0 320 #define UVD_ENGINE_CNTL__ENGINE_START_MODE_MASK 0x2 321 #define UVD_ENGINE_CNTL__ENGINE_START_MODE__SHIFT 0x1 322 //UVD_UDEC_DBW_UV_ADDR_CONFIG 323 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 324 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 325 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 326 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 327 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 328 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 329 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 330 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 331 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 332 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 333 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 334 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 335 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 336 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 337 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 338 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 339 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 340 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 341 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 342 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 343 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 344 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 345 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 346 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 347 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 348 #define UVD_UDEC_DBW_UV_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 349 //UVD_UDEC_ADDR_CONFIG 350 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 351 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 352 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 353 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 354 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 355 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 356 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 357 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 358 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 359 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 360 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 361 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 362 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 363 #define UVD_UDEC_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 364 #define UVD_UDEC_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 365 #define UVD_UDEC_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 366 #define UVD_UDEC_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 367 #define UVD_UDEC_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 368 #define UVD_UDEC_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 369 #define UVD_UDEC_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 370 #define UVD_UDEC_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 371 #define UVD_UDEC_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 372 #define UVD_UDEC_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 373 #define UVD_UDEC_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 374 #define UVD_UDEC_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 375 #define UVD_UDEC_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 376 //UVD_UDEC_DB_ADDR_CONFIG 377 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 378 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 379 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 380 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 381 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 382 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 383 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 384 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 385 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 386 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 387 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 388 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 389 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 390 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 391 #define UVD_UDEC_DB_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 392 #define UVD_UDEC_DB_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 393 #define UVD_UDEC_DB_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 394 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 395 #define UVD_UDEC_DB_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 396 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 397 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 398 #define UVD_UDEC_DB_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 399 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 400 #define UVD_UDEC_DB_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 401 #define UVD_UDEC_DB_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 402 #define UVD_UDEC_DB_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 403 //UVD_UDEC_DBW_ADDR_CONFIG 404 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES__SHIFT 0x0 405 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE__SHIFT 0x3 406 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS__SHIFT 0x6 407 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE__SHIFT 0x8 408 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS__SHIFT 0xc 409 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE__SHIFT 0x10 410 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES__SHIFT 0x13 411 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS__SHIFT 0x15 412 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE__SHIFT 0x18 413 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE__SHIFT 0x1a 414 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE__SHIFT 0x1c 415 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES__SHIFT 0x1e 416 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE__SHIFT 0x1f 417 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_PIPES_MASK 0x00000007L 418 #define UVD_UDEC_DBW_ADDR_CONFIG__PIPE_INTERLEAVE_SIZE_MASK 0x00000038L 419 #define UVD_UDEC_DBW_ADDR_CONFIG__MAX_COMPRESSED_FRAGS_MASK 0x000000C0L 420 #define UVD_UDEC_DBW_ADDR_CONFIG__BANK_INTERLEAVE_SIZE_MASK 0x00000700L 421 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_BANKS_MASK 0x00007000L 422 #define UVD_UDEC_DBW_ADDR_CONFIG__SHADER_ENGINE_TILE_SIZE_MASK 0x00070000L 423 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_SHADER_ENGINES_MASK 0x00180000L 424 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_GPUS_MASK 0x00E00000L 425 #define UVD_UDEC_DBW_ADDR_CONFIG__MULTI_GPU_TILE_SIZE_MASK 0x03000000L 426 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_RB_PER_SE_MASK 0x0C000000L 427 #define UVD_UDEC_DBW_ADDR_CONFIG__ROW_SIZE_MASK 0x30000000L 428 #define UVD_UDEC_DBW_ADDR_CONFIG__NUM_LOWER_PIPES_MASK 0x40000000L 429 #define UVD_UDEC_DBW_ADDR_CONFIG__SE_ENABLE_MASK 0x80000000L 430 //UVD_SUVD_CGC_GATE 431 #define UVD_SUVD_CGC_GATE__SRE__SHIFT 0x0 432 #define UVD_SUVD_CGC_GATE__SIT__SHIFT 0x1 433 #define UVD_SUVD_CGC_GATE__SMP__SHIFT 0x2 434 #define UVD_SUVD_CGC_GATE__SCM__SHIFT 0x3 435 #define UVD_SUVD_CGC_GATE__SDB__SHIFT 0x4 436 #define UVD_SUVD_CGC_GATE__SRE_H264__SHIFT 0x5 437 #define UVD_SUVD_CGC_GATE__SRE_HEVC__SHIFT 0x6 438 #define UVD_SUVD_CGC_GATE__SIT_H264__SHIFT 0x7 439 #define UVD_SUVD_CGC_GATE__SIT_HEVC__SHIFT 0x8 440 #define UVD_SUVD_CGC_GATE__SCM_H264__SHIFT 0x9 441 #define UVD_SUVD_CGC_GATE__SCM_HEVC__SHIFT 0xa 442 #define UVD_SUVD_CGC_GATE__SDB_H264__SHIFT 0xb 443 #define UVD_SUVD_CGC_GATE__SDB_HEVC__SHIFT 0xc 444 #define UVD_SUVD_CGC_GATE__SCLR__SHIFT 0xd 445 #define UVD_SUVD_CGC_GATE__UVD_SC__SHIFT 0xe 446 #define UVD_SUVD_CGC_GATE__ENT__SHIFT 0xf 447 #define UVD_SUVD_CGC_GATE__IME__SHIFT 0x10 448 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC__SHIFT 0x11 449 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC__SHIFT 0x12 450 #define UVD_SUVD_CGC_GATE__SITE__SHIFT 0x13 451 #define UVD_SUVD_CGC_GATE__SRE_VP9__SHIFT 0x14 452 #define UVD_SUVD_CGC_GATE__SCM_VP9__SHIFT 0x15 453 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC__SHIFT 0x16 454 #define UVD_SUVD_CGC_GATE__SDB_VP9__SHIFT 0x17 455 #define UVD_SUVD_CGC_GATE__IME_HEVC__SHIFT 0x18 456 #define UVD_SUVD_CGC_GATE__SRE_MASK 0x00000001L 457 #define UVD_SUVD_CGC_GATE__SIT_MASK 0x00000002L 458 #define UVD_SUVD_CGC_GATE__SMP_MASK 0x00000004L 459 #define UVD_SUVD_CGC_GATE__SCM_MASK 0x00000008L 460 #define UVD_SUVD_CGC_GATE__SDB_MASK 0x00000010L 461 #define UVD_SUVD_CGC_GATE__SRE_H264_MASK 0x00000020L 462 #define UVD_SUVD_CGC_GATE__SRE_HEVC_MASK 0x00000040L 463 #define UVD_SUVD_CGC_GATE__SIT_H264_MASK 0x00000080L 464 #define UVD_SUVD_CGC_GATE__SIT_HEVC_MASK 0x00000100L 465 #define UVD_SUVD_CGC_GATE__SCM_H264_MASK 0x00000200L 466 #define UVD_SUVD_CGC_GATE__SCM_HEVC_MASK 0x00000400L 467 #define UVD_SUVD_CGC_GATE__SDB_H264_MASK 0x00000800L 468 #define UVD_SUVD_CGC_GATE__SDB_HEVC_MASK 0x00001000L 469 #define UVD_SUVD_CGC_GATE__SCLR_MASK 0x00002000L 470 #define UVD_SUVD_CGC_GATE__UVD_SC_MASK 0x00004000L 471 #define UVD_SUVD_CGC_GATE__ENT_MASK 0x00008000L 472 #define UVD_SUVD_CGC_GATE__IME_MASK 0x00010000L 473 #define UVD_SUVD_CGC_GATE__SIT_HEVC_DEC_MASK 0x00020000L 474 #define UVD_SUVD_CGC_GATE__SIT_HEVC_ENC_MASK 0x00040000L 475 #define UVD_SUVD_CGC_GATE__SITE_MASK 0x00080000L 476 #define UVD_SUVD_CGC_GATE__SRE_VP9_MASK 0x00100000L 477 #define UVD_SUVD_CGC_GATE__SCM_VP9_MASK 0x00200000L 478 #define UVD_SUVD_CGC_GATE__SIT_VP9_DEC_MASK 0x00400000L 479 #define UVD_SUVD_CGC_GATE__SDB_VP9_MASK 0x00800000L 480 #define UVD_SUVD_CGC_GATE__IME_HEVC_MASK 0x01000000L 481 //UVD_SUVD_CGC_STATUS 482 #define UVD_SUVD_CGC_STATUS__SRE_VCLK__SHIFT 0x0 483 #define UVD_SUVD_CGC_STATUS__SRE_DCLK__SHIFT 0x1 484 #define UVD_SUVD_CGC_STATUS__SIT_DCLK__SHIFT 0x2 485 #define UVD_SUVD_CGC_STATUS__SMP_DCLK__SHIFT 0x3 486 #define UVD_SUVD_CGC_STATUS__SCM_DCLK__SHIFT 0x4 487 #define UVD_SUVD_CGC_STATUS__SDB_DCLK__SHIFT 0x5 488 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK__SHIFT 0x6 489 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK__SHIFT 0x7 490 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK__SHIFT 0x8 491 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK__SHIFT 0x9 492 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK__SHIFT 0xa 493 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK__SHIFT 0xb 494 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK__SHIFT 0xc 495 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK__SHIFT 0xd 496 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK__SHIFT 0xe 497 #define UVD_SUVD_CGC_STATUS__UVD_SC__SHIFT 0xf 498 #define UVD_SUVD_CGC_STATUS__ENT_DCLK__SHIFT 0x10 499 #define UVD_SUVD_CGC_STATUS__IME_DCLK__SHIFT 0x11 500 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK__SHIFT 0x12 501 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK__SHIFT 0x13 502 #define UVD_SUVD_CGC_STATUS__SITE_DCLK__SHIFT 0x14 503 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK__SHIFT 0x15 504 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK__SHIFT 0x16 505 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK__SHIFT 0x17 506 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK__SHIFT 0x18 507 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK__SHIFT 0x19 508 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK__SHIFT 0x1a 509 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK__SHIFT 0x1b 510 #define UVD_SUVD_CGC_STATUS__SRE_VCLK_MASK 0x00000001L 511 #define UVD_SUVD_CGC_STATUS__SRE_DCLK_MASK 0x00000002L 512 #define UVD_SUVD_CGC_STATUS__SIT_DCLK_MASK 0x00000004L 513 #define UVD_SUVD_CGC_STATUS__SMP_DCLK_MASK 0x00000008L 514 #define UVD_SUVD_CGC_STATUS__SCM_DCLK_MASK 0x00000010L 515 #define UVD_SUVD_CGC_STATUS__SDB_DCLK_MASK 0x00000020L 516 #define UVD_SUVD_CGC_STATUS__SRE_H264_VCLK_MASK 0x00000040L 517 #define UVD_SUVD_CGC_STATUS__SRE_HEVC_VCLK_MASK 0x00000080L 518 #define UVD_SUVD_CGC_STATUS__SIT_H264_DCLK_MASK 0x00000100L 519 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DCLK_MASK 0x00000200L 520 #define UVD_SUVD_CGC_STATUS__SCM_H264_DCLK_MASK 0x00000400L 521 #define UVD_SUVD_CGC_STATUS__SCM_HEVC_DCLK_MASK 0x00000800L 522 #define UVD_SUVD_CGC_STATUS__SDB_H264_DCLK_MASK 0x00001000L 523 #define UVD_SUVD_CGC_STATUS__SDB_HEVC_DCLK_MASK 0x00002000L 524 #define UVD_SUVD_CGC_STATUS__SCLR_DCLK_MASK 0x00004000L 525 #define UVD_SUVD_CGC_STATUS__UVD_SC_MASK 0x00008000L 526 #define UVD_SUVD_CGC_STATUS__ENT_DCLK_MASK 0x00010000L 527 #define UVD_SUVD_CGC_STATUS__IME_DCLK_MASK 0x00020000L 528 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_DEC_DCLK_MASK 0x00040000L 529 #define UVD_SUVD_CGC_STATUS__SIT_HEVC_ENC_DCLK_MASK 0x00080000L 530 #define UVD_SUVD_CGC_STATUS__SITE_DCLK_MASK 0x00100000L 531 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_DCLK_MASK 0x00200000L 532 #define UVD_SUVD_CGC_STATUS__SITE_HEVC_ENC_DCLK_MASK 0x00400000L 533 #define UVD_SUVD_CGC_STATUS__SRE_VP9_VCLK_MASK 0x00800000L 534 #define UVD_SUVD_CGC_STATUS__SCM_VP9_VCLK_MASK 0x01000000L 535 #define UVD_SUVD_CGC_STATUS__SIT_VP9_DEC_DCLK_MASK 0x02000000L 536 #define UVD_SUVD_CGC_STATUS__SDB_VP9_DCLK_MASK 0x04000000L 537 #define UVD_SUVD_CGC_STATUS__IME_HEVC_DCLK_MASK 0x08000000L 538 //UVD_SUVD_CGC_CTRL 539 #define UVD_SUVD_CGC_CTRL__SRE_MODE__SHIFT 0x0 540 #define UVD_SUVD_CGC_CTRL__SIT_MODE__SHIFT 0x1 541 #define UVD_SUVD_CGC_CTRL__SMP_MODE__SHIFT 0x2 542 #define UVD_SUVD_CGC_CTRL__SCM_MODE__SHIFT 0x3 543 #define UVD_SUVD_CGC_CTRL__SDB_MODE__SHIFT 0x4 544 #define UVD_SUVD_CGC_CTRL__SCLR_MODE__SHIFT 0x5 545 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE__SHIFT 0x6 546 #define UVD_SUVD_CGC_CTRL__ENT_MODE__SHIFT 0x7 547 #define UVD_SUVD_CGC_CTRL__IME_MODE__SHIFT 0x8 548 #define UVD_SUVD_CGC_CTRL__SITE_MODE__SHIFT 0x9 549 #define UVD_SUVD_CGC_CTRL__SRE_MODE_MASK 0x00000001L 550 #define UVD_SUVD_CGC_CTRL__SIT_MODE_MASK 0x00000002L 551 #define UVD_SUVD_CGC_CTRL__SMP_MODE_MASK 0x00000004L 552 #define UVD_SUVD_CGC_CTRL__SCM_MODE_MASK 0x00000008L 553 #define UVD_SUVD_CGC_CTRL__SDB_MODE_MASK 0x00000010L 554 #define UVD_SUVD_CGC_CTRL__SCLR_MODE_MASK 0x00000020L 555 #define UVD_SUVD_CGC_CTRL__UVD_SC_MODE_MASK 0x00000040L 556 #define UVD_SUVD_CGC_CTRL__ENT_MODE_MASK 0x00000080L 557 #define UVD_SUVD_CGC_CTRL__IME_MODE_MASK 0x00000100L 558 #define UVD_SUVD_CGC_CTRL__SITE_MODE_MASK 0x00000200L 559 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW 560 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 561 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 562 //UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH 563 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 564 #define UVD_LMI_VCPU_CACHE1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 565 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW 566 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 567 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 568 //UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH 569 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 570 #define UVD_LMI_VCPU_CACHE2_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 571 //UVD_NO_OP 572 #define UVD_NO_OP__NO_OP__SHIFT 0x0 573 #define UVD_NO_OP__NO_OP_MASK 0xFFFFFFFFL 574 //UVD_VERSION 575 #define UVD_VERSION__MINOR_VERSION__SHIFT 0x0 576 #define UVD_VERSION__MAJOR_VERSION__SHIFT 0x10 577 #define UVD_VERSION__MINOR_VERSION_MASK 0x0000FFFFL 578 #define UVD_VERSION__MAJOR_VERSION_MASK 0xFFFF0000L 579 //UVD_GP_SCRATCH8 580 #define UVD_GP_SCRATCH8__DATA__SHIFT 0x0 581 #define UVD_GP_SCRATCH8__DATA_MASK 0xFFFFFFFFL 582 //UVD_GP_SCRATCH9 583 #define UVD_GP_SCRATCH9__DATA__SHIFT 0x0 584 #define UVD_GP_SCRATCH9__DATA_MASK 0xFFFFFFFFL 585 //UVD_GP_SCRATCH10 586 #define UVD_GP_SCRATCH10__DATA__SHIFT 0x0 587 #define UVD_GP_SCRATCH10__DATA_MASK 0xFFFFFFFFL 588 //UVD_GP_SCRATCH11 589 #define UVD_GP_SCRATCH11__DATA__SHIFT 0x0 590 #define UVD_GP_SCRATCH11__DATA_MASK 0xFFFFFFFFL 591 //UVD_GP_SCRATCH12 592 #define UVD_GP_SCRATCH12__DATA__SHIFT 0x0 593 #define UVD_GP_SCRATCH12__DATA_MASK 0xFFFFFFFFL 594 //UVD_GP_SCRATCH13 595 #define UVD_GP_SCRATCH13__DATA__SHIFT 0x0 596 #define UVD_GP_SCRATCH13__DATA_MASK 0xFFFFFFFFL 597 //UVD_GP_SCRATCH14 598 #define UVD_GP_SCRATCH14__DATA__SHIFT 0x0 599 #define UVD_GP_SCRATCH14__DATA_MASK 0xFFFFFFFFL 600 //UVD_GP_SCRATCH15 601 #define UVD_GP_SCRATCH15__DATA__SHIFT 0x0 602 #define UVD_GP_SCRATCH15__DATA_MASK 0xFFFFFFFFL 603 //UVD_GP_SCRATCH16 604 #define UVD_GP_SCRATCH16__DATA__SHIFT 0x0 605 #define UVD_GP_SCRATCH16__DATA_MASK 0xFFFFFFFFL 606 //UVD_GP_SCRATCH17 607 #define UVD_GP_SCRATCH17__DATA__SHIFT 0x0 608 #define UVD_GP_SCRATCH17__DATA_MASK 0xFFFFFFFFL 609 //UVD_GP_SCRATCH18 610 #define UVD_GP_SCRATCH18__DATA__SHIFT 0x0 611 #define UVD_GP_SCRATCH18__DATA_MASK 0xFFFFFFFFL 612 //UVD_GP_SCRATCH19 613 #define UVD_GP_SCRATCH19__DATA__SHIFT 0x0 614 #define UVD_GP_SCRATCH19__DATA_MASK 0xFFFFFFFFL 615 //UVD_GP_SCRATCH20 616 #define UVD_GP_SCRATCH20__DATA__SHIFT 0x0 617 #define UVD_GP_SCRATCH20__DATA_MASK 0xFFFFFFFFL 618 //UVD_GP_SCRATCH21 619 #define UVD_GP_SCRATCH21__DATA__SHIFT 0x0 620 #define UVD_GP_SCRATCH21__DATA_MASK 0xFFFFFFFFL 621 //UVD_GP_SCRATCH22 622 #define UVD_GP_SCRATCH22__DATA__SHIFT 0x0 623 #define UVD_GP_SCRATCH22__DATA_MASK 0xFFFFFFFFL 624 //UVD_GP_SCRATCH23 625 #define UVD_GP_SCRATCH23__DATA__SHIFT 0x0 626 #define UVD_GP_SCRATCH23__DATA_MASK 0xFFFFFFFFL 627 //UVD_RB_BASE_LO2 628 #define UVD_RB_BASE_LO2__RB_BASE_LO__SHIFT 0x6 629 #define UVD_RB_BASE_LO2__RB_BASE_LO_MASK 0xFFFFFFC0L 630 //UVD_RB_BASE_HI2 631 #define UVD_RB_BASE_HI2__RB_BASE_HI__SHIFT 0x0 632 #define UVD_RB_BASE_HI2__RB_BASE_HI_MASK 0xFFFFFFFFL 633 //UVD_RB_SIZE2 634 #define UVD_RB_SIZE2__RB_SIZE__SHIFT 0x4 635 #define UVD_RB_SIZE2__RB_SIZE_MASK 0x007FFFF0L 636 //UVD_RB_RPTR2 637 #define UVD_RB_RPTR2__RB_RPTR__SHIFT 0x4 638 #define UVD_RB_RPTR2__RB_RPTR_MASK 0x007FFFF0L 639 //UVD_RB_WPTR2 640 #define UVD_RB_WPTR2__RB_WPTR__SHIFT 0x4 641 #define UVD_RB_WPTR2__RB_WPTR_MASK 0x007FFFF0L 642 //UVD_RB_BASE_LO 643 #define UVD_RB_BASE_LO__RB_BASE_LO__SHIFT 0x6 644 #define UVD_RB_BASE_LO__RB_BASE_LO_MASK 0xFFFFFFC0L 645 //UVD_RB_BASE_HI 646 #define UVD_RB_BASE_HI__RB_BASE_HI__SHIFT 0x0 647 #define UVD_RB_BASE_HI__RB_BASE_HI_MASK 0xFFFFFFFFL 648 //UVD_RB_SIZE 649 #define UVD_RB_SIZE__RB_SIZE__SHIFT 0x4 650 #define UVD_RB_SIZE__RB_SIZE_MASK 0x007FFFF0L 651 //UVD_RB_RPTR 652 #define UVD_RB_RPTR__RB_RPTR__SHIFT 0x4 653 #define UVD_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 654 //UVD_RB_WPTR 655 #define UVD_RB_WPTR__RB_WPTR__SHIFT 0x4 656 #define UVD_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 657 //UVD_RB_WPTR4 658 #define UVD_RB_WPTR4__RB_WPTR__SHIFT 0x4 659 #define UVD_RB_WPTR4__RB_WPTR_MASK 0x007FFFF0L 660 //UVD_JRBC_RB_RPTR 661 #define UVD_JRBC_RB_RPTR__RB_RPTR__SHIFT 0x4 662 #define UVD_JRBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 663 //UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH 664 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 665 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 666 //UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW 667 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 668 #define UVD_LMI_VCPU_CACHE_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 669 //UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH 670 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 671 #define UVD_LMI_VCPU_NC1_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 672 //UVD_LMI_VCPU_NC1_64BIT_BAR_LOW 673 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 674 #define UVD_LMI_VCPU_NC1_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 675 //UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH 676 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 677 #define UVD_LMI_VCPU_NC0_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 678 //UVD_LMI_VCPU_NC0_64BIT_BAR_LOW 679 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 680 #define UVD_LMI_VCPU_NC0_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 681 //UVD_LMI_LBSI_64BIT_BAR_HIGH 682 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 683 #define UVD_LMI_LBSI_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 684 //UVD_LMI_LBSI_64BIT_BAR_LOW 685 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 686 #define UVD_LMI_LBSI_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 687 //UVD_LMI_RBC_IB_64BIT_BAR_HIGH 688 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 689 #define UVD_LMI_RBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 690 //UVD_LMI_RBC_IB_64BIT_BAR_LOW 691 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 692 #define UVD_LMI_RBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 693 //UVD_LMI_RBC_RB_64BIT_BAR_HIGH 694 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 695 #define UVD_LMI_RBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 696 //UVD_LMI_RBC_RB_64BIT_BAR_LOW 697 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 698 #define UVD_LMI_RBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 699 700 701 // addressBlock: uvd_uvddec 702 //UVD_SEMA_CNTL 703 #define UVD_SEMA_CNTL__SEMAPHORE_EN__SHIFT 0x0 704 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS__SHIFT 0x1 705 #define UVD_SEMA_CNTL__SEMAPHORE_EN_MASK 0x00000001L 706 #define UVD_SEMA_CNTL__ADVANCED_MODE_DIS_MASK 0x00000002L 707 //UVD_LMI_JRBC_RB_64BIT_BAR_LOW 708 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 709 #define UVD_LMI_JRBC_RB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 710 //UVD_LMI_JRBC_RB_64BIT_BAR_HIGH 711 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 712 #define UVD_LMI_JRBC_RB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 713 //UVD_LMI_JRBC_IB_64BIT_BAR_LOW 714 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0__SHIFT 0x0 715 #define UVD_LMI_JRBC_IB_64BIT_BAR_LOW__BITS_31_0_MASK 0xFFFFFFFFL 716 //UVD_LMI_JRBC_IB_64BIT_BAR_HIGH 717 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32__SHIFT 0x0 718 #define UVD_LMI_JRBC_IB_64BIT_BAR_HIGH__BITS_63_32_MASK 0xFFFFFFFFL 719 //UVD_LMI_JRBC_IB_VMID 720 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID__SHIFT 0x0 721 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID__SHIFT 0x4 722 #define UVD_LMI_JRBC_IB_VMID__IB_WR_VMID_MASK 0x0000000FL 723 #define UVD_LMI_JRBC_IB_VMID__IB_RD_VMID_MASK 0x000000F0L 724 //UVD_JRBC_RB_WPTR 725 #define UVD_JRBC_RB_WPTR__RB_WPTR__SHIFT 0x4 726 #define UVD_JRBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 727 //UVD_JRBC_RB_CNTL 728 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x0 729 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1 730 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x4 731 #define UVD_JRBC_RB_CNTL__RB_NO_FETCH_MASK 0x00000001L 732 #define UVD_JRBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x00000002L 733 #define UVD_JRBC_RB_CNTL__RB_PRE_WRITE_TIMER_MASK 0x0007FFF0L 734 //UVD_JRBC_IB_SIZE 735 #define UVD_JRBC_IB_SIZE__IB_SIZE__SHIFT 0x4 736 #define UVD_JRBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 737 //UVD_JRBC_LMI_SWAP_CNTL 738 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 739 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 740 #define UVD_JRBC_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 741 #define UVD_JRBC_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 742 //UVD_JRBC_SOFT_RESET 743 #define UVD_JRBC_SOFT_RESET__RESET__SHIFT 0x0 744 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS__SHIFT 0x10 745 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS__SHIFT 0x11 746 #define UVD_JRBC_SOFT_RESET__RESET_MASK 0x00000001L 747 #define UVD_JRBC_SOFT_RESET__VCLK_RESET_STATUS_MASK 0x00010000L 748 #define UVD_JRBC_SOFT_RESET__SCLK_RESET_STATUS_MASK 0x00020000L 749 //UVD_JRBC_STATUS 750 #define UVD_JRBC_STATUS__RB_JOB_DONE__SHIFT 0x0 751 #define UVD_JRBC_STATUS__IB_JOB_DONE__SHIFT 0x1 752 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD__SHIFT 0x2 753 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT__SHIFT 0x3 754 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT__SHIFT 0x4 755 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT__SHIFT 0x5 756 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD__SHIFT 0x6 757 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT__SHIFT 0x7 758 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT__SHIFT 0x8 759 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT__SHIFT 0x9 760 #define UVD_JRBC_STATUS__RB_TRAP_STATUS__SHIFT 0xa 761 #define UVD_JRBC_STATUS__PREEMPT_STATUS__SHIFT 0xb 762 #define UVD_JRBC_STATUS__IB_TRAP_STATUS__SHIFT 0xc 763 #define UVD_JRBC_STATUS__INT_EN__SHIFT 0x10 764 #define UVD_JRBC_STATUS__INT_ACK__SHIFT 0x11 765 #define UVD_JRBC_STATUS__RB_JOB_DONE_MASK 0x00000001L 766 #define UVD_JRBC_STATUS__IB_JOB_DONE_MASK 0x00000002L 767 #define UVD_JRBC_STATUS__RB_ILLEGAL_CMD_MASK 0x00000004L 768 #define UVD_JRBC_STATUS__RB_COND_REG_RD_TIMEOUT_MASK 0x00000008L 769 #define UVD_JRBC_STATUS__RB_MEM_WR_TIMEOUT_MASK 0x00000010L 770 #define UVD_JRBC_STATUS__RB_MEM_RD_TIMEOUT_MASK 0x00000020L 771 #define UVD_JRBC_STATUS__IB_ILLEGAL_CMD_MASK 0x00000040L 772 #define UVD_JRBC_STATUS__IB_COND_REG_RD_TIMEOUT_MASK 0x00000080L 773 #define UVD_JRBC_STATUS__IB_MEM_WR_TIMEOUT_MASK 0x00000100L 774 #define UVD_JRBC_STATUS__IB_MEM_RD_TIMEOUT_MASK 0x00000200L 775 #define UVD_JRBC_STATUS__RB_TRAP_STATUS_MASK 0x00000400L 776 #define UVD_JRBC_STATUS__PREEMPT_STATUS_MASK 0x00000800L 777 #define UVD_JRBC_STATUS__IB_TRAP_STATUS_MASK 0x00001000L 778 #define UVD_JRBC_STATUS__INT_EN_MASK 0x00010000L 779 #define UVD_JRBC_STATUS__INT_ACK_MASK 0x00020000L 780 //UVD_RB_RPTR3 781 #define UVD_RB_RPTR3__RB_RPTR__SHIFT 0x4 782 #define UVD_RB_RPTR3__RB_RPTR_MASK 0x007FFFF0L 783 //UVD_RB_WPTR3 784 #define UVD_RB_WPTR3__RB_WPTR__SHIFT 0x4 785 #define UVD_RB_WPTR3__RB_WPTR_MASK 0x007FFFF0L 786 //UVD_RB_BASE_LO3 787 #define UVD_RB_BASE_LO3__RB_BASE_LO__SHIFT 0x6 788 #define UVD_RB_BASE_LO3__RB_BASE_LO_MASK 0xFFFFFFC0L 789 //UVD_RB_BASE_HI3 790 #define UVD_RB_BASE_HI3__RB_BASE_HI__SHIFT 0x0 791 #define UVD_RB_BASE_HI3__RB_BASE_HI_MASK 0xFFFFFFFFL 792 //UVD_RB_SIZE3 793 #define UVD_RB_SIZE3__RB_SIZE__SHIFT 0x4 794 #define UVD_RB_SIZE3__RB_SIZE_MASK 0x007FFFF0L 795 //JPEG_CGC_GATE 796 #define JPEG_CGC_GATE__JPEG__SHIFT 0x14 797 #define JPEG_CGC_GATE__JPEG2__SHIFT 0x15 798 #define JPEG_CGC_GATE__JPEG_MASK 0x00100000L 799 #define JPEG_CGC_GATE__JPEG2_MASK 0x00200000L 800 //UVD_CTX_INDEX 801 #define UVD_CTX_INDEX__INDEX__SHIFT 0x0 802 #define UVD_CTX_INDEX__INDEX_MASK 0x000001FFL 803 //UVD_CTX_DATA 804 #define UVD_CTX_DATA__DATA__SHIFT 0x0 805 #define UVD_CTX_DATA__DATA_MASK 0xFFFFFFFFL 806 //UVD_CGC_GATE 807 #define UVD_CGC_GATE__SYS__SHIFT 0x0 808 #define UVD_CGC_GATE__UDEC__SHIFT 0x1 809 #define UVD_CGC_GATE__MPEG2__SHIFT 0x2 810 #define UVD_CGC_GATE__REGS__SHIFT 0x3 811 #define UVD_CGC_GATE__RBC__SHIFT 0x4 812 #define UVD_CGC_GATE__LMI_MC__SHIFT 0x5 813 #define UVD_CGC_GATE__LMI_UMC__SHIFT 0x6 814 #define UVD_CGC_GATE__IDCT__SHIFT 0x7 815 #define UVD_CGC_GATE__MPRD__SHIFT 0x8 816 #define UVD_CGC_GATE__MPC__SHIFT 0x9 817 #define UVD_CGC_GATE__LBSI__SHIFT 0xa 818 #define UVD_CGC_GATE__LRBBM__SHIFT 0xb 819 #define UVD_CGC_GATE__UDEC_RE__SHIFT 0xc 820 #define UVD_CGC_GATE__UDEC_CM__SHIFT 0xd 821 #define UVD_CGC_GATE__UDEC_IT__SHIFT 0xe 822 #define UVD_CGC_GATE__UDEC_DB__SHIFT 0xf 823 #define UVD_CGC_GATE__UDEC_MP__SHIFT 0x10 824 #define UVD_CGC_GATE__WCB__SHIFT 0x11 825 #define UVD_CGC_GATE__VCPU__SHIFT 0x12 826 #define UVD_CGC_GATE__SCPU__SHIFT 0x13 827 #define UVD_CGC_GATE__SYS_MASK 0x00000001L 828 #define UVD_CGC_GATE__UDEC_MASK 0x00000002L 829 #define UVD_CGC_GATE__MPEG2_MASK 0x00000004L 830 #define UVD_CGC_GATE__REGS_MASK 0x00000008L 831 #define UVD_CGC_GATE__RBC_MASK 0x00000010L 832 #define UVD_CGC_GATE__LMI_MC_MASK 0x00000020L 833 #define UVD_CGC_GATE__LMI_UMC_MASK 0x00000040L 834 #define UVD_CGC_GATE__IDCT_MASK 0x00000080L 835 #define UVD_CGC_GATE__MPRD_MASK 0x00000100L 836 #define UVD_CGC_GATE__MPC_MASK 0x00000200L 837 #define UVD_CGC_GATE__LBSI_MASK 0x00000400L 838 #define UVD_CGC_GATE__LRBBM_MASK 0x00000800L 839 #define UVD_CGC_GATE__UDEC_RE_MASK 0x00001000L 840 #define UVD_CGC_GATE__UDEC_CM_MASK 0x00002000L 841 #define UVD_CGC_GATE__UDEC_IT_MASK 0x00004000L 842 #define UVD_CGC_GATE__UDEC_DB_MASK 0x00008000L 843 #define UVD_CGC_GATE__UDEC_MP_MASK 0x00010000L 844 #define UVD_CGC_GATE__WCB_MASK 0x00020000L 845 #define UVD_CGC_GATE__VCPU_MASK 0x00040000L 846 #define UVD_CGC_GATE__SCPU_MASK 0x00080000L 847 //UVD_CGC_STATUS 848 #define UVD_CGC_STATUS__SYS_SCLK__SHIFT 0x0 849 #define UVD_CGC_STATUS__SYS_DCLK__SHIFT 0x1 850 #define UVD_CGC_STATUS__SYS_VCLK__SHIFT 0x2 851 #define UVD_CGC_STATUS__UDEC_SCLK__SHIFT 0x3 852 #define UVD_CGC_STATUS__UDEC_DCLK__SHIFT 0x4 853 #define UVD_CGC_STATUS__UDEC_VCLK__SHIFT 0x5 854 #define UVD_CGC_STATUS__MPEG2_SCLK__SHIFT 0x6 855 #define UVD_CGC_STATUS__MPEG2_DCLK__SHIFT 0x7 856 #define UVD_CGC_STATUS__MPEG2_VCLK__SHIFT 0x8 857 #define UVD_CGC_STATUS__REGS_SCLK__SHIFT 0x9 858 #define UVD_CGC_STATUS__REGS_VCLK__SHIFT 0xa 859 #define UVD_CGC_STATUS__RBC_SCLK__SHIFT 0xb 860 #define UVD_CGC_STATUS__LMI_MC_SCLK__SHIFT 0xc 861 #define UVD_CGC_STATUS__LMI_UMC_SCLK__SHIFT 0xd 862 #define UVD_CGC_STATUS__IDCT_SCLK__SHIFT 0xe 863 #define UVD_CGC_STATUS__IDCT_VCLK__SHIFT 0xf 864 #define UVD_CGC_STATUS__MPRD_SCLK__SHIFT 0x10 865 #define UVD_CGC_STATUS__MPRD_DCLK__SHIFT 0x11 866 #define UVD_CGC_STATUS__MPRD_VCLK__SHIFT 0x12 867 #define UVD_CGC_STATUS__MPC_SCLK__SHIFT 0x13 868 #define UVD_CGC_STATUS__MPC_DCLK__SHIFT 0x14 869 #define UVD_CGC_STATUS__LBSI_SCLK__SHIFT 0x15 870 #define UVD_CGC_STATUS__LBSI_VCLK__SHIFT 0x16 871 #define UVD_CGC_STATUS__LRBBM_SCLK__SHIFT 0x17 872 #define UVD_CGC_STATUS__WCB_SCLK__SHIFT 0x18 873 #define UVD_CGC_STATUS__VCPU_SCLK__SHIFT 0x19 874 #define UVD_CGC_STATUS__VCPU_VCLK__SHIFT 0x1a 875 #define UVD_CGC_STATUS__SCPU_SCLK__SHIFT 0x1b 876 #define UVD_CGC_STATUS__SCPU_VCLK__SHIFT 0x1c 877 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE__SHIFT 0x1d 878 #define UVD_CGC_STATUS__JPEG_ACTIVE__SHIFT 0x1e 879 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE__SHIFT 0x1f 880 #define UVD_CGC_STATUS__SYS_SCLK_MASK 0x00000001L 881 #define UVD_CGC_STATUS__SYS_DCLK_MASK 0x00000002L 882 #define UVD_CGC_STATUS__SYS_VCLK_MASK 0x00000004L 883 #define UVD_CGC_STATUS__UDEC_SCLK_MASK 0x00000008L 884 #define UVD_CGC_STATUS__UDEC_DCLK_MASK 0x00000010L 885 #define UVD_CGC_STATUS__UDEC_VCLK_MASK 0x00000020L 886 #define UVD_CGC_STATUS__MPEG2_SCLK_MASK 0x00000040L 887 #define UVD_CGC_STATUS__MPEG2_DCLK_MASK 0x00000080L 888 #define UVD_CGC_STATUS__MPEG2_VCLK_MASK 0x00000100L 889 #define UVD_CGC_STATUS__REGS_SCLK_MASK 0x00000200L 890 #define UVD_CGC_STATUS__REGS_VCLK_MASK 0x00000400L 891 #define UVD_CGC_STATUS__RBC_SCLK_MASK 0x00000800L 892 #define UVD_CGC_STATUS__LMI_MC_SCLK_MASK 0x00001000L 893 #define UVD_CGC_STATUS__LMI_UMC_SCLK_MASK 0x00002000L 894 #define UVD_CGC_STATUS__IDCT_SCLK_MASK 0x00004000L 895 #define UVD_CGC_STATUS__IDCT_VCLK_MASK 0x00008000L 896 #define UVD_CGC_STATUS__MPRD_SCLK_MASK 0x00010000L 897 #define UVD_CGC_STATUS__MPRD_DCLK_MASK 0x00020000L 898 #define UVD_CGC_STATUS__MPRD_VCLK_MASK 0x00040000L 899 #define UVD_CGC_STATUS__MPC_SCLK_MASK 0x00080000L 900 #define UVD_CGC_STATUS__MPC_DCLK_MASK 0x00100000L 901 #define UVD_CGC_STATUS__LBSI_SCLK_MASK 0x00200000L 902 #define UVD_CGC_STATUS__LBSI_VCLK_MASK 0x00400000L 903 #define UVD_CGC_STATUS__LRBBM_SCLK_MASK 0x00800000L 904 #define UVD_CGC_STATUS__WCB_SCLK_MASK 0x01000000L 905 #define UVD_CGC_STATUS__VCPU_SCLK_MASK 0x02000000L 906 #define UVD_CGC_STATUS__VCPU_VCLK_MASK 0x04000000L 907 #define UVD_CGC_STATUS__SCPU_SCLK_MASK 0x08000000L 908 #define UVD_CGC_STATUS__SCPU_VCLK_MASK 0x10000000L 909 #define UVD_CGC_STATUS__ALL_ENC_ACTIVE_MASK 0x20000000L 910 #define UVD_CGC_STATUS__JPEG_ACTIVE_MASK 0x40000000L 911 #define UVD_CGC_STATUS__ALL_DEC_ACTIVE_MASK 0x80000000L 912 //UVD_CGC_CTRL 913 #define UVD_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 914 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 915 #define UVD_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 916 #define UVD_CGC_CTRL__UDEC_RE_MODE__SHIFT 0xb 917 #define UVD_CGC_CTRL__UDEC_CM_MODE__SHIFT 0xc 918 #define UVD_CGC_CTRL__UDEC_IT_MODE__SHIFT 0xd 919 #define UVD_CGC_CTRL__UDEC_DB_MODE__SHIFT 0xe 920 #define UVD_CGC_CTRL__UDEC_MP_MODE__SHIFT 0xf 921 #define UVD_CGC_CTRL__SYS_MODE__SHIFT 0x10 922 #define UVD_CGC_CTRL__UDEC_MODE__SHIFT 0x11 923 #define UVD_CGC_CTRL__MPEG2_MODE__SHIFT 0x12 924 #define UVD_CGC_CTRL__REGS_MODE__SHIFT 0x13 925 #define UVD_CGC_CTRL__RBC_MODE__SHIFT 0x14 926 #define UVD_CGC_CTRL__LMI_MC_MODE__SHIFT 0x15 927 #define UVD_CGC_CTRL__LMI_UMC_MODE__SHIFT 0x16 928 #define UVD_CGC_CTRL__IDCT_MODE__SHIFT 0x17 929 #define UVD_CGC_CTRL__MPRD_MODE__SHIFT 0x18 930 #define UVD_CGC_CTRL__MPC_MODE__SHIFT 0x19 931 #define UVD_CGC_CTRL__LBSI_MODE__SHIFT 0x1a 932 #define UVD_CGC_CTRL__LRBBM_MODE__SHIFT 0x1b 933 #define UVD_CGC_CTRL__WCB_MODE__SHIFT 0x1c 934 #define UVD_CGC_CTRL__VCPU_MODE__SHIFT 0x1d 935 #define UVD_CGC_CTRL__SCPU_MODE__SHIFT 0x1e 936 #define UVD_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 937 #define UVD_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 938 #define UVD_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 939 #define UVD_CGC_CTRL__UDEC_RE_MODE_MASK 0x00000800L 940 #define UVD_CGC_CTRL__UDEC_CM_MODE_MASK 0x00001000L 941 #define UVD_CGC_CTRL__UDEC_IT_MODE_MASK 0x00002000L 942 #define UVD_CGC_CTRL__UDEC_DB_MODE_MASK 0x00004000L 943 #define UVD_CGC_CTRL__UDEC_MP_MODE_MASK 0x00008000L 944 #define UVD_CGC_CTRL__SYS_MODE_MASK 0x00010000L 945 #define UVD_CGC_CTRL__UDEC_MODE_MASK 0x00020000L 946 #define UVD_CGC_CTRL__MPEG2_MODE_MASK 0x00040000L 947 #define UVD_CGC_CTRL__REGS_MODE_MASK 0x00080000L 948 #define UVD_CGC_CTRL__RBC_MODE_MASK 0x00100000L 949 #define UVD_CGC_CTRL__LMI_MC_MODE_MASK 0x00200000L 950 #define UVD_CGC_CTRL__LMI_UMC_MODE_MASK 0x00400000L 951 #define UVD_CGC_CTRL__IDCT_MODE_MASK 0x00800000L 952 #define UVD_CGC_CTRL__MPRD_MODE_MASK 0x01000000L 953 #define UVD_CGC_CTRL__MPC_MODE_MASK 0x02000000L 954 #define UVD_CGC_CTRL__LBSI_MODE_MASK 0x04000000L 955 #define UVD_CGC_CTRL__LRBBM_MODE_MASK 0x08000000L 956 #define UVD_CGC_CTRL__WCB_MODE_MASK 0x10000000L 957 #define UVD_CGC_CTRL__VCPU_MODE_MASK 0x20000000L 958 #define UVD_CGC_CTRL__SCPU_MODE_MASK 0x40000000L 959 //UVD_GP_SCRATCH0 960 #define UVD_GP_SCRATCH0__DATA__SHIFT 0x0 961 #define UVD_GP_SCRATCH0__DATA_MASK 0xFFFFFFFFL 962 //UVD_GP_SCRATCH1 963 #define UVD_GP_SCRATCH1__DATA__SHIFT 0x0 964 #define UVD_GP_SCRATCH1__DATA_MASK 0xFFFFFFFFL 965 //UVD_GP_SCRATCH2 966 #define UVD_GP_SCRATCH2__DATA__SHIFT 0x0 967 #define UVD_GP_SCRATCH2__DATA_MASK 0xFFFFFFFFL 968 //UVD_GP_SCRATCH3 969 #define UVD_GP_SCRATCH3__DATA__SHIFT 0x0 970 #define UVD_GP_SCRATCH3__DATA_MASK 0xFFFFFFFFL 971 //UVD_GP_SCRATCH4 972 #define UVD_GP_SCRATCH4__DATA__SHIFT 0x0 973 #define UVD_GP_SCRATCH4__DATA_MASK 0xFFFFFFFFL 974 //UVD_GP_SCRATCH5 975 #define UVD_GP_SCRATCH5__DATA__SHIFT 0x0 976 #define UVD_GP_SCRATCH5__DATA_MASK 0xFFFFFFFFL 977 //UVD_GP_SCRATCH6 978 #define UVD_GP_SCRATCH6__DATA__SHIFT 0x0 979 #define UVD_GP_SCRATCH6__DATA_MASK 0xFFFFFFFFL 980 //UVD_GP_SCRATCH7 981 #define UVD_GP_SCRATCH7__DATA__SHIFT 0x0 982 #define UVD_GP_SCRATCH7__DATA_MASK 0xFFFFFFFFL 983 //UVD_LMI_VCPU_CACHE_VMID 984 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID__SHIFT 0x0 985 #define UVD_LMI_VCPU_CACHE_VMID__VCPU_CACHE_VMID_MASK 0x0000000FL 986 //UVD_LMI_CTRL2 987 #define UVD_LMI_CTRL2__SPH_DIS__SHIFT 0x0 988 #define UVD_LMI_CTRL2__STALL_ARB__SHIFT 0x1 989 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT__SHIFT 0x2 990 #define UVD_LMI_CTRL2__MASK_UMC_URGENT__SHIFT 0x3 991 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS__SHIFT 0x7 992 #define UVD_LMI_CTRL2__STALL_ARB_UMC__SHIFT 0x8 993 #define UVD_LMI_CTRL2__MC_READ_ID_SEL__SHIFT 0x9 994 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL__SHIFT 0xb 995 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM__SHIFT 0x11 996 #define UVD_LMI_CTRL2__SPH_DIS_MASK 0x00000001L 997 #define UVD_LMI_CTRL2__STALL_ARB_MASK 0x00000002L 998 #define UVD_LMI_CTRL2__ASSERT_UMC_URGENT_MASK 0x00000004L 999 #define UVD_LMI_CTRL2__MASK_UMC_URGENT_MASK 0x00000008L 1000 #define UVD_LMI_CTRL2__DRCITF_BUBBLE_FIX_DIS_MASK 0x00000080L 1001 #define UVD_LMI_CTRL2__STALL_ARB_UMC_MASK 0x00000100L 1002 #define UVD_LMI_CTRL2__MC_READ_ID_SEL_MASK 0x00000600L 1003 #define UVD_LMI_CTRL2__MC_WRITE_ID_SEL_MASK 0x00001800L 1004 #define UVD_LMI_CTRL2__RE_OFLD_MIF_WR_REQ_NUM_MASK 0x01FE0000L 1005 //UVD_MASTINT_EN 1006 #define UVD_MASTINT_EN__OVERRUN_RST__SHIFT 0x0 1007 #define UVD_MASTINT_EN__VCPU_EN__SHIFT 0x1 1008 #define UVD_MASTINT_EN__SYS_EN__SHIFT 0x2 1009 #define UVD_MASTINT_EN__INT_OVERRUN__SHIFT 0x4 1010 #define UVD_MASTINT_EN__OVERRUN_RST_MASK 0x00000001L 1011 #define UVD_MASTINT_EN__VCPU_EN_MASK 0x00000002L 1012 #define UVD_MASTINT_EN__SYS_EN_MASK 0x00000004L 1013 #define UVD_MASTINT_EN__INT_OVERRUN_MASK 0x007FFFF0L 1014 //UVD_SYS_INT_EN 1015 #define UVD_SYS_INT_EN__UVD_JRBC_EN__SHIFT 0x4 1016 #define UVD_SYS_INT_EN__UVD_JRBC_EN_MASK 0x00000010L 1017 //JPEG_CGC_CTRL 1018 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE__SHIFT 0x0 1019 #define JPEG_CGC_CTRL__JPEG2_MODE__SHIFT 0x1 1020 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER__SHIFT 0x2 1021 #define JPEG_CGC_CTRL__CLK_OFF_DELAY__SHIFT 0x6 1022 #define JPEG_CGC_CTRL__JPEG_MODE__SHIFT 0x1f 1023 #define JPEG_CGC_CTRL__DYN_CLOCK_MODE_MASK 0x00000001L 1024 #define JPEG_CGC_CTRL__JPEG2_MODE_MASK 0x00000002L 1025 #define JPEG_CGC_CTRL__CLK_GATE_DLY_TIMER_MASK 0x0000003CL 1026 #define JPEG_CGC_CTRL__CLK_OFF_DELAY_MASK 0x000007C0L 1027 #define JPEG_CGC_CTRL__JPEG_MODE_MASK 0x80000000L 1028 //UVD_LMI_CTRL 1029 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER__SHIFT 0x0 1030 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN__SHIFT 0x8 1031 #define UVD_LMI_CTRL__REQ_MODE__SHIFT 0x9 1032 #define UVD_LMI_CTRL__ASSERT_MC_URGENT__SHIFT 0xb 1033 #define UVD_LMI_CTRL__MASK_MC_URGENT__SHIFT 0xc 1034 #define UVD_LMI_CTRL__DATA_COHERENCY_EN__SHIFT 0xd 1035 #define UVD_LMI_CTRL__CRC_RESET__SHIFT 0xe 1036 #define UVD_LMI_CTRL__CRC_SEL__SHIFT 0xf 1037 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN__SHIFT 0x15 1038 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN__SHIFT 0x16 1039 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN__SHIFT 0x17 1040 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN__SHIFT 0x18 1041 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN__SHIFT 0x19 1042 #define UVD_LMI_CTRL__RFU__SHIFT 0x1b 1043 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_MASK 0x000000FFL 1044 #define UVD_LMI_CTRL__WRITE_CLEAN_TIMER_EN_MASK 0x00000100L 1045 #define UVD_LMI_CTRL__REQ_MODE_MASK 0x00000200L 1046 #define UVD_LMI_CTRL__ASSERT_MC_URGENT_MASK 0x00000800L 1047 #define UVD_LMI_CTRL__MASK_MC_URGENT_MASK 0x00001000L 1048 #define UVD_LMI_CTRL__DATA_COHERENCY_EN_MASK 0x00002000L 1049 #define UVD_LMI_CTRL__CRC_RESET_MASK 0x00004000L 1050 #define UVD_LMI_CTRL__CRC_SEL_MASK 0x000F8000L 1051 #define UVD_LMI_CTRL__VCPU_DATA_COHERENCY_EN_MASK 0x00200000L 1052 #define UVD_LMI_CTRL__CM_DATA_COHERENCY_EN_MASK 0x00400000L 1053 #define UVD_LMI_CTRL__DB_DB_DATA_COHERENCY_EN_MASK 0x00800000L 1054 #define UVD_LMI_CTRL__DB_IT_DATA_COHERENCY_EN_MASK 0x01000000L 1055 #define UVD_LMI_CTRL__IT_IT_DATA_COHERENCY_EN_MASK 0x02000000L 1056 #define UVD_LMI_CTRL__RFU_MASK 0xF8000000L 1057 //UVD_LMI_STATUS 1058 #define UVD_LMI_STATUS__READ_CLEAN__SHIFT 0x0 1059 #define UVD_LMI_STATUS__WRITE_CLEAN__SHIFT 0x1 1060 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW__SHIFT 0x2 1061 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN__SHIFT 0x3 1062 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW__SHIFT 0x6 1063 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW__SHIFT 0x9 1064 #define UVD_LMI_STATUS__READ_CLEAN_MASK 0x00000001L 1065 #define UVD_LMI_STATUS__WRITE_CLEAN_MASK 0x00000002L 1066 #define UVD_LMI_STATUS__WRITE_CLEAN_RAW_MASK 0x00000004L 1067 #define UVD_LMI_STATUS__VCPU_LMI_WRITE_CLEAN_MASK 0x00000008L 1068 #define UVD_LMI_STATUS__UMC_WRITE_CLEAN_RAW_MASK 0x00000040L 1069 #define UVD_LMI_STATUS__UMC_READ_CLEAN_RAW_MASK 0x00000200L 1070 //UVD_LMI_SWAP_CNTL 1071 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP__SHIFT 0x0 1072 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP__SHIFT 0x2 1073 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP__SHIFT 0x4 1074 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP__SHIFT 0x6 1075 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP__SHIFT 0x8 1076 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP__SHIFT 0xa 1077 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP__SHIFT 0xc 1078 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP__SHIFT 0xe 1079 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP__SHIFT 0x10 1080 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP__SHIFT 0x12 1081 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP__SHIFT 0x14 1082 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP__SHIFT 0x16 1083 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP__SHIFT 0x18 1084 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP__SHIFT 0x1a 1085 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP__SHIFT 0x1c 1086 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP__SHIFT 0x1e 1087 #define UVD_LMI_SWAP_CNTL__RB_MC_SWAP_MASK 0x00000003L 1088 #define UVD_LMI_SWAP_CNTL__IB_MC_SWAP_MASK 0x0000000CL 1089 #define UVD_LMI_SWAP_CNTL__RB_RPTR_MC_SWAP_MASK 0x00000030L 1090 #define UVD_LMI_SWAP_CNTL__VCPU_R_MC_SWAP_MASK 0x000000C0L 1091 #define UVD_LMI_SWAP_CNTL__VCPU_W_MC_SWAP_MASK 0x00000300L 1092 #define UVD_LMI_SWAP_CNTL__CM_MC_SWAP_MASK 0x00000C00L 1093 #define UVD_LMI_SWAP_CNTL__IT_MC_SWAP_MASK 0x00003000L 1094 #define UVD_LMI_SWAP_CNTL__DB_R_MC_SWAP_MASK 0x0000C000L 1095 #define UVD_LMI_SWAP_CNTL__DB_W_MC_SWAP_MASK 0x00030000L 1096 #define UVD_LMI_SWAP_CNTL__CSM_MC_SWAP_MASK 0x000C0000L 1097 #define UVD_LMI_SWAP_CNTL__ACAP_MC_SWAP_MASK 0x00300000L 1098 #define UVD_LMI_SWAP_CNTL__MP_REF16_MC_SWAP_MASK 0x00C00000L 1099 #define UVD_LMI_SWAP_CNTL__DBW_MC_SWAP_MASK 0x03000000L 1100 #define UVD_LMI_SWAP_CNTL__RB_WR_MC_SWAP_MASK 0x0C000000L 1101 #define UVD_LMI_SWAP_CNTL__RE_MC_SWAP_MASK 0x30000000L 1102 #define UVD_LMI_SWAP_CNTL__MP_MC_SWAP_MASK 0xC0000000L 1103 //UVD_MPC_CNTL 1104 #define UVD_MPC_CNTL__REPLACEMENT_MODE__SHIFT 0x3 1105 #define UVD_MPC_CNTL__REPLACEMENT_MODE_MASK 0x00000038L 1106 //UVD_MPC_SET_MUXA0 1107 #define UVD_MPC_SET_MUXA0__VARA_0__SHIFT 0x0 1108 #define UVD_MPC_SET_MUXA0__VARA_1__SHIFT 0x6 1109 #define UVD_MPC_SET_MUXA0__VARA_2__SHIFT 0xc 1110 #define UVD_MPC_SET_MUXA0__VARA_3__SHIFT 0x12 1111 #define UVD_MPC_SET_MUXA0__VARA_4__SHIFT 0x18 1112 #define UVD_MPC_SET_MUXA0__VARA_0_MASK 0x0000003FL 1113 #define UVD_MPC_SET_MUXA0__VARA_1_MASK 0x00000FC0L 1114 #define UVD_MPC_SET_MUXA0__VARA_2_MASK 0x0003F000L 1115 #define UVD_MPC_SET_MUXA0__VARA_3_MASK 0x00FC0000L 1116 #define UVD_MPC_SET_MUXA0__VARA_4_MASK 0x3F000000L 1117 //UVD_MPC_SET_MUXA1 1118 #define UVD_MPC_SET_MUXA1__VARA_5__SHIFT 0x0 1119 #define UVD_MPC_SET_MUXA1__VARA_6__SHIFT 0x6 1120 #define UVD_MPC_SET_MUXA1__VARA_7__SHIFT 0xc 1121 #define UVD_MPC_SET_MUXA1__VARA_5_MASK 0x0000003FL 1122 #define UVD_MPC_SET_MUXA1__VARA_6_MASK 0x00000FC0L 1123 #define UVD_MPC_SET_MUXA1__VARA_7_MASK 0x0003F000L 1124 //UVD_MPC_SET_MUXB0 1125 #define UVD_MPC_SET_MUXB0__VARB_0__SHIFT 0x0 1126 #define UVD_MPC_SET_MUXB0__VARB_1__SHIFT 0x6 1127 #define UVD_MPC_SET_MUXB0__VARB_2__SHIFT 0xc 1128 #define UVD_MPC_SET_MUXB0__VARB_3__SHIFT 0x12 1129 #define UVD_MPC_SET_MUXB0__VARB_4__SHIFT 0x18 1130 #define UVD_MPC_SET_MUXB0__VARB_0_MASK 0x0000003FL 1131 #define UVD_MPC_SET_MUXB0__VARB_1_MASK 0x00000FC0L 1132 #define UVD_MPC_SET_MUXB0__VARB_2_MASK 0x0003F000L 1133 #define UVD_MPC_SET_MUXB0__VARB_3_MASK 0x00FC0000L 1134 #define UVD_MPC_SET_MUXB0__VARB_4_MASK 0x3F000000L 1135 //UVD_MPC_SET_MUXB1 1136 #define UVD_MPC_SET_MUXB1__VARB_5__SHIFT 0x0 1137 #define UVD_MPC_SET_MUXB1__VARB_6__SHIFT 0x6 1138 #define UVD_MPC_SET_MUXB1__VARB_7__SHIFT 0xc 1139 #define UVD_MPC_SET_MUXB1__VARB_5_MASK 0x0000003FL 1140 #define UVD_MPC_SET_MUXB1__VARB_6_MASK 0x00000FC0L 1141 #define UVD_MPC_SET_MUXB1__VARB_7_MASK 0x0003F000L 1142 //UVD_MPC_SET_MUX 1143 #define UVD_MPC_SET_MUX__SET_0__SHIFT 0x0 1144 #define UVD_MPC_SET_MUX__SET_1__SHIFT 0x3 1145 #define UVD_MPC_SET_MUX__SET_2__SHIFT 0x6 1146 #define UVD_MPC_SET_MUX__SET_0_MASK 0x00000007L 1147 #define UVD_MPC_SET_MUX__SET_1_MASK 0x00000038L 1148 #define UVD_MPC_SET_MUX__SET_2_MASK 0x000001C0L 1149 //UVD_MPC_SET_ALU 1150 #define UVD_MPC_SET_ALU__FUNCT__SHIFT 0x0 1151 #define UVD_MPC_SET_ALU__OPERAND__SHIFT 0x4 1152 #define UVD_MPC_SET_ALU__FUNCT_MASK 0x00000007L 1153 #define UVD_MPC_SET_ALU__OPERAND_MASK 0x00000FF0L 1154 //UVD_GPCOM_SYS_CMD 1155 #define UVD_GPCOM_SYS_CMD__CMD_SEND__SHIFT 0x0 1156 #define UVD_GPCOM_SYS_CMD__CMD__SHIFT 0x1 1157 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE__SHIFT 0x1f 1158 #define UVD_GPCOM_SYS_CMD__CMD_SEND_MASK 0x00000001L 1159 #define UVD_GPCOM_SYS_CMD__CMD_MASK 0x7FFFFFFEL 1160 #define UVD_GPCOM_SYS_CMD__CMD_SOURCE_MASK 0x80000000L 1161 //UVD_GPCOM_SYS_DATA0 1162 #define UVD_GPCOM_SYS_DATA0__DATA0__SHIFT 0x0 1163 #define UVD_GPCOM_SYS_DATA0__DATA0_MASK 0xFFFFFFFFL 1164 //UVD_GPCOM_SYS_DATA1 1165 #define UVD_GPCOM_SYS_DATA1__DATA1__SHIFT 0x0 1166 #define UVD_GPCOM_SYS_DATA1__DATA1_MASK 0xFFFFFFFFL 1167 //UVD_VCPU_CACHE_OFFSET0 1168 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0__SHIFT 0x0 1169 #define UVD_VCPU_CACHE_OFFSET0__CACHE_OFFSET0_MASK 0x001FFFFFL 1170 //UVD_VCPU_CACHE_SIZE0 1171 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0__SHIFT 0x0 1172 #define UVD_VCPU_CACHE_SIZE0__CACHE_SIZE0_MASK 0x001FFFFFL 1173 //UVD_VCPU_CACHE_OFFSET1 1174 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1__SHIFT 0x0 1175 #define UVD_VCPU_CACHE_OFFSET1__CACHE_OFFSET1_MASK 0x001FFFFFL 1176 //UVD_VCPU_CACHE_SIZE1 1177 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1__SHIFT 0x0 1178 #define UVD_VCPU_CACHE_SIZE1__CACHE_SIZE1_MASK 0x001FFFFFL 1179 //UVD_VCPU_CACHE_OFFSET2 1180 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2__SHIFT 0x0 1181 #define UVD_VCPU_CACHE_OFFSET2__CACHE_OFFSET2_MASK 0x001FFFFFL 1182 //UVD_VCPU_CACHE_SIZE2 1183 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2__SHIFT 0x0 1184 #define UVD_VCPU_CACHE_SIZE2__CACHE_SIZE2_MASK 0x001FFFFFL 1185 //UVD_VCPU_CNTL 1186 #define UVD_VCPU_CNTL__CLK_EN__SHIFT 0x9 1187 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP__SHIFT 0x11 1188 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL__SHIFT 0x14 1189 #define UVD_VCPU_CNTL__CLK_EN_MASK 0x00000200L 1190 #define UVD_VCPU_CNTL__MIF_WR_LOW_THRESHOLD_BP_MASK 0x00020000L 1191 #define UVD_VCPU_CNTL__PRB_TIMEOUT_VAL_MASK 0x0FF00000L 1192 //UVD_SOFT_RESET 1193 #define UVD_SOFT_RESET__RBC_SOFT_RESET__SHIFT 0x0 1194 #define UVD_SOFT_RESET__LBSI_SOFT_RESET__SHIFT 0x1 1195 #define UVD_SOFT_RESET__LMI_SOFT_RESET__SHIFT 0x2 1196 #define UVD_SOFT_RESET__VCPU_SOFT_RESET__SHIFT 0x3 1197 #define UVD_SOFT_RESET__UDEC_SOFT_RESET__SHIFT 0x4 1198 #define UVD_SOFT_RESET__CSM_SOFT_RESET__SHIFT 0x5 1199 #define UVD_SOFT_RESET__CXW_SOFT_RESET__SHIFT 0x6 1200 #define UVD_SOFT_RESET__TAP_SOFT_RESET__SHIFT 0x7 1201 #define UVD_SOFT_RESET__MPC_SOFT_RESET__SHIFT 0x8 1202 #define UVD_SOFT_RESET__IH_SOFT_RESET__SHIFT 0xa 1203 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET__SHIFT 0xd 1204 #define UVD_SOFT_RESET__SPH_SOFT_RESET__SHIFT 0xe 1205 #define UVD_SOFT_RESET__MIF_SOFT_RESET__SHIFT 0xf 1206 #define UVD_SOFT_RESET__LCM_SOFT_RESET__SHIFT 0x10 1207 #define UVD_SOFT_RESET__SUVD_SOFT_RESET__SHIFT 0x11 1208 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS__SHIFT 0x12 1209 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS__SHIFT 0x13 1210 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS__SHIFT 0x14 1211 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS__SHIFT 0x15 1212 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS__SHIFT 0x16 1213 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS__SHIFT 0x1a 1214 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS__SHIFT 0x1b 1215 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS__SHIFT 0x1c 1216 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS__SHIFT 0x1d 1217 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS__SHIFT 0x1e 1218 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS__SHIFT 0x1f 1219 #define UVD_SOFT_RESET__RBC_SOFT_RESET_MASK 0x00000001L 1220 #define UVD_SOFT_RESET__LBSI_SOFT_RESET_MASK 0x00000002L 1221 #define UVD_SOFT_RESET__LMI_SOFT_RESET_MASK 0x00000004L 1222 #define UVD_SOFT_RESET__VCPU_SOFT_RESET_MASK 0x00000008L 1223 #define UVD_SOFT_RESET__UDEC_SOFT_RESET_MASK 0x00000010L 1224 #define UVD_SOFT_RESET__CSM_SOFT_RESET_MASK 0x00000020L 1225 #define UVD_SOFT_RESET__CXW_SOFT_RESET_MASK 0x00000040L 1226 #define UVD_SOFT_RESET__TAP_SOFT_RESET_MASK 0x00000080L 1227 #define UVD_SOFT_RESET__MPC_SOFT_RESET_MASK 0x00000100L 1228 #define UVD_SOFT_RESET__IH_SOFT_RESET_MASK 0x00000400L 1229 #define UVD_SOFT_RESET__LMI_UMC_SOFT_RESET_MASK 0x00002000L 1230 #define UVD_SOFT_RESET__SPH_SOFT_RESET_MASK 0x00004000L 1231 #define UVD_SOFT_RESET__MIF_SOFT_RESET_MASK 0x00008000L 1232 #define UVD_SOFT_RESET__LCM_SOFT_RESET_MASK 0x00010000L 1233 #define UVD_SOFT_RESET__SUVD_SOFT_RESET_MASK 0x00020000L 1234 #define UVD_SOFT_RESET__LBSI_VCLK_RESET_STATUS_MASK 0x00040000L 1235 #define UVD_SOFT_RESET__VCPU_VCLK_RESET_STATUS_MASK 0x00080000L 1236 #define UVD_SOFT_RESET__UDEC_VCLK_RESET_STATUS_MASK 0x00100000L 1237 #define UVD_SOFT_RESET__UDEC_DCLK_RESET_STATUS_MASK 0x00200000L 1238 #define UVD_SOFT_RESET__MPC_DCLK_RESET_STATUS_MASK 0x00400000L 1239 #define UVD_SOFT_RESET__MIF_DCLK_RESET_STATUS_MASK 0x04000000L 1240 #define UVD_SOFT_RESET__LCM_DCLK_RESET_STATUS_MASK 0x08000000L 1241 #define UVD_SOFT_RESET__SUVD_VCLK_RESET_STATUS_MASK 0x10000000L 1242 #define UVD_SOFT_RESET__SUVD_DCLK_RESET_STATUS_MASK 0x20000000L 1243 #define UVD_SOFT_RESET__RE_DCLK_RESET_STATUS_MASK 0x40000000L 1244 #define UVD_SOFT_RESET__SRE_DCLK_RESET_STATUS_MASK 0x80000000L 1245 //UVD_LMI_RBC_IB_VMID 1246 #define UVD_LMI_RBC_IB_VMID__IB_VMID__SHIFT 0x0 1247 #define UVD_LMI_RBC_IB_VMID__IB_VMID_MASK 0x0000000FL 1248 //UVD_RBC_IB_SIZE 1249 #define UVD_RBC_IB_SIZE__IB_SIZE__SHIFT 0x4 1250 #define UVD_RBC_IB_SIZE__IB_SIZE_MASK 0x007FFFF0L 1251 //UVD_RBC_RB_RPTR 1252 #define UVD_RBC_RB_RPTR__RB_RPTR__SHIFT 0x4 1253 #define UVD_RBC_RB_RPTR__RB_RPTR_MASK 0x007FFFF0L 1254 //UVD_RBC_RB_WPTR 1255 #define UVD_RBC_RB_WPTR__RB_WPTR__SHIFT 0x4 1256 #define UVD_RBC_RB_WPTR__RB_WPTR_MASK 0x007FFFF0L 1257 //UVD_RBC_RB_WPTR_CNTL 1258 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER__SHIFT 0x0 1259 #define UVD_RBC_RB_WPTR_CNTL__RB_PRE_WRITE_TIMER_MASK 0x00007FFFL 1260 //UVD_RBC_WPTR_STATUS 1261 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE__SHIFT 0x4 1262 #define UVD_RBC_WPTR_STATUS__RB_WPTR_IN_USE_MASK 0x007FFFF0L 1263 //UVD_RBC_RB_CNTL 1264 #define UVD_RBC_RB_CNTL__RB_BUFSZ__SHIFT 0x0 1265 #define UVD_RBC_RB_CNTL__RB_BLKSZ__SHIFT 0x8 1266 #define UVD_RBC_RB_CNTL__RB_NO_FETCH__SHIFT 0x10 1267 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN__SHIFT 0x14 1268 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE__SHIFT 0x18 1269 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN__SHIFT 0x1c 1270 #define UVD_RBC_RB_CNTL__RB_BUFSZ_MASK 0x0000001FL 1271 #define UVD_RBC_RB_CNTL__RB_BLKSZ_MASK 0x00001F00L 1272 #define UVD_RBC_RB_CNTL__RB_NO_FETCH_MASK 0x00010000L 1273 #define UVD_RBC_RB_CNTL__RB_WPTR_POLL_EN_MASK 0x00100000L 1274 #define UVD_RBC_RB_CNTL__RB_NO_UPDATE_MASK 0x01000000L 1275 #define UVD_RBC_RB_CNTL__RB_RPTR_WR_EN_MASK 0x10000000L 1276 //UVD_RBC_RB_RPTR_ADDR 1277 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR__SHIFT 0x0 1278 #define UVD_RBC_RB_RPTR_ADDR__RB_RPTR_ADDR_MASK 0xFFFFFFFFL 1279 //UVD_STATUS 1280 #define UVD_STATUS__RBC_BUSY__SHIFT 0x0 1281 #define UVD_STATUS__VCPU_REPORT__SHIFT 0x1 1282 #define UVD_STATUS__AVP_BUSY__SHIFT 0x8 1283 #define UVD_STATUS__IDCT_BUSY__SHIFT 0x9 1284 #define UVD_STATUS__IDCT_CTL_ACK__SHIFT 0xb 1285 #define UVD_STATUS__UVD_CTL_ACK__SHIFT 0xc 1286 #define UVD_STATUS__AVP_BLOCK_ACK__SHIFT 0xd 1287 #define UVD_STATUS__IDCT_BLOCK_ACK__SHIFT 0xe 1288 #define UVD_STATUS__UVD_BLOCK_ACK__SHIFT 0xf 1289 #define UVD_STATUS__RBC_ACCESS_GPCOM__SHIFT 0x10 1290 #define UVD_STATUS__SYS_GPCOM_REQ__SHIFT 0x1f 1291 #define UVD_STATUS__RBC_BUSY_MASK 0x00000001L 1292 #define UVD_STATUS__VCPU_REPORT_MASK 0x000000FEL 1293 #define UVD_STATUS__AVP_BUSY_MASK 0x00000100L 1294 #define UVD_STATUS__IDCT_BUSY_MASK 0x00000200L 1295 #define UVD_STATUS__IDCT_CTL_ACK_MASK 0x00000800L 1296 #define UVD_STATUS__UVD_CTL_ACK_MASK 0x00001000L 1297 #define UVD_STATUS__AVP_BLOCK_ACK_MASK 0x00002000L 1298 #define UVD_STATUS__IDCT_BLOCK_ACK_MASK 0x00004000L 1299 #define UVD_STATUS__UVD_BLOCK_ACK_MASK 0x00008000L 1300 #define UVD_STATUS__RBC_ACCESS_GPCOM_MASK 0x00010000L 1301 #define UVD_STATUS__SYS_GPCOM_REQ_MASK 0x80000000L 1302 //UVD_SEMA_TIMEOUT_STATUS 1303 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x0 1304 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT__SHIFT 0x1 1305 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT__SHIFT 0x2 1306 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR__SHIFT 0x3 1307 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000001L 1308 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_WAIT_FAULT_TIMEOUT_STAT_MASK 0x00000002L 1309 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_SIGNAL_INCOMPLETE_TIMEOUT_STAT_MASK 0x00000004L 1310 #define UVD_SEMA_TIMEOUT_STATUS__SEMAPHORE_TIMEOUT_CLEAR_MASK 0x00000008L 1311 //UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL 1312 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN__SHIFT 0x0 1313 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT__SHIFT 0x1 1314 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 1315 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_EN_MASK 0x00000001L 1316 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__WAIT_INCOMPLETE_COUNT_MASK 0x001FFFFEL 1317 #define UVD_SEMA_WAIT_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 1318 //UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL 1319 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN__SHIFT 0x0 1320 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT__SHIFT 0x1 1321 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 1322 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_EN_MASK 0x00000001L 1323 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__WAIT_FAULT_COUNT_MASK 0x001FFFFEL 1324 #define UVD_SEMA_WAIT_FAULT_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 1325 //UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL 1326 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN__SHIFT 0x0 1327 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT__SHIFT 0x1 1328 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER__SHIFT 0x18 1329 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_EN_MASK 0x00000001L 1330 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__SIGNAL_INCOMPLETE_COUNT_MASK 0x001FFFFEL 1331 #define UVD_SEMA_SIGNAL_INCOMPLETE_TIMEOUT_CNTL__RESEND_TIMER_MASK 0x07000000L 1332 //UVD_CONTEXT_ID 1333 #define UVD_CONTEXT_ID__CONTEXT_ID__SHIFT 0x0 1334 #define UVD_CONTEXT_ID__CONTEXT_ID_MASK 0xFFFFFFFFL 1335 //UVD_CONTEXT_ID2 1336 #define UVD_CONTEXT_ID2__CONTEXT_ID2__SHIFT 0x0 1337 #define UVD_CONTEXT_ID2__CONTEXT_ID2_MASK 0xFFFFFFFFL 1338 //UVD_RBC_WPTR_POLL_CNTL 1339 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ__SHIFT 0x0 1340 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT__SHIFT 0x10 1341 #define UVD_RBC_WPTR_POLL_CNTL__POLL_FREQ_MASK 0x0000FFFFL 1342 #define UVD_RBC_WPTR_POLL_CNTL__IDLE_POLL_COUNT_MASK 0xFFFF0000L 1343 //UVD_RBC_WPTR_POLL_ADDR 1344 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR__SHIFT 0x2 1345 #define UVD_RBC_WPTR_POLL_ADDR__POLL_ADDR_MASK 0xFFFFFFFCL 1346 //UVD_RB_BASE_LO4 1347 #define UVD_RB_BASE_LO4__RB_BASE_LO__SHIFT 0x6 1348 #define UVD_RB_BASE_LO4__RB_BASE_LO_MASK 0xFFFFFFC0L 1349 //UVD_RB_BASE_HI4 1350 #define UVD_RB_BASE_HI4__RB_BASE_HI__SHIFT 0x0 1351 #define UVD_RB_BASE_HI4__RB_BASE_HI_MASK 0xFFFFFFFFL 1352 //UVD_RB_SIZE4 1353 #define UVD_RB_SIZE4__RB_SIZE__SHIFT 0x4 1354 #define UVD_RB_SIZE4__RB_SIZE_MASK 0x007FFFF0L 1355 //UVD_RB_RPTR4 1356 #define UVD_RB_RPTR4__RB_RPTR__SHIFT 0x4 1357 #define UVD_RB_RPTR4__RB_RPTR_MASK 0x007FFFF0L 1358 1359 1360 #endif 1361
Indexes created Thu Oct 02 14:10:14 GMT 2025