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    Searched defs:UseMI (Results 1 - 23 of 23) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
Localizer.cpp 126 MachineInstr &UseMI = *MOUse.getParent();
127 if (MRI->hasOneUse(Reg) && !UseMI.isPHI())
128 InsertMBB->insert(InsertMBB->SkipPHIsAndLabels(UseMI), LocalizedMI);
164 for (MachineInstr &UseMI : MRI->use_nodbg_instructions(Reg)) {
165 if (!UseMI.isPHI())
166 Users.insert(&UseMI);
  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIFixSGPRCopies.cpp 186 const auto *UseMI = MO.getParent();
187 if (UseMI == &MI)
189 if (MO.isDef() || UseMI->getParent() != MI.getParent() ||
190 UseMI->getOpcode() <= TargetOpcode::GENERIC_OP_END)
193 unsigned OpIdx = UseMI->getOperandNo(&MO);
194 if (OpIdx >= UseMI->getDesc().getNumOperands() ||
195 !TII->isOperandLegal(*UseMI, OpIdx, &Src))
788 const MachineInstr *UseMI = Use.getParent();
789 AllAGPRUses &= (UseMI->isCopy() &&
790 TRI->isAGPR(*MRI, UseMI->getOperand(0).getReg())) |
    [all...]
SILowerControlFlow.cpp 217 auto UseMI = MRI->use_instr_nodbg_begin(SaveExecReg);
218 SimpleIf = !hasKill(MI.getParent(), UseMI->getParent());
SIFoldOperands.cpp 24 MachineInstr *UseMI;
38 UseMI(MI), OpToFold(nullptr), ShrinkOpcode(ShrinkOp), UseOpNo(OpNo),
88 MachineInstr *UseMI,
151 const MachineInstr &UseMI,
154 if (TII->isInlineConstant(UseMI, OpNo, OpToFold))
157 unsigned Opc = UseMI.getOpcode();
175 const MachineInstr &UseMI,
181 if (TII->isMUBUF(UseMI))
182 return OpNo == AMDGPU::getNamedOperandIdx(UseMI.getOpcode(),
184 if (!TII->isFLATScratch(UseMI))
    [all...]
SIInstrInfo.cpp 2696 bool SIInstrInfo::FoldImmediate(MachineInstr &UseMI, MachineInstr &DefMI,
2721 unsigned Opc = UseMI.getOpcode();
2723 Register DstReg = UseMI.getOperand(0).getReg();
2724 bool Is16Bit = getOpSize(UseMI, 0) == 2;
2729 if (UseMI.getOperand(1).getSubReg() == AMDGPU::hi16)
2743 UseMI.getOperand(0).getSubReg() != AMDGPU::lo16)
2746 UseMI.getOperand(0).setSubReg(0);
2749 UseMI.getOperand(0).setReg(DstReg);
2751 assert(UseMI.getOperand(1).getReg().isVirtual());
2754 UseMI.setDesc(get(NewOpc))
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/
LiveRangeEdit.cpp 187 MachineInstr *DefMI = nullptr, *UseMI = nullptr;
199 if (UseMI && UseMI != MI)
204 UseMI = MI;
207 if (!DefMI || !UseMI)
213 LIS.getInstructionIndex(*UseMI)))
217 // Assume there are stores between DefMI and UseMI.
223 << " into single use: " << *UseMI);
226 if (UseMI->readsWritesVirtualRegister(LI->reg(), &Ops).second)
229 MachineInstr *FoldMI = TII.foldMemoryOperand(*UseMI, Ops, *DefMI, &LIS)
    [all...]
MachineSSAUpdater.cpp 225 MachineInstr *UseMI = U.getParent();
227 if (UseMI->isPHI()) {
228 MachineBasicBlock *SourceBB = findCorrespondingPred(UseMI, &U);
231 NewVR = GetValueInMiddleOfBlock(UseMI->getParent());
DetectDeadLanes.cpp 420 const MachineInstr &UseMI = *MO.getParent();
421 if (UseMI.isKill())
425 if (lowersToCopies(UseMI)) {
426 assert(UseMI.getDesc().getNumDefs() == 1);
427 const MachineOperand &Def = *UseMI.defs().begin();
434 if (lowersToCopies(UseMI)) {
436 CrossCopy = isCrossCopy(*MRI, UseMI, DstRC, MO);
438 LLVM_DEBUG(dbgs() << "Copy across incompatible classes: " << UseMI);
RegisterScavenging.cpp 290 MachineBasicBlock::iterator &UseMI) {
347 UseMI = RestorePointMI;
449 MachineBasicBlock::iterator &UseMI) {
494 if (!TRI->saveScavengerRegister(*MBB, Before, UseMI, &RC, Reg)) {
511 TII->loadRegFromStackSlot(*MBB, UseMI, Reg, Scavenged[SI].FrameIndex,
513 II = std::prev(UseMI);
545 MachineBasicBlock::iterator UseMI;
546 Register SReg = findSurvivorReg(I, Candidates, 25, UseMI);
557 ScavengedInfo &Scavenged = spill(SReg, *RC, SPAdj, I, UseMI);
558 Scavenged.Restore = &*std::prev(UseMI);
    [all...]
TailDuplicator.cpp 221 MachineInstr *UseMI = UseMO.getParent();
223 if (UseMI->isDebugValue()) {
228 UseMI->eraseFromParent();
231 if (UseMI->getParent() == DefBB && !UseMI->isPHI())
299 for (MachineInstr &UseMI : MRI->use_instructions(Reg)) {
300 if (UseMI.isDebugValue())
302 if (UseMI.getParent() != BB)
LiveIntervals.cpp 477 for (MachineInstr &UseMI : MRI->reg_instructions(Reg)) {
478 if (UseMI.isDebugValue() || !UseMI.readsVirtualRegister(Reg))
480 SlotIndex Idx = getInstructionIndex(UseMI).getRegSlot();
488 dbgs() << Idx << '\t' << UseMI
584 MachineInstr *UseMI = MO.getParent();
585 SlotIndex Idx = getInstructionIndex(*UseMI).getRegSlot();
PeepholeOptimizer.cpp 504 MachineInstr *UseMI = UseMO.getParent();
505 if (UseMI == &MI)
508 if (UseMI->isPHI()) {
534 if (UseMI->getOpcode() == TargetOpcode::SUBREG_TO_REG)
537 MachineBasicBlock *UseMBB = UseMI->getParent();
540 if (!LocalMIs.count(UseMI))
577 MachineInstr *UseMI = UseMO->getParent();
578 MachineBasicBlock *UseMBB = UseMI->getParent();
589 MachineInstr *Copy = BuildMI(*UseMBB, UseMI, UseMI->getDebugLoc()
    [all...]
ModuloSchedule.cpp 88 MachineInstr *UseMI = UseOp.getParent();
89 int UseStage = Schedule.getStage(UseMI);
1152 MachineInstr *UseMI = UseOp.getParent();
1154 if (UseMI->getParent() != BB)
1156 if (UseMI->isPHI()) {
1157 if (!Phi->isPHI() && UseMI->getOperand(0).getReg() == NewReg)
1159 if (getLoopPhiReg(*UseMI, BB) != OldReg)
1162 InstrMapTy::iterator OrigInstr = InstrMap.find(UseMI);
1605 for (MachineInstr &UseMI : MRI.use_instructions(DefMO.getReg())) {
1608 assert(UseMI.isPHI())
    [all...]
MachinePipeliner.cpp 860 MachineInstr *UseMI = &*UI;
861 SUnit *SU = getSUnit(UseMI);
862 if (SU != nullptr && UseMI->isPHI()) {
RegisterCoalescer.cpp 866 MachineInstr *UseMI = MO.getParent();
867 unsigned OpNo = &MO - &UseMI->getOperand(0);
868 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI);
873 if (UseMI->isRegTiedToDefOperand(OpNo))
916 MachineInstr *UseMI = UseMO.getParent();
917 if (UseMI->isDebugValue()) {
923 SlotIndex UseIdx = LIS->getInstructionIndex(*UseMI).getRegSlot(true);
934 if (UseMI == CopyMI)
936 if (!UseMI->isCopy())
938 if (UseMI->getOperand(0).getReg() != IntB.reg() |
    [all...]
  /src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
AArch64PostLegalizerCombiner.cpp 159 MachineInstr &UseMI = *MRI.use_instr_begin(Dst);
160 unsigned UseOpc = UseMI.getOpcode();
  /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
MLxExpansionPass.cpp 122 MachineInstr *UseMI = &*MRI->use_instr_nodbg_begin(Reg);
123 if (UseMI->getParent() != MBB)
126 while (UseMI->isCopy() || UseMI->isInsertSubreg()) {
127 Reg = UseMI->getOperand(0).getReg();
130 UseMI = &*MRI->use_instr_nodbg_begin(Reg);
131 if (UseMI->getParent() != MBB)
  /src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
PPCVSXFMAMutate.cpp 286 MachineInstr *UseMI = UseMO.getParent();
290 if (UseMI == AddendMI)
  /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
HexagonOptAddrMode.cpp 92 bool xformUseMI(MachineInstr *TfrMI, MachineInstr *UseMI,
96 bool updateAddUses(MachineInstr *AddMI, MachineInstr *UseMI);
187 MachineInstr &UseMI = *NodeAddr<StmtNode *>(IA).Addr->getCode();
191 MI.getParent() != UseMI.getParent())
194 const MCInstrDesc &UseMID = UseMI.getDesc();
196 HII->getAddrMode(UseMI) != HexagonII::BaseImmOffset ||
197 getBaseWithLongOffset(UseMI) < 0)
201 if (UseMID.mayStore() && UseMI.getOperand(2).isReg() &&
202 UseMI.getOperand(2).getReg() == MI.getOperand(0).getReg())
205 for (auto &Mo : UseMI.operands()
    [all...]
HexagonConstExtenders.cpp 317 MachineInstr *UseMI = nullptr;
330 return UseMI->getOperand(OpNum);
333 return UseMI->getOperand(OpNum);
1102 unsigned IdxOpc = getRegOffOpcode(ED.UseMI->getOpcode());
1112 if (!ED.UseMI->mayLoad() && !ED.UseMI->mayStore())
1217 ED.UseMI = &MI;
1284 if (ED.UseMI->getOpcode() == Hexagon::A2_tfrsi) {
1489 MachineBasicBlock *DomB = ED0.UseMI->getParent();
1490 RefMIs.insert(ED0.UseMI);
    [all...]
HexagonHardwareLoops.cpp 1068 MachineInstr *UseMI = Use.getParent();
1071 if (MI != UseMI)
1102 MachineInstr *UseMI = I->getParent();
1103 if (UseMI == MI)
1106 UseMI->getOperand(0).setReg(0U);
  /src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
SelectionDAGISel.cpp 627 MachineInstr *UseMI = &*(UI++);
628 if (UseMI->isDebugValue()) continue;
629 if (UseMI->isCopy() && !CopyUseMI && UseMI->getParent() == EntryMBB) {
630 CopyUseMI = UseMI; continue;
  /src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
RISCVISelLowering.cpp 6524 MachineInstr *UseMI = MRI.getVRegDef(UseMO.getReg());
6525 if (UseMI) {
6526 UseMI = elideCopies(UseMI, MRI);
6527 if (UseMI && UseMI->isImplicitDef())

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