| /src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/ |
| FunctionPropertiesAnalysis.h | 41 /// Number of uses of this function, plus 1 if the function is callable
43 int64_t Uses = 0;
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| /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Utils/ |
| SSAUpdaterBulk.h | 34 /// wants to rewrite a set of uses of one value with uses of a set of values.
37 /// updates of different uses (which is not the case when traditional SSAUpdater
42 SmallVector<Use *, 4> Uses;
78 /// the requested uses update.
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| /src/external/apache2/llvm/dist/llvm/lib/Target/M68k/ |
| M68kFrameLowering.cpp | 154 SmallSet<uint16_t, 8> Uses;
164 Uses.insert(*AI);
168 if (!Uses.count(CS))
667 // 1. The interrupt handling function uses any of the "rep" instructions.
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| /src/external/apache2/llvm/dist/clang/lib/Sema/ |
| ScopeInfo.cpp | 153 WeakUseVector &Uses =
155 Uses.push_back(WeakUseTy(Msg, Msg->getNumArgs() == 0));
180 FunctionScopeInfo::WeakObjectUseMap::iterator Uses = WeakObjectUses.end();
185 Uses = WeakObjectUses.find(WeakObjectProfileTy(RefExpr));
192 Uses = WeakObjectUses.find(WeakObjectProfileTy(IvarE));
195 Uses = WeakObjectUses.find(WeakObjectProfileTy(DRE));
199 Uses =
208 if (Uses == WeakObjectUses.end())
213 llvm::find(llvm::reverse(Uses->second), WeakUseTy(E, true));
214 if (ThisUse == Uses->second.rend()
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| MachineLoopUtils.cpp | 59 // Replace all uses outside the original loop with the new register.
60 // FIXME: is the use_iterator stable enough to mutate register uses
62 SmallVector<MachineOperand *, 4> Uses;
65 Uses.push_back(&Use);
66 for (auto *Use : Uses) {
75 for (MachineOperand &MO : I->uses())
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| MIRCanonicalizerPass.cpp | 334 std::vector<MachineOperand *> Uses;
336 Uses.push_back(&*UI);
337 for (auto *MO : Uses)
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| RDFLiveness.cpp | 347 // Go over all phi uses and get the reaching defs for each use.
421 NodeSet Uses;
424 // defs, no more uses can be reached.
426 return Uses;
428 // Add all directly reached uses.
437 Uses.insert(U);
460 Uses.insert(T.begin(), T.end());
462 return Uses;
483 // Go over all defs and collect the reached uses that are non-phi uses
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/Transforms/Scalar/ |
| ConstantHoisting.h | 79 /// Keeps track of a constant candidate and its uses.
81 ConstantUseListType Uses;
95 Uses.push_back(ConstantUser(Inst, Idx));
102 ConstantUseListType Uses;
106 RebasedConstantInfo(ConstantUseListType &&Uses, Constant *Offset,
107 Type *Ty=nullptr) : Uses(std::move(Uses)), Offset(Offset), Ty(Ty) {}
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| /src/external/apache2/llvm/dist/llvm/tools/llvm-exegesis/lib/ |
| MCInstrDescView.h | 209 SmallVector<RegisterOperandAssignment, 2> Uses;
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| /src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| ScheduleDAGInstrs.h | 75 /// For non-data-dependent uses, OpIdx == -1.
98 /// Track local uses of virtual registers. These uses are gathered by the DAG
163 /// Defs, Uses - Remember where defs and uses of each register are as we
168 Reg2SUnitsMap Uses;
374 /// Returns true if the def register in \p MO has no uses.
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| /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| SIFormMemoryClauses.cpp | 64 const RegUse &Uses) const;
66 void collectRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses) const;
67 bool processRegUses(const MachineInstr &MI, RegUse &Defs, RegUse &Uses,
122 for (const MachineOperand &MO : MI.uses()) {
153 const RegUse &Uses) const {
170 const RegUse &Map = MO.isDef() ? Uses : Defs;
217 // Collect register defs and uses along with their lane masks and states.
219 RegUse &Defs, RegUse &Uses) const {
230 RegUse &Map = MO.isDef() ? Defs : Uses;
247 RegUse &Defs, RegUse &Uses,
[all...] |
| GCNDPPCombine.cpp | 8 // The pass combines V_MOV_B32_dpp instruction with its VALU uses as a DPP src0
37 // The mov_dpp instruction should reside in the same BB as all its uses
127 // Give up if there are any uses of the carry-out from instructions like
398 " for all uses\n");
406 LLVM_DEBUG(dbgs() << " failed: 64 bit dpp move uses unsupported"
491 SmallVector<MachineOperand*, 16> Uses;
494 Uses.push_back(&Use);
497 while (!Uses.empty()) {
498 MachineOperand *Use = Uses.pop_back_val();
511 " for all uses\n")
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| ARCOptAddrMode.cpp | 82 // If \p Uses is not null, fill it with instructions after \p Ldst which use
85 SmallVectorImpl<MachineInstr *> *Uses);
87 // Returns true if all instruction in \p Uses array can be adjusted
89 bool canFixPastUses(const ArrayRef<MachineInstr *> &Uses,
92 // Update all instructions in \p Uses to accomodate increment
94 void fixPastUses(ArrayRef<MachineInstr *> Uses, unsigned BaseReg,
138 // Return true if \p MI dominates of uses of virtual register \p VReg
227 SmallVector<MachineInstr *, 8> Uses;
228 MachineInstr *MoveTo = canJoinInstructions(&Ldst, &Add, &Uses);
233 if (!canFixPastUses(Uses, Add.getOperand(2), B)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| Thumb2ITBlockPass.cpp | 68 RegisterSet &Defs, RegisterSet &Uses);
79 /// instructions in the IT block. This also tracks "dependencies", i.e. uses
81 static void TrackDefUses(MachineInstr *MI, RegisterSet &Defs, RegisterSet &Uses,
107 InsertUsesDefs(LocalUses, Uses);
110 /// Clear kill flags for any uses in the given set. This will likely
113 static void ClearKillFlags(MachineInstr *MI, RegisterSet &Uses) {
117 if (!Uses.count(MO.getReg()))
138 RegisterSet &Defs, RegisterSet &Uses) {
152 if (Uses.count(DstReg) || Defs.count(SrcReg))
196 RegisterSet Defs, Uses;
[all...] |
| A15SDOptimizer.cpp | 208 // Check if all the uses of this instruction are marked as
621 // Collect all the uses of this MI's DPR def for updating later.
622 SmallVector<MachineOperand*, 8> Uses;
626 Uses.push_back(&*I);
633 for (SmallVectorImpl<MachineOperand *>::const_iterator I = Uses.begin(),
634 E = Uses.end(); I != E; ++I) {
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| BitTracker.h | 75 UseQueueType() : Uses(Dist) {}
78 return Uses.size();
84 return Uses.top();
88 Uses.push(MI);
92 Uses.pop();
103 std::priority_queue<MachineInstr*, std::vector<MachineInstr*>, Cmp> Uses;
119 UseQueueType UseQ; // Work queue of register uses.
|
| HexagonGenMux.cpp | 62 "farther of the two predicated uses"));
100 BitVector Defs, Uses;
103 DefUseInfo(const BitVector &D, const BitVector &U) : Defs(D), Uses(U) {}
130 BitVector &Uses) const;
159 BitVector &Uses) const {
160 // First, get the implicit defs and uses for this instruction.
168 expandReg(*R++, Uses);
170 // Look over all operands, and collect explicit defs and uses.
175 BitVector &Set = MO.isDef() ? Defs : Uses;
184 BitVector Defs(NR), Uses(NR)
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| WebAssemblyFixFunctionBitcasts.cpp | 67 SmallVectorImpl<std::pair<Use *, Function *>> &Uses,
69 for (Use &U : V->uses()) {
71 findUses(BC, F, Uses, ConstantBCs);
73 findUses(A, F, Uses, ConstantBCs);
77 // Skip uses that aren't immediately called
89 Uses.push_back(std::make_pair(&U, &F));
241 SmallVector<std::pair<Use *, Function *>, 0> Uses;
250 findUses(&F, F, Uses, ConstantBCs);
272 Uses.push_back(std::make_pair(UseMain, &F));
279 for (auto &UseFunc : Uses) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/IPO/ |
| FunctionAttrs.cpp | 332 SmallVector<ArgumentGraphNode *, 4> Uses;
346 // uses every node. Because the graph is directed and nothing points into
355 iterator begin() { return SyntheticRoot.Uses.begin(); }
356 iterator end() { return SyntheticRoot.Uses.end(); }
362 SyntheticRoot.Uses.push_back(&Node);
368 /// consider that a capture, instead adding it to the "Uses" list and
416 Uses.push_back(&*std::next(F->arg_begin(), UseIndex));
423 // Uses within our SCC.
424 SmallVector<Argument *, 4> Uses;
438 static ChildIteratorType child_begin(NodeRef N) { return N->Uses.begin();
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| X86RegisterInfo.cpp | 751 // LOCAL_ESCAPE uses a single offset, with no register. It only works in the
831 SmallSet<uint16_t, 8> Uses;
840 Uses.insert(*AI);
844 if (!Uses.count(CS) && CS != X86::RIP && CS != X86::RSP && CS != X86::ESP)
|
| /src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| InstrInfoEmitter.cpp | 106 static void PrintDefList(const std::vector<Record*> &Uses,
109 for (Record *U : Uses)
728 // Emit all of the instruction's implicit uses and defs.
729 Records.startTimer("Emit uses/defs");
732 std::vector<Record*> Uses = Inst->getValueAsListOfDefs("Uses");
733 if (!Uses.empty()) {
734 unsigned &IL = EmittedLists[Uses];
735 if (!IL) PrintDefList(Uses, IL = ++ListNumber, OS);
1003 // Emit the implicit uses and defs lists..
[all...] |
| GICombinerEmitter.cpp | 543 const auto &Uses = NamedEdgeUses[NameAndDefs.getKey()];
545 for (const VarInfo &UseVar : Uses) {
557 // from the def to the uses but we can't know which direction we're going
560 const auto &Uses = NameAndUses.getValue();
561 if (Uses.size() > 1) {
562 const auto &LeadingVar = Uses.front();
563 for (const auto &Var : ArrayRef<VarInfo>(Uses).drop_front()) {
682 "Generated state machine cannot lookup uses from a def (yet)");
|
| /src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| MipsDelaySlotFiller.cpp | 121 /// Set bits in Uses corresponding to MBB's live-out registers except for
136 BitVector Defs, Uses;
181 /// This subclass uses memory dependence information to determine whether a
192 /// Update Defs and Uses. Return true if there exist dependences that
193 /// disqualify the delay slot candidate between V and values in Uses and
202 SmallPtrSet<ValueType, 4> Uses, Defs;
345 : TRI(TRI), Defs(TRI.getNumRegs(), false), Uses(TRI.getNumRegs(), false) {}
408 Uses.set(LI.PhysReg);
429 Uses |= NewUses;
439 return (isRegInSet(Defs, Reg) || isRegInSet(Uses, Reg))
[all...] |
| /src/external/apache2/llvm/dist/llvm/lib/Transforms/Scalar/ |
| ConstantHoisting.cpp | 315 /// Find an insertion point that dominates all uses.
323 for (auto const &U : RCI.Uses)
363 /// could also be a cast instruction or a constant expression that uses the
545 // and their number of uses:
550 // Selecting constant 12 because it has the most uses will generate negative
556 // range 0..35, and thus 3 + 2 + 8 = 13 uses are in range. Selecting 12 would
557 // have only 8 uses in range, so choosing 2 as a base is more optimal. Thus, in
576 NumUses += ConstCand->Uses.size();
589 NumUses += ConstCand->Uses.size();
593 for (auto User : ConstCand->Uses) {
[all...] |
| /src/external/apache2/llvm/dist/llvm/include/llvm/MCA/ |
| Instruction.h | 71 // uses always come first in the sequence of uses.
93 /// Tracks uses of a register definition (e.g. register write).
410 SmallVector<ReadState, 4> Uses;
417 SmallVectorImpl<ReadState> &getUses() { return Uses; }
418 ArrayRef<ReadState> getUses() const { return Uses; }
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