1 /* $NetBSD: vtpbcreg.h,v 1.2 2005/12/24 20:06:46 perry Exp $ */ 2 3 /* 4 * Registers for the V3 Semiconductor V962 and V360EPC i960 5 * PCI bus controller. 6 * 7 * This file is modified from the PMON sources available from 8 * Algorithmics, Ltd. 9 */ 10 11 #if BYTE_ORDER == LITTLE_ENDIAN 12 #define V96XW(vt, x) *(volatile u_int32_t *)((vt)->vt_addr + (x)) 13 #define V96XH(vt, x) *(volatile u_int16_t *)((vt)->vt_addr + (x)) 14 #define V96XB(vt, x) *(volatile u_int8_t *)((vt)->vt_addr + (x)) 15 #else 16 #define V96XW(vt, x) *(volatile u_int32_t *)((vt)->vt_addr + (x)) 17 #define V96XH(vt, x) *(volatile u_int16_t *)((vt)->vt_addr + ((x) ^ 2)) 18 #define V96XB(vt, x) *(volatile u_int8_t *)((vt)->vt_addr + ((x) ^ 3)) 19 #endif 20 21 #define V96X_PCI_VENDOR(vt) V96XH(vt, 0x00) 22 #define V96X_PCI_DEVICE(vt) V96XH(vt, 0x02) 23 #define V96X_PCI_CMD(vt) V96XH(vt, 0x04) 24 #define V96X_PCI_STAT(vt) V96XH(vt, 0x06) 25 #define V96X_PCI_CC_REV(vt) V96XW(vt, 0x08) 26 #define V96X_PCI_I20_BASE(vt) V96XW(vt, 0x10) /* B.2 only */ 27 #define V96X_PCI_HDR_CFG(vt) V96XW(vt, 0x0c) 28 #define V96X_PCI_IO_BASE(vt) V96XW(vt, 0x10) 29 #define V96X_PCI_BASE0(vt) V96XW(vt, 0x14) 30 #define V96X_PCI_BASE1(vt) V96XW(vt, 0x18) 31 #define V96X_PCI_BPARAM(vt) V96XW(vt, 0x3c) 32 #define V96X_PCI_MAP0(vt) V96XW(vt, 0x40) 33 #define V96X_PCI_MAP1(vt) V96XW(vt, 0x44) 34 #define V96X_PCI_INT_STAT(vt) V96XW(vt, 0x48) 35 #define V96X_PCI_INT_CFG(vt) V96XW(vt, 0x4c) 36 #define V96X_LB_BASE0(vt) V96XW(vt, 0x54) 37 #define V96X_LB_BASE1(vt) V96XW(vt, 0x58) 38 #define V96X_LB_MAP0(vt) V96XH(vt, 0x5e) 39 #define V96X_LB_MAP1(vt) V96XH(vt, 0x62) 40 #define V96X_LB_BASE2(vt) V96XH(vt, 0x64) /* B.2 only */ 41 #define V96X_LB_MAP2(vt) V96XH(vt, 0x66) /* B.2 only */ 42 #define V96X_LB_SIZE(vt) V96XW(vt, 0x68) /* B.2 only */ 43 #define V96X_LB_IO_BASE(vt) V96XW(vt, 0x6c) 44 #define V96X_FIFO_CFG(vt) V96XH(vt, 0x70) 45 #define V96X_FIFO_PRIORITY(vt) V96XH(vt, 0x72) 46 #define V96X_FIFO_STAT(vt) V96XH(vt, 0x74) 47 #define V96X_LB_ISTAT(vt) V96XB(vt, 0x76) 48 #define V96X_LB_IMASK(vt) V96XB(vt, 0x77) 49 #define V96X_SYSTEM(vt) V96XH(vt, 0x78) 50 #define V96X_LB_CFGL(vt) V96XB(vt, 0x7a) 51 #define V96X_LB_CFG(vt) V96XB(vt, 0x7b) 52 #define V96X_PCI_CFG(vt) V96XB(vt, 0x7c) /* B.2 only */ 53 #define V96X_DMA_PCI_ADDR0(vt) V96XW(vt, 0x80) 54 #define V96X_DMA_LOCAL_ADDR0(vt) V96XW(vt, 0x84) 55 #define V96X_DMA_LENGTH0(vt) V96XW(vt, 0x88) 56 #define V96X_DMA_CTLB_ADR0(vt) V96XW(vt, 0x8c) 57 #define V96X_DMA_PCI_ADDR1(vt) V96XW(vt, 0x90) 58 #define V96X_DMA_LOCAL_ADDR1(vt) V96XW(vt, 0x94) 59 #define V96X_DMA_LENGTH1(vt) V96XW(vt, 0x98) 60 #define V96X_DMA_CTLB_ADR1(vt) V96XW(vt, 0x9c) 61 #define V96X_MAIL_DATA(vt, n) V96XB(vt, 0xc0 + (n)) 62 #define V96X_LB_MAIL_IEWR(vt) V96XH(vt, 0xd0) 63 #define V96X_LB_MAIL_IERD(vt) V96XH(vt, 0xd2) 64 #define V96X_PCI_MAIL_IEWR(vt) V96XH(vt, 0xd4) 65 #define V96X_PCI_MAIL_IERD(vt) V96XH(vt, 0xd6) 66 #define V96X_MAIL_WR_STAT(vt) V96XH(vt, 0xd8) 67 #define V96X_MAIL_RD_STAT(vt) V96XH(vt, 0xdc) 68 69 #define V96X_PCI_CMD_FBB_EN 0x0200 70 #define V96X_PCI_CMD_SERR_EN 0x0100 71 #define V96X_PCI_CMD_PAR_EN 0x0040 72 #define V96X_PCI_CMD_MASTER_EN 0x0004 73 #define V96X_PCI_CMD_MEM_EN 0x0002 74 #define V96X_PCI_CMD_IO_EN 0x0001 75 76 #define V96X_PCI_STAT_PAR_ERR 0x8000 77 #define V96X_PCI_STAT_SYS_ERR 0x4000 78 #define V96X_PCI_STAT_M_ABORT 0x2000 79 #define V96X_PCI_STAT_T_ABORT 0x1000 80 #define V96X_PCI_STAT_DEVSEL 0x0600 81 #define V96X_PCI_STAT_PAR_REP 0x0100 82 #define V96X_PCI_STAT_FAST_BACK 0x0080 83 84 #define V96X_PCI_CC_REV_BASE_CLASS 0xff000000 85 #define V96X_PCI_CC_REV_SUB_CLASS 0x00ff0000 86 #define V96X_PCI_CC_REV_PROG_IF 0x0000ff00 87 #define V96X_PCI_CC_REV_UREV 0x000000f0 88 #define V96X_PCI_CC_REV_VREV 0x0000000f 89 90 #define V96X_VREV_A 0x0 91 #define V96X_VREV_B0 0x1 92 #define V96X_VREV_B1 0x2 93 #define V96X_VREV_B2 0x3 94 #define V96X_VREV_C0 0x4 95 96 #define V96X_PCI_HDR_CFG_LT 0x0000ff00 97 #define V96X_PCI_HDR_CFG_LT_SHIFT 8 98 #define V96X_PCI_HDR_CFG_CLS 0x000000ff 99 #define V96X_PCI_HDR_CFG_CLS_SHIFT 0 100 101 /* pci access to internal v96xpbc registers */ 102 #define V96X_PCI_IO_BASE_ADR_BASE 0xfffffff0 103 #define V96X_PCI_IO_BASE_PREFETCH 0x00000008 104 #define V96X_PCI_IO_BASE_TYPE 0x00000006 105 #define V96X_PCI_IO_BASE_IO 0x00000001 106 #define V96X_PCI_IO_BASE_MEM 0x00000000 107 108 /* pci to local bus aperture 0 base address */ 109 #define V96X_PCI_BASE0_ADR_BASE 0xfff00000 110 #define V96X_PCI_BASE0_ADR_BASEL 0x000fff00 111 112 /* pci to local bus aperture 1 base address */ 113 #define V96X_PCI_BASE1_ADR_BASE 0xfff00000 114 #define V96X_PCI_BASE1_ADR_BASEL 0x000fc000 115 #define V96X_PCI_BASE1_ADR_DOS_MEM 0x00000700 116 117 #define V96X_PCI_BASEx_PREFETCH 0x00000008 118 #define V96X_PCI_BASEx_IO 0x00000001 119 #define V96X_PCI_BASEx_MEM 0x00000000 120 121 /* pci bus parameter register */ 122 #define V96X_PCI_BPARAM_MAX_LAT 0xff000000 123 #define V96X_PCI_BPARAM_MIN_GNT 0x00ff0000 124 #define V96X_PCI_BPARAM_INT_PIN 0x00000700 125 #define V96X_PCI_BPARAM_INT_LINE 0x0000000f 126 127 /* pci bus to local bus address map 0 */ 128 #define V96X_PCI_MAPx_MAP_ADR 0xfff00000 129 #define V96X_PCI_MAPx_RD_POST_INH 0x00008000 130 #define V96X_PCI_MAP0_ROM_SIZE 0x00000c00 131 #define V96X_PCI_MAPx_SWAP 0x00000300 132 #define V96X_PCI_MAPx_ADR_SIZE 0x000000f0 133 #define V96X_PCI_MAPx_REG_EN 0x00000002 134 #define V96X_PCI_MAPx_ENABLE 0x00000001 135 136 #define V96X_ADR_SIZE_1MB (0x0<<4) 137 #define V96X_ADR_SIZE_2MB (0x1<<4) 138 #define V96X_ADR_SIZE_4MB (0x2<<4) 139 #define V96X_ADR_SIZE_8MB (0x3<<4) 140 #define V96X_ADR_SIZE_16MB (0x4<<4) 141 #define V96X_ADR_SIZE_32MB (0x5<<4) 142 #define V96X_ADR_SIZE_64MB (0x6<<4) 143 #define V96X_ADR_SIZE_128MB (0x7<<4) 144 #define V96X_ADR_SIZE_256MB (0x8<<4) 145 #define V96X_ADR_SIZE_DOSMODE (0xc<<4) 146 147 #define V96X_SWAP_NONE (0x0<<8) 148 #define V96X_SWAP_16BIT (0x1<<8) 149 #define V96X_SWAP_8BIT (0x2<<8) 150 #define V96X_SWAP_AUTO (0x3<<8) 151 152 /* pci interrupt status register */ 153 #define V96X_PCI_INT_STAT_MAILBOX 0x80000000 154 #define V96X_PCI_INT_STAT_LOCAL 0x40000000 155 #define V96X_PCI_INT_STAT_DMA1 0x02000000 156 #define V96X_PCI_INT_STAT_DMA0 0x01000000 157 #define V96X_PCI_INT_STAT_INTC_TO_D 0x00004000 158 #define V96X_PCI_INT_STAT_INTB_TO_D 0x00002000 159 #define V96X_PCI_INT_STAT_INTA_TO_D 0x00001000 160 #define V96X_PCI_INT_STAT_INTD_TO_C 0x00000800 161 #define V96X_PCI_INT_STAT_INTB_TO_C 0x00000200 162 #define V96X_PCI_INT_STAT_INTA_TO_C 0x00000100 163 #define V96X_PCI_INT_STAT_INTD_TO_B 0x00000080 164 #define V96X_PCI_INT_STAT_INTC_TO_B 0x00000040 165 #define V96X_PCI_INT_STAT_INTA_TO_B 0x00000010 166 #define V96X_PCI_INT_STAT_INTD_TO_A 0x00000008 167 #define V96X_PCI_INT_STAT_INTC_TO_A 0x00000004 168 #define V96X_PCI_INT_STAT_INTB_TO_A 0x00000002 169 170 /* pci interrupt config register */ 171 #define V96X_PCI_INT_CFG_MAILBOX 0x80000000 172 #define V96X_PCI_INT_CFG_LOCAL 0x40000000 173 #define V96X_PCI_INT_CFG_DMA1 0x02000000 174 #define V96X_PCI_INT_CFG_DMA0 0x01000000 175 #define V96X_PCI_INT_CFG_MODE_D 0x00c00000 176 #define V96X_PCI_INT_CFG_MODE_D_SHIFT 22 177 #define V96X_PCI_INT_CFG_MODE_C 0x00300000 178 #define V96X_PCI_INT_CFG_MODE_C_SHIFT 20 179 #define V96X_PCI_INT_CFG_MODE_B 0x000c0000 180 #define V96X_PCI_INT_CFG_MODE_B_SHIFT 18 181 #define V96X_PCI_INT_CFG_MODE_A 0x00030000 182 #define V96X_PCI_INT_CFG_MODE_A_SHIFT 16 183 #define V96X_PCI_INT_CFG_MODE_LEVEL 0x0 184 #define V96X_PCI_INT_CFG_MODE_EDGE 0x1 185 #define V96X_PCI_INT_CFG_MODE_SWCLR 0x2 186 #define V96X_PCI_INT_CFG_MODE_HWCLR 0x3 187 #define V96X_PCI_INT_CFG_INTD_TO_LB 0x00008000 188 #define V96X_PCI_INT_CFG_INTC_TO_D 0x00004000 189 #define V96X_PCI_INT_CFG_INTB_TO_D 0x00002000 190 #define V96X_PCI_INT_CFG_INTA_TO_D 0x00001000 191 #define V96X_PCI_INT_CFG_INTD_TO_C 0x00000800 192 #define V96X_PCI_INT_CFG_INTC_TO_LB 0x00000400 193 #define V96X_PCI_INT_CFG_INTB_TO_C 0x00000200 194 #define V96X_PCI_INT_CFG_INTA_TO_C 0x00000100 195 #define V96X_PCI_INT_CFG_INTD_TO_B 0x00000080 196 #define V96X_PCI_INT_CFG_INTC_TO_B 0x00000040 197 #define V96X_PCI_INT_CFG_INTB_TO_LB 0x00000020 198 #define V96X_PCI_INT_CFG_INTA_TO_B 0x00000010 199 #define V96X_PCI_INT_CFG_INTD_TO_A 0x00000008 200 #define V96X_PCI_INT_CFG_INTC_TO_A 0x00000004 201 #define V96X_PCI_INT_CFG_INTB_TO_A 0x00000002 202 #define V96X_PCI_INT_CFG_INTA_TO_LB 0x00000001 203 204 /* local bus to pci bus aperture 0,1 */ 205 #define V96X_LB_BASEx_ADR_BASE 0xfff00000 206 #define V96X_LB_BASEx_SWAP 0x00000300 207 #define V96X_LB_BASEx_ADR_SIZE 0x000000f0 208 #define V96X_LB_BASEx_PREFETCH 0x00000008 209 #define V96X_LB_BASEx_ENABLE 0x00000001 210 211 /* local bus to pci bus address map 0,1 */ 212 #define V96X_LB_MAPx_MAP_ADR 0xfff0 213 #define V96X_LB_MAPx_TYPE 0x0007 214 #define V96X_LB_TYPE_IACK (0x0<<1) 215 #define V96X_LB_TYPE_IO (0x1<<1) 216 #define V96X_LB_TYPE_MEM (0x3<<1) 217 #define V96X_LB_TYPE_CONF (0x5<<1) 218 #define V96X_LB_MAPx_AD_LOW_EN 0x0001 /* C.0 only */ 219 220 /* local bus interrupt control, status and masks */ 221 #define V96X_LB_INTR_MAILBOX 0x80 222 #define V96X_LB_INTR_PCI_RD 0x40 223 #define V96X_LB_INTR_PCI_WR 0x20 224 #define V96X_LB_INTR_PCI_INT 0x10 225 #define V96X_LB_INTR_DMA1 0x02 226 #define V96X_LB_INTR_DMA0 0x01 227 228 /* local bus configuration */ 229 #define V96X_LB_CFG_TO_256 0x20 230 #define V96X_LB_CFG_TO_64 0x00 231 #define V96X_LB_CFG_LB_INT 0x02 232 #define V96X_LB_CFG_ERR_EN 0x02 233 #define V96X_LB_CFG_RDY_EN 0x01 234 235 /* PCI bus configuration */ 236 #define V96X_PCI_CFG_I2O_EN 0x8000 237 #define V96X_PCI_CFG_IO_REG_DIS 0x4000 238 #define V96X_PCI_CFG_IO_DIS 0x2000 239 #define V96X_PCI_CFG_EN3V 0x1000 240 #define V96X_PCI_CFG_AD_LOW 0x0300 241 #define V96X_PCI_CFG_AD_LOW_SHIFT 8 242 #define V96X_PCI_CFG_DMA_RTYPE 0x00e0 243 #define V96X_PCI_CFG_DMA_WTYPE 0x000e 244 245 /* fifo configuration register */ 246 #define V96X_FIFO_CFG_PBRST_MAX 0xc000 247 #define V96X_FIFO_CFG_PBRST_MAX_SHIFT 14 248 #define V96X_FIFO_CFG_WR_LB 0x3000 249 #define V96X_FIFO_CFG_WR_LB_SHIFT 12 250 #define V96X_FIFO_CFG_RD_LB1 0x0c00 251 #define V96X_FIFO_CFG_RD_LB1_SHIFT 10 252 #define V96X_FIFO_CFG_RD_LB0 0x0300 253 #define V96X_FIFO_CFG_RD_LB0_SHIFT 8 254 #define V96X_FIFO_CFG_LBRST_MAX 0x00c0 255 #define V96X_FIFO_CFG_LBRST_MAX_SHIFT 6 256 #define V96X_FIFO_CFG_WR_PCI 0x0030 257 #define V96X_FIFO_CFG_WR_PCI_SHIFT 4 258 #define V96X_FIFO_CFG_RD_PCI1 0x000c 259 #define V96X_FIFO_CFG_RD_PCI1_SHIFT 2 260 #define V96X_FIFO_CFG_RD_PCI0 0x0003 261 #define V96X_FIFO_CFG_RD_PCI0_SHIFT 0 262 263 /* meaning of above bitfields */ 264 265 /* max burst length */ 266 #define V96X_FIFO_CFG_BRST_4 0x0 267 #define V96X_FIFO_CFG_BRST_8 0x1 268 #define V96X_FIFO_CFG_BRST_16 0x2 269 #define V96X_FIFO_CFG_BRST_256 0x3 270 271 /* when to start refilling read fifo */ 272 #define V96X_FIFO_CFG_RD_NOTFULL 0x0 273 #define V96X_FIFO_CFG_RD_HALF 0x1 274 #define V96X_FIFO_CFG_RD_EMPTY 0x2 275 276 /* when to start emptying write fifo */ 277 #define V96X_FIFO_CFG_WR_NOTEMPTY 0x0 278 #define V96X_FIFO_CFG_WR_3WORDS 0x2 279 #define V96X_FIFO_CFG_WR_ENDBRST 0x3 280 281 /* fifo priority control */ 282 #define V96X_FIFO_PRIORITY_LOCAL_RD 0x1000 283 #define V96X_FIFO_PRIORITY_LOCAL_WR 0x0000 284 #define V96X_FIFO_PRIORITY_LB_RD1 0x0c00 285 #define V96X_FIFO_PRIORITY_LB_RD1_SHIFT 10 286 #define V96X_FIFO_PRIORITY_LB_RD0 0x0300 287 #define V96X_FIFO_PRIORITY_LB_RD0_SHIFT 8 288 #define V96X_FIFO_PRIORITY_PCI_RD 0x0010 289 #define V96X_FIFO_PRIORITY_PCI_WR 0x0000 290 #define V96X_FIFO_PRIORITY_PCI_RD1 0x000c 291 #define V96X_FIFO_PRIORITY_PCI_RD1_SHIFT 2 292 #define V96X_FIFO_PRIORITY_PCI_RD0 0x0003 293 #define V96X_FIFO_PRIORITY_PCI_RD0_SHIFT 0 294 295 /* meaning of above bitfields */ 296 #define V96X_FIFO_PRI_NOFLUSH 0x0 297 #define V96X_FIFO_PRI_FLUSHME 0x2 298 #define V96X_FIFO_PRI_FLUSHALL 0x3 299 300 /* fifo status */ 301 #define V96X_FIFO_STAT_L2P_WR 0x3000 302 #define V96X_FIFO_STAT_L2P_RD1 0x0c00 303 #define V96X_FIFO_STAT_L2P_RD0 0x0300 304 #define V96X_FIFO_STAT_P2L_WR 0x0030 305 #define V96X_FIFO_STAT_P2L_RD1 0x000c 306 #define V96X_FIFO_STAT_P2L_RD0 0x0003 307 308 #define V96X_DMA_COUNT_CHAIN 0x80000000 309 #define V96X_DMA_COUNT_PRIORITY 0x20000000 310 #define V96X_DMA_COUNT_P2L 0x10000000 311 #define V96X_DMA_COUNT_SWAP 0x0c000000 312 #define V96X_DMA_COUNT_ABORT 0x02000000 313 #define V96X_DMA_COUNT_DMA_IPR 0x01000000 314 315 #define V96X_SYSTEM_RST_OUT 0x8000 316 #define V96X_SYSTEM_LOCK 0x4000 317 #define V96X_SYSTEM_SPROM_EN 0x2000 318 #define V96X_SYSTEM_SCL 0x1000 319 #define V96X_SYSTEM_SDA_OUT 0x0800 320 #define V96X_SYSTEM_SDA_IN 0x0400 321 #define V96X_SYSTEM_POE 0x0200 322 #define V96X_SYSTEM_LB_RD_PCI1 0x0040 323 #define V96X_SYSTEM_LB_RD_PCI0 0x0020 324 #define V96X_SYSTEM_LB_WR_PCI 0x0010 325 #define V96X_SYSTEM_PCI_RD_LB1 0x0004 326 #define V96X_SYSTEM_PCI_RD_LB0 0x0002 327 #define V96X_SYSTEM_PC_WR_LBI 0x0001 328
Indexes created Sun Sep 21 20:09:37 GMT 2025