1 /* $NetBSD: grtworeg.h,v 1.2 2005/12/11 12:18:53 christos Exp $ */ 2 3 /* 4 * Copyright (c) 2004 Christopher SEKIYA 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 3. The name of the author may not be used to endorse or promote products 16 * derived from this software without specific prior written permission. 17 * 18 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 19 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 20 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 21 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 22 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 23 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 24 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 25 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 26 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 27 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 28 * 29 * <<Id: LICENSE_GC,v 1.1 2001/10/01 23:24:05 cgd Exp>> 30 */ 31 32 #ifndef _ARCH_SGIMIPS_GIO_GRTWOREG_H_ 33 #define _ARCH_SGIMIPS_GIO_GRTWOREG_H_ 34 35 /* 36 * Memory map: 37 * 38 * 0x1f000000 - 0x1f01ffff Shared data RAM 39 * 0x1f020000 - 0x1f03ffff (unused) 40 * 0x1f040000 - 0x1f05ffff FIFO 41 * 0x1f060000 - 0x1f068000 HQ2 ucode 42 * 0x1f068000 - 0x1f069fff GE7 (eight of them) 43 * 0x1f06a000 - 0x1f06b004 HQ2 44 * 0x1f06c000 Board revision register 45 * 0x1f06c020 clock 46 * 0x1f06c040 VC1 47 * 0x1f06c060 BT479 Triple-DAC (read) 48 * 0x1f06c080 BT479 Triple-DAC (write) 49 * 0x1f06c0a0 BT457 DAC (red) 50 * 0x1f06c0c0 BT457 DAC (green) 51 * 0x1f06c0e0 BT457 DAC (blue) 52 * 0x1f06c100 XMAP5 (five of them) 53 * 0x1f06c1a0 XMAP5 ("xmap all") 54 * 0x1f06c1c0 Kaleidoscope (AB1) 55 * 0x1f06c1e0 Kaleidoscope (CC1) 56 * 0x1f06c200 RE3 (27-bit registers) 57 * 0x1f06c280 RE3 (24-bit registers) 58 * 0x1f06c600 RE3 (32-bit registers) 59 */ 60 61 #define GR2_FIFO 0x40000 62 #define GR2_FIFO_INIT (GR2_FIFO + 0x644) 63 #define GR2_FIFO_COLOR (GR2_FIFO + 0x648) 64 #define GR2_FIFO_FINISH (GR2_FIFO + 0x64c) 65 #define GR2_FIFO_PNT2I (GR2_FIFO + 0x650) 66 #define GR2_FIFO_RECTI2D (GR2_FIFO + 0x654) 67 #define GR2_FIFO_CMOV2I (GR2_FIFO + 0x658) 68 #define GR2_FIFO_LINE2I (GR2_FIFO + 0x65c) 69 #define GR2_FIFO_DRAWCHAR (GR2_FIFO + 0x660) 70 #define GR2_FIFO_RECTCOPY (GR2_FIFO + 0x664) 71 #define GR2_FIFO_DATA (GR2_FIFO + 0x77c) 72 73 /* HQ2 */ 74 75 #define HQ2_BASE 0x6a000 76 #define HQ2_ATTRJUMP (HQ2_BASE + 0x00) 77 #define HQ2_VERSION (HQ2_BASE + 0x40) 78 #define HQ2_VERSION_MASK 0xff000000 79 #define HQ2_VERSION_SHIFT 23 80 81 #define HQ2_NUMGE (HQ2_BASE + 0x44) 82 #define HQ2_FIN1 (HQ2_BASE + 0x48) 83 #define HQ2_FIN2 (HQ2_BASE + 0x4c) 84 #define HQ2_DMASYNC (HQ2_BASE + 0x50) 85 #define HQ2_FIFO_FULL_TIMEOUT (HQ2_BASE + 0x54) 86 #define HQ2_FIFO_EMPTY_TIMEOUT (HQ2_BASE + 0x58) 87 #define HQ2_FIFO_FULL (HQ2_BASE + 0x5c) 88 #define HQ2_FIFO_EMPTY (HQ2_BASE + 0x60) 89 #define HQ2_GE7_LOAD_UCODE (HQ2_BASE + 0x64) 90 #define HQ2_GEDMA (HQ2_BASE + 0x68) 91 #define HQ2_HQ_GEPC (HQ2_BASE + 0x6c) 92 #define HQ2_GEPC (HQ2_BASE + 0x70) 93 #define HQ2_INTR (HQ2_BASE + 0x74) 94 #define HQ2_UNSTALL (HQ2_BASE + 0x78) 95 #define HQ2_MYSTERY (HQ2_BASE + 0x7c) /* == 0xdeadbeef */ 96 #define HQ2_REFRESH (HQ2_BASE + 0x80) 97 #define HQ2_FIN3 (HQ2_BASE + 0x100) 98 99 /* GE7 */ 100 101 #define GE7_REVISION 0x680fc 102 #define GE7_REVISION_MASK 0xf0 103 104 /* VC1 */ 105 106 #define VC1_BASE 0x6c040 107 #define VC1_COMMAND (VC1_BASE + 0x00) 108 #define VC1_XMAPMODE (VC1_BASE + 0x04) 109 #define VC1_SRAM (VC1_BASE + 0x08) 110 #define VC1_TESTREG (VC1_BASE + 0x0c) 111 #define VC1_ADDRLO (VC1_BASE + 0x10) 112 #define VC1_ADDRHI (VC1_BASE + 0x14) 113 #define VC1_SYSCTL (VC1_BASE + 0x18) 114 115 /* VC1 System Control Register */ 116 #define VC1_SYSCTL_INTERRUPT 0x01 117 #define VC1_SYSCTL_VTG 0x02 118 #define VC1_SYSCTL_VC1 0x04 119 #define VC1_SYSCTL_DID 0x08 120 #define VC1_SYSCTL_CURSOR 0x10 121 #define VC1_SYSCTL_CURSOR_DISPLAY 0x20 122 #define VC1_SYSCTL_GENSYNC 0x40 123 #define VC1_SYSCTL_VIDEO 0x80 124 125 /* VC1 SRAM memory map */ 126 #define VC1_SRAM_VIDTIM_LST_BASE 0x0000 127 #define VC1_SRAM_VIDTIM_CURSLST_BASE 0x0400 128 #define VC1_SRAM_VIDTIM_FRMT_BASE 0x0800 129 #define VC1_SRAM_VIDTIM_CURSFRMT_BASE 0x0900 130 #define VC1_SRAM_INTERLACED 0x09f0 131 #define VC1_SRAM_SCREENWIDTH 0x09f2 132 #define VC1_SRAM_NEXTDID_ADDR 0x09f4 133 #define VC1_SRAM_CURSOR0_BASE 0x0a00 /* 32x32 */ 134 #define VC1_SRAM_DID_FRMT_BASE 0x0b00 135 #define VC1_SRAM_DID_MAX_FMTSIZE 0x0900 136 #define VC1_SRAM_DID_LST_END 0x8000 137 138 /* VC1 registers */ 139 #define VC1_VIDEO_EP 0x00 140 #define VC1_VIDEO_LC 0x02 141 #define VC1_VIDEO_SC 0x04 142 #define VC1_VIDEO_TSA 0x06 143 #define VC1_VIDEO_TSB 0x07 144 #define VC1_VIDEO_TSC 0x08 145 #define VC1_VIDEO_LP 0x09 146 #define VC1_VIDEO_LS_EP 0x0b 147 #define VC1_VIDEO_LR 0x0d 148 #define VC1_VIDEO_FC 0x10 149 #define VC1_VIDEO_ENABLE 0x14 150 151 /* Cursor Generator */ 152 #define VC1_CURSOR_EP 0x20 153 #define VC1_CURSOR_XL 0x22 154 #define VC1_CURSOR_YL 0x24 155 #define VC1_CURSOR_MODE 0x26 156 #define VC1_CURSOR_BX 0x27 157 #define VC1_CURSOR_LY 0x28 158 #define VC1_CURSOR_YC 0x2a 159 #define VC1_CURSOR_CC 0x2e 160 #define VC1_CURSOR_RC 0x30 161 162 /* Board revision register */ 163 164 #define GR2_REVISION 0x6c000 165 #define GR2_REVISION_RD0 0x6c000 166 #define GR2_REVISION_RD0_VERSION_MASK 0x0f 167 #define GR2_REVISION4_RD0_MONITOR_MASK 0xf0 168 169 #define GR2_REVISION_RD1 0x6c004 170 #define GR2_REVISION_RD1_BACKEND_REV 0x03 171 #define GR2_REVISION_RD1_ZBUFFER 0x0c 172 173 #define GR2_REVISION4_RD1_BACKEND 0x03 174 #define GR2_REVISION4_RD1_24BPP 0x10 175 #define GR2_REVISION4_RD1_ZBUFFER 0x20 176 177 #define GR2_REVISION_RD2 0x6c008 178 #define GR2_REVISION_RD2_BACKEND_REV 0x000c 179 180 /* one slot = 8bpp, two slots = 16bpp, three slots = 24bpp, br < 4 only */ 181 #define GR2_REVISION_RD3 0x6c00c 182 #define GR2_REVISION_RD3_VMA 0x03 /* both bits set == empty 183 * slot */ 184 #define GR2_REVISION_RD3_VMB 0x0c 185 #define GR2_REVISION_RD3_VMC 0x30 186 187 /* XMAP5 -- five of them, 0x1f06c100 - 0x1f06c1a0 */ 188 189 #define XMAP5_MISC 0x00 190 #define XMAP5_MODE 0x04 191 #define XMAP5_CLUT 0x08 192 #define XMAP5_CRC 0x0c 193 #define XMAP5_ADDRLO 0x10 194 #define XMAP5_ADRHI 0x14 195 #define XMAP5_BYTECOUNT 0x18 196 #define XMAP5_FIFOSTATUS 0x1c 197 198 #define XMAPALL_MISC 0x6c1a0 199 #define XMAPALL_MODE 0x6c1a4 200 #define XMAPALL_CLUT 0x6c1a8 201 #define XMAPALL_CRC 0x6c1ac 202 #define XMAPALL_ADDRLO 0x6c190 203 #define XMAPALL_ADDRHI 0x6c194 204 #define XMAPALL_BYTECOUNT 0x6c198 205 #define XMAPALL_FIFOSTATUS 0x6c19c 206 207 #endif 208
Indexes created Sun Sep 21 20:09:37 GMT 2025