1 /* $NetBSD: sid.h,v 1.5 2021/12/18 23:45:43 riastradh Exp $ */ 2 3 /* 4 * Copyright 2011 Advanced Micro Devices, Inc. 5 * 6 * Permission is hereby granted, free of charge, to any person obtaining a 7 * copy of this software and associated documentation files (the "Software"), 8 * to deal in the Software without restriction, including without limitation 9 * the rights to use, copy, modify, merge, publish, distribute, sublicense, 10 * and/or sell copies of the Software, and to permit persons to whom the 11 * Software is furnished to do so, subject to the following conditions: 12 * 13 * The above copyright notice and this permission notice shall be included in 14 * all copies or substantial portions of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL 19 * THE COPYRIGHT HOLDER(S) OR AUTHOR(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR 22 * OTHER DEALINGS IN THE SOFTWARE. 23 * 24 * Authors: Alex Deucher 25 */ 26 #ifndef SI_H 27 #define SI_H 28 29 #define TAHITI_RB_BITMAP_WIDTH_PER_SH 2 30 31 #define TAHITI_GB_ADDR_CONFIG_GOLDEN 0x12011003 32 #define VERDE_GB_ADDR_CONFIG_GOLDEN 0x12010002 33 #define HAINAN_GB_ADDR_CONFIG_GOLDEN 0x02010001 34 35 #define SI_MAX_SH_GPRS 256 36 #define SI_MAX_TEMP_GPRS 16 37 #define SI_MAX_SH_THREADS 256 38 #define SI_MAX_SH_STACK_ENTRIES 4096 39 #define SI_MAX_FRC_EOV_CNT 16384 40 #define SI_MAX_BACKENDS 8 41 #define SI_MAX_BACKENDS_MASK 0xFF 42 #define SI_MAX_BACKENDS_PER_SE_MASK 0x0F 43 #define SI_MAX_SIMDS 12 44 #define SI_MAX_SIMDS_MASK 0x0FFF 45 #define SI_MAX_SIMDS_PER_SE_MASK 0x00FF 46 #define SI_MAX_PIPES 8 47 #define SI_MAX_PIPES_MASK 0xFF 48 #define SI_MAX_PIPES_PER_SIMD_MASK 0x3F 49 #define SI_MAX_LDS_NUM 0xFFFF 50 #define SI_MAX_TCC 16 51 #define SI_MAX_TCC_MASK 0xFFFF 52 53 /* SMC IND accessor regs */ 54 #define SMC_IND_INDEX_0 0x200 55 #define SMC_IND_DATA_0 0x204 56 57 #define SMC_IND_ACCESS_CNTL 0x228 58 # define AUTO_INCREMENT_IND_0 (1 << 0) 59 #define SMC_MESSAGE_0 0x22c 60 #define SMC_RESP_0 0x230 61 62 /* CG IND registers are accessed via SMC indirect space + SMC_CG_IND_START */ 63 #define SMC_CG_IND_START 0xc0030000 64 #define SMC_CG_IND_END 0xc0040000 65 66 #define CG_CGTT_LOCAL_0 0x400 67 #define CG_CGTT_LOCAL_1 0x401 68 69 /* SMC IND registers */ 70 #define SMC_SYSCON_RESET_CNTL 0x80000000 71 # define RST_REG (1 << 0) 72 #define SMC_SYSCON_CLOCK_CNTL_0 0x80000004 73 # define CK_DISABLE (1 << 0) 74 # define CKEN (1 << 24) 75 76 #define VGA_HDP_CONTROL 0x328 77 #define VGA_MEMORY_DISABLE (1 << 4) 78 79 #define DCCG_DISP_SLOW_SELECT_REG 0x4fc 80 #define DCCG_DISP1_SLOW_SELECT(x) ((x) << 0) 81 #define DCCG_DISP1_SLOW_SELECT_MASK (7 << 0) 82 #define DCCG_DISP1_SLOW_SELECT_SHIFT 0 83 #define DCCG_DISP2_SLOW_SELECT(x) ((x) << 4) 84 #define DCCG_DISP2_SLOW_SELECT_MASK (7 << 4) 85 #define DCCG_DISP2_SLOW_SELECT_SHIFT 4 86 87 #define CG_SPLL_FUNC_CNTL 0x600 88 #define SPLL_RESET (1 << 0) 89 #define SPLL_SLEEP (1 << 1) 90 #define SPLL_BYPASS_EN (1 << 3) 91 #define SPLL_REF_DIV(x) ((x) << 4) 92 #define SPLL_REF_DIV_MASK (0x3f << 4) 93 #define SPLL_PDIV_A(x) ((x) << 20) 94 #define SPLL_PDIV_A_MASK (0x7f << 20) 95 #define SPLL_PDIV_A_SHIFT 20 96 #define CG_SPLL_FUNC_CNTL_2 0x604 97 #define SCLK_MUX_SEL(x) ((x) << 0) 98 #define SCLK_MUX_SEL_MASK (0x1ff << 0) 99 #define SPLL_CTLREQ_CHG (1 << 23) 100 #define SCLK_MUX_UPDATE (1 << 26) 101 #define CG_SPLL_FUNC_CNTL_3 0x608 102 #define SPLL_FB_DIV(x) ((x) << 0) 103 #define SPLL_FB_DIV_MASK (0x3ffffff << 0) 104 #define SPLL_FB_DIV_SHIFT 0 105 #define SPLL_DITHEN (1 << 28) 106 #define CG_SPLL_FUNC_CNTL_4 0x60c 107 108 #define SPLL_STATUS 0x614 109 #define SPLL_CHG_STATUS (1 << 1) 110 #define SPLL_CNTL_MODE 0x618 111 #define SPLL_SW_DIR_CONTROL (1 << 0) 112 # define SPLL_REFCLK_SEL(x) ((x) << 26) 113 # define SPLL_REFCLK_SEL_MASK (3 << 26) 114 115 #define CG_SPLL_SPREAD_SPECTRUM 0x620 116 #define SSEN (1 << 0) 117 #define CLK_S(x) ((x) << 4) 118 #define CLK_S_MASK (0xfff << 4) 119 #define CLK_S_SHIFT 4 120 #define CG_SPLL_SPREAD_SPECTRUM_2 0x624 121 #define CLK_V(x) ((x) << 0) 122 #define CLK_V_MASK (0x3ffffff << 0) 123 #define CLK_V_SHIFT 0 124 125 #define CG_SPLL_AUTOSCALE_CNTL 0x62c 126 # define AUTOSCALE_ON_SS_CLEAR (1 << 9) 127 128 /* discrete uvd clocks */ 129 #define CG_UPLL_FUNC_CNTL 0x634 130 # define UPLL_RESET_MASK 0x00000001 131 # define UPLL_SLEEP_MASK 0x00000002 132 # define UPLL_BYPASS_EN_MASK 0x00000004 133 # define UPLL_CTLREQ_MASK 0x00000008 134 # define UPLL_VCO_MODE_MASK 0x00000600 135 # define UPLL_REF_DIV_MASK 0x003F0000 136 # define UPLL_CTLACK_MASK 0x40000000 137 # define UPLL_CTLACK2_MASK 0x80000000 138 #define CG_UPLL_FUNC_CNTL_2 0x638 139 # define UPLL_PDIV_A(x) ((x) << 0) 140 # define UPLL_PDIV_A_MASK 0x0000007F 141 # define UPLL_PDIV_B(x) ((x) << 8) 142 # define UPLL_PDIV_B_MASK 0x00007F00 143 # define VCLK_SRC_SEL(x) ((x) << 20) 144 # define VCLK_SRC_SEL_MASK 0x01F00000 145 # define DCLK_SRC_SEL(x) ((x) << 25) 146 # define DCLK_SRC_SEL_MASK 0x3E000000 147 #define CG_UPLL_FUNC_CNTL_3 0x63C 148 # define UPLL_FB_DIV(x) ((x) << 0) 149 # define UPLL_FB_DIV_MASK 0x01FFFFFF 150 #define CG_UPLL_FUNC_CNTL_4 0x644 151 # define UPLL_SPARE_ISPARE9 0x00020000 152 #define CG_UPLL_FUNC_CNTL_5 0x648 153 # define RESET_ANTI_MUX_MASK 0x00000200 154 #define CG_UPLL_SPREAD_SPECTRUM 0x650 155 # define SSEN_MASK 0x00000001 156 157 #define MPLL_BYPASSCLK_SEL 0x65c 158 # define MPLL_CLKOUT_SEL(x) ((x) << 8) 159 # define MPLL_CLKOUT_SEL_MASK 0xFF00 160 161 #define CG_CLKPIN_CNTL 0x660 162 # define XTALIN_DIVIDE (1 << 1) 163 # define BCLK_AS_XCLK (1 << 2) 164 #define CG_CLKPIN_CNTL_2 0x664 165 # define FORCE_BIF_REFCLK_EN (1 << 3) 166 # define MUX_TCLK_TO_XCLK (1 << 8) 167 168 #define THM_CLK_CNTL 0x66c 169 # define CMON_CLK_SEL(x) ((x) << 0) 170 # define CMON_CLK_SEL_MASK 0xFF 171 # define TMON_CLK_SEL(x) ((x) << 8) 172 # define TMON_CLK_SEL_MASK 0xFF00 173 #define MISC_CLK_CNTL 0x670 174 # define DEEP_SLEEP_CLK_SEL(x) ((x) << 0) 175 # define DEEP_SLEEP_CLK_SEL_MASK 0xFF 176 # define ZCLK_SEL(x) ((x) << 8) 177 # define ZCLK_SEL_MASK 0xFF00 178 179 #define CG_THERMAL_CTRL 0x700 180 #define DPM_EVENT_SRC(x) ((x) << 0) 181 #define DPM_EVENT_SRC_MASK (7 << 0) 182 #define DIG_THERM_DPM(x) ((x) << 14) 183 #define DIG_THERM_DPM_MASK 0x003FC000 184 #define DIG_THERM_DPM_SHIFT 14 185 #define CG_THERMAL_STATUS 0x704 186 #define FDO_PWM_DUTY(x) ((x) << 9) 187 #define FDO_PWM_DUTY_MASK (0xff << 9) 188 #define FDO_PWM_DUTY_SHIFT 9 189 #define CG_THERMAL_INT 0x708 190 #define DIG_THERM_INTH(x) ((x) << 8) 191 #define DIG_THERM_INTH_MASK 0x0000FF00 192 #define DIG_THERM_INTH_SHIFT 8 193 #define DIG_THERM_INTL(x) ((x) << 16) 194 #define DIG_THERM_INTL_MASK 0x00FF0000 195 #define DIG_THERM_INTL_SHIFT 16 196 #define THERM_INT_MASK_HIGH (1 << 24) 197 #define THERM_INT_MASK_LOW (1 << 25) 198 199 #define CG_MULT_THERMAL_CTRL 0x710 200 #define TEMP_SEL(x) ((x) << 20) 201 #define TEMP_SEL_MASK (0xff << 20) 202 #define TEMP_SEL_SHIFT 20 203 #define CG_MULT_THERMAL_STATUS 0x714 204 #define ASIC_MAX_TEMP(x) ((x) << 0) 205 #define ASIC_MAX_TEMP_MASK 0x000001ff 206 #define ASIC_MAX_TEMP_SHIFT 0 207 #define CTF_TEMP(x) ((x) << 9) 208 #define CTF_TEMP_MASK 0x0003fe00 209 #define CTF_TEMP_SHIFT 9 210 211 #define CG_FDO_CTRL0 0x754 212 #define FDO_STATIC_DUTY(x) ((x) << 0) 213 #define FDO_STATIC_DUTY_MASK 0x000000FF 214 #define FDO_STATIC_DUTY_SHIFT 0 215 #define CG_FDO_CTRL1 0x758 216 #define FMAX_DUTY100(x) ((x) << 0) 217 #define FMAX_DUTY100_MASK 0x000000FF 218 #define FMAX_DUTY100_SHIFT 0 219 #define CG_FDO_CTRL2 0x75C 220 #define TMIN(x) ((x) << 0) 221 #define TMIN_MASK 0x000000FF 222 #define TMIN_SHIFT 0 223 #define FDO_PWM_MODE(x) ((x) << 11) 224 #define FDO_PWM_MODE_MASK (7 << 11) 225 #define FDO_PWM_MODE_SHIFT 11 226 #define TACH_PWM_RESP_RATE(x) ((x) << 25) 227 #define TACH_PWM_RESP_RATE_MASK (0x7fU << 25) 228 #define TACH_PWM_RESP_RATE_SHIFT 25 229 230 #define CG_TACH_CTRL 0x770 231 # define EDGE_PER_REV(x) ((x) << 0) 232 # define EDGE_PER_REV_MASK (0x7 << 0) 233 # define EDGE_PER_REV_SHIFT 0 234 # define TARGET_PERIOD(x) ((x) << 3) 235 # define TARGET_PERIOD_MASK 0xfffffff8 236 # define TARGET_PERIOD_SHIFT 3 237 #define CG_TACH_STATUS 0x774 238 # define TACH_PERIOD(x) ((x) << 0) 239 # define TACH_PERIOD_MASK 0xffffffff 240 # define TACH_PERIOD_SHIFT 0 241 242 #define GENERAL_PWRMGT 0x780 243 # define GLOBAL_PWRMGT_EN (1 << 0) 244 # define STATIC_PM_EN (1 << 1) 245 # define THERMAL_PROTECTION_DIS (1 << 2) 246 # define THERMAL_PROTECTION_TYPE (1 << 3) 247 # define SW_SMIO_INDEX(x) ((x) << 6) 248 # define SW_SMIO_INDEX_MASK (1 << 6) 249 # define SW_SMIO_INDEX_SHIFT 6 250 # define VOLT_PWRMGT_EN (1 << 10) 251 # define DYN_SPREAD_SPECTRUM_EN (1 << 23) 252 #define CG_TPC 0x784 253 #define SCLK_PWRMGT_CNTL 0x788 254 # define SCLK_PWRMGT_OFF (1 << 0) 255 # define SCLK_LOW_D1 (1 << 1) 256 # define FIR_RESET (1 << 4) 257 # define FIR_FORCE_TREND_SEL (1 << 5) 258 # define FIR_TREND_MODE (1 << 6) 259 # define DYN_GFX_CLK_OFF_EN (1 << 7) 260 # define GFX_CLK_FORCE_ON (1 << 8) 261 # define GFX_CLK_REQUEST_OFF (1 << 9) 262 # define GFX_CLK_FORCE_OFF (1 << 10) 263 # define GFX_CLK_OFF_ACPI_D1 (1 << 11) 264 # define GFX_CLK_OFF_ACPI_D2 (1 << 12) 265 # define GFX_CLK_OFF_ACPI_D3 (1 << 13) 266 # define DYN_LIGHT_SLEEP_EN (1 << 14) 267 268 #define TARGET_AND_CURRENT_PROFILE_INDEX 0x798 269 # define CURRENT_STATE_INDEX_MASK (0xf << 4) 270 # define CURRENT_STATE_INDEX_SHIFT 4 271 272 #define CG_FTV 0x7bc 273 274 #define CG_FFCT_0 0x7c0 275 # define UTC_0(x) ((x) << 0) 276 # define UTC_0_MASK (0x3ff << 0) 277 # define DTC_0(x) ((x) << 10) 278 # define DTC_0_MASK (0x3ff << 10) 279 280 #define CG_BSP 0x7fc 281 # define BSP(x) ((x) << 0) 282 # define BSP_MASK (0xffff << 0) 283 # define BSU(x) ((x) << 16) 284 # define BSU_MASK (0xf << 16) 285 #define CG_AT 0x800 286 # define CG_R(x) ((x) << 0) 287 # define CG_R_MASK (0xffff << 0) 288 # define CG_L(x) ((x) << 16) 289 # define CG_L_MASK (0xffff << 16) 290 291 #define CG_GIT 0x804 292 # define CG_GICST(x) ((x) << 0) 293 # define CG_GICST_MASK (0xffff << 0) 294 # define CG_GIPOT(x) ((x) << 16) 295 # define CG_GIPOT_MASK (0xffff << 16) 296 297 #define CG_SSP 0x80c 298 # define SST(x) ((x) << 0) 299 # define SST_MASK (0xffff << 0) 300 # define SSTU(x) ((x) << 16) 301 # define SSTU_MASK (0xf << 16) 302 303 #define CG_DISPLAY_GAP_CNTL 0x828 304 # define DISP1_GAP(x) ((x) << 0) 305 # define DISP1_GAP_MASK (3 << 0) 306 # define DISP2_GAP(x) ((x) << 2) 307 # define DISP2_GAP_MASK (3 << 2) 308 # define VBI_TIMER_COUNT(x) ((x) << 4) 309 # define VBI_TIMER_COUNT_MASK (0x3fff << 4) 310 # define VBI_TIMER_UNIT(x) ((x) << 20) 311 # define VBI_TIMER_UNIT_MASK (7 << 20) 312 # define DISP1_GAP_MCHG(x) ((x) << 24) 313 # define DISP1_GAP_MCHG_MASK (3 << 24) 314 # define DISP2_GAP_MCHG(x) ((x) << 26) 315 # define DISP2_GAP_MCHG_MASK (3 << 26) 316 317 #define CG_ULV_CONTROL 0x878 318 #define CG_ULV_PARAMETER 0x87c 319 320 #define SMC_SCRATCH0 0x884 321 322 #define CG_CAC_CTRL 0x8b8 323 # define CAC_WINDOW(x) ((x) << 0) 324 # define CAC_WINDOW_MASK 0x00ffffff 325 326 #define DMIF_ADDR_CONFIG 0xBD4 327 328 #define DMIF_ADDR_CALC 0xC00 329 330 #define PIPE0_DMIF_BUFFER_CONTROL 0x0ca0 331 # define DMIF_BUFFERS_ALLOCATED(x) ((x) << 0) 332 # define DMIF_BUFFERS_ALLOCATED_COMPLETED (1 << 4) 333 334 #define SRBM_STATUS 0xE50 335 #define GRBM_RQ_PENDING (1 << 5) 336 #define VMC_BUSY (1 << 8) 337 #define MCB_BUSY (1 << 9) 338 #define MCB_NON_DISPLAY_BUSY (1 << 10) 339 #define MCC_BUSY (1 << 11) 340 #define MCD_BUSY (1 << 12) 341 #define SEM_BUSY (1 << 14) 342 #define IH_BUSY (1 << 17) 343 344 #define SRBM_SOFT_RESET 0x0E60 345 #define SOFT_RESET_BIF (1 << 1) 346 #define SOFT_RESET_DC (1 << 5) 347 #define SOFT_RESET_DMA1 (1 << 6) 348 #define SOFT_RESET_GRBM (1 << 8) 349 #define SOFT_RESET_HDP (1 << 9) 350 #define SOFT_RESET_IH (1 << 10) 351 #define SOFT_RESET_MC (1 << 11) 352 #define SOFT_RESET_ROM (1 << 14) 353 #define SOFT_RESET_SEM (1 << 15) 354 #define SOFT_RESET_VMC (1 << 17) 355 #define SOFT_RESET_DMA (1 << 20) 356 #define SOFT_RESET_TST (1 << 21) 357 #define SOFT_RESET_REGBB (1 << 22) 358 #define SOFT_RESET_ORB (1 << 23) 359 360 #define CC_SYS_RB_BACKEND_DISABLE 0xe80 361 #define GC_USER_SYS_RB_BACKEND_DISABLE 0xe84 362 363 #define SRBM_READ_ERROR 0xE98 364 #define SRBM_INT_CNTL 0xEA0 365 #define SRBM_INT_ACK 0xEA8 366 367 #define SRBM_STATUS2 0x0EC4 368 #define DMA_BUSY (1 << 5) 369 #define DMA1_BUSY (1 << 6) 370 371 #define VM_L2_CNTL 0x1400 372 #define ENABLE_L2_CACHE (1 << 0) 373 #define ENABLE_L2_FRAGMENT_PROCESSING (1 << 1) 374 #define L2_CACHE_PTE_ENDIAN_SWAP_MODE(x) ((x) << 2) 375 #define L2_CACHE_PDE_ENDIAN_SWAP_MODE(x) ((x) << 4) 376 #define ENABLE_L2_PTE_CACHE_LRU_UPDATE_BY_WRITE (1 << 9) 377 #define ENABLE_L2_PDE0_CACHE_LRU_UPDATE_BY_WRITE (1 << 10) 378 #define EFFECTIVE_L2_QUEUE_SIZE(x) (((x) & 7) << 15) 379 #define CONTEXT1_IDENTITY_ACCESS_MODE(x) (((x) & 3) << 19) 380 #define VM_L2_CNTL2 0x1404 381 #define INVALIDATE_ALL_L1_TLBS (1 << 0) 382 #define INVALIDATE_L2_CACHE (1 << 1) 383 #define INVALIDATE_CACHE_MODE(x) ((x) << 26) 384 #define INVALIDATE_PTE_AND_PDE_CACHES 0 385 #define INVALIDATE_ONLY_PTE_CACHES 1 386 #define INVALIDATE_ONLY_PDE_CACHES 2 387 #define VM_L2_CNTL3 0x1408 388 #define BANK_SELECT(x) ((x) << 0) 389 #define L2_CACHE_UPDATE_MODE(x) ((x) << 6) 390 #define L2_CACHE_BIGK_FRAGMENT_SIZE(x) ((x) << 15) 391 #define L2_CACHE_BIGK_ASSOCIATIVITY (1 << 20) 392 #define VM_L2_STATUS 0x140C 393 #define L2_BUSY (1 << 0) 394 #define VM_CONTEXT0_CNTL 0x1410 395 #define ENABLE_CONTEXT (1 << 0) 396 #define PAGE_TABLE_DEPTH(x) (((x) & 3) << 1) 397 #define RANGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 3) 398 #define RANGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 4) 399 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 6) 400 #define DUMMY_PAGE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 7) 401 #define PDE0_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 9) 402 #define PDE0_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 10) 403 #define VALID_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 12) 404 #define VALID_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 13) 405 #define READ_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 15) 406 #define READ_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 16) 407 #define WRITE_PROTECTION_FAULT_ENABLE_INTERRUPT (1 << 18) 408 #define WRITE_PROTECTION_FAULT_ENABLE_DEFAULT (1 << 19) 409 #define PAGE_TABLE_BLOCK_SIZE(x) (((x) & 0xF) << 24) 410 #define VM_CONTEXT1_CNTL 0x1414 411 #define VM_CONTEXT0_CNTL2 0x1430 412 #define VM_CONTEXT1_CNTL2 0x1434 413 #define VM_CONTEXT8_PAGE_TABLE_BASE_ADDR 0x1438 414 #define VM_CONTEXT9_PAGE_TABLE_BASE_ADDR 0x143c 415 #define VM_CONTEXT10_PAGE_TABLE_BASE_ADDR 0x1440 416 #define VM_CONTEXT11_PAGE_TABLE_BASE_ADDR 0x1444 417 #define VM_CONTEXT12_PAGE_TABLE_BASE_ADDR 0x1448 418 #define VM_CONTEXT13_PAGE_TABLE_BASE_ADDR 0x144c 419 #define VM_CONTEXT14_PAGE_TABLE_BASE_ADDR 0x1450 420 #define VM_CONTEXT15_PAGE_TABLE_BASE_ADDR 0x1454 421 422 #define VM_CONTEXT1_PROTECTION_FAULT_ADDR 0x14FC 423 #define VM_CONTEXT1_PROTECTION_FAULT_STATUS 0x14DC 424 #define PROTECTIONS_MASK (0xf << 0) 425 #define PROTECTIONS_SHIFT 0 426 /* bit 0: range 427 * bit 1: pde0 428 * bit 2: valid 429 * bit 3: read 430 * bit 4: write 431 */ 432 #define MEMORY_CLIENT_ID_MASK (0xff << 12) 433 #define MEMORY_CLIENT_ID_SHIFT 12 434 #define MEMORY_CLIENT_RW_MASK (1 << 24) 435 #define MEMORY_CLIENT_RW_SHIFT 24 436 #define FAULT_VMID_MASK (0xf << 25) 437 #define FAULT_VMID_SHIFT 25 438 439 #define VM_INVALIDATE_REQUEST 0x1478 440 #define VM_INVALIDATE_RESPONSE 0x147c 441 442 #define VM_CONTEXT0_PROTECTION_FAULT_DEFAULT_ADDR 0x1518 443 #define VM_CONTEXT1_PROTECTION_FAULT_DEFAULT_ADDR 0x151c 444 445 #define VM_CONTEXT0_PAGE_TABLE_BASE_ADDR 0x153c 446 #define VM_CONTEXT1_PAGE_TABLE_BASE_ADDR 0x1540 447 #define VM_CONTEXT2_PAGE_TABLE_BASE_ADDR 0x1544 448 #define VM_CONTEXT3_PAGE_TABLE_BASE_ADDR 0x1548 449 #define VM_CONTEXT4_PAGE_TABLE_BASE_ADDR 0x154c 450 #define VM_CONTEXT5_PAGE_TABLE_BASE_ADDR 0x1550 451 #define VM_CONTEXT6_PAGE_TABLE_BASE_ADDR 0x1554 452 #define VM_CONTEXT7_PAGE_TABLE_BASE_ADDR 0x1558 453 #define VM_CONTEXT0_PAGE_TABLE_START_ADDR 0x155c 454 #define VM_CONTEXT1_PAGE_TABLE_START_ADDR 0x1560 455 456 #define VM_CONTEXT0_PAGE_TABLE_END_ADDR 0x157C 457 #define VM_CONTEXT1_PAGE_TABLE_END_ADDR 0x1580 458 459 #define VM_L2_CG 0x15c0 460 #define MC_CG_ENABLE (1 << 18) 461 #define MC_LS_ENABLE (1 << 19) 462 463 #define MC_SHARED_CHMAP 0x2004 464 #define NOOFCHAN_SHIFT 12 465 #define NOOFCHAN_MASK 0x0000f000 466 #define MC_SHARED_CHREMAP 0x2008 467 468 #define MC_VM_FB_LOCATION 0x2024 469 #define MC_VM_AGP_TOP 0x2028 470 #define MC_VM_AGP_BOT 0x202C 471 #define MC_VM_AGP_BASE 0x2030 472 #define MC_VM_SYSTEM_APERTURE_LOW_ADDR 0x2034 473 #define MC_VM_SYSTEM_APERTURE_HIGH_ADDR 0x2038 474 #define MC_VM_SYSTEM_APERTURE_DEFAULT_ADDR 0x203C 475 476 #define MC_VM_MX_L1_TLB_CNTL 0x2064 477 #define ENABLE_L1_TLB (1 << 0) 478 #define ENABLE_L1_FRAGMENT_PROCESSING (1 << 1) 479 #define SYSTEM_ACCESS_MODE_PA_ONLY (0 << 3) 480 #define SYSTEM_ACCESS_MODE_USE_SYS_MAP (1 << 3) 481 #define SYSTEM_ACCESS_MODE_IN_SYS (2 << 3) 482 #define SYSTEM_ACCESS_MODE_NOT_IN_SYS (3 << 3) 483 #define SYSTEM_APERTURE_UNMAPPED_ACCESS_PASS_THRU (0 << 5) 484 #define ENABLE_ADVANCED_DRIVER_MODEL (1 << 6) 485 486 #define MC_SHARED_BLACKOUT_CNTL 0x20ac 487 488 #define MC_HUB_MISC_HUB_CG 0x20b8 489 #define MC_HUB_MISC_VM_CG 0x20bc 490 491 #define MC_HUB_MISC_SIP_CG 0x20c0 492 493 #define MC_XPB_CLK_GAT 0x2478 494 495 #define MC_CITF_MISC_RD_CG 0x2648 496 #define MC_CITF_MISC_WR_CG 0x264c 497 #define MC_CITF_MISC_VM_CG 0x2650 498 499 #define MC_ARB_RAMCFG 0x2760 500 #define NOOFBANK_SHIFT 0 501 #define NOOFBANK_MASK 0x00000003 502 #define NOOFRANK_SHIFT 2 503 #define NOOFRANK_MASK 0x00000004 504 #define NOOFROWS_SHIFT 3 505 #define NOOFROWS_MASK 0x00000038 506 #define NOOFCOLS_SHIFT 6 507 #define NOOFCOLS_MASK 0x000000C0 508 #define CHANSIZE_SHIFT 8 509 #define CHANSIZE_MASK 0x00000100 510 #define CHANSIZE_OVERRIDE (1 << 11) 511 #define NOOFGROUPS_SHIFT 12 512 #define NOOFGROUPS_MASK 0x00001000 513 514 #define MC_ARB_DRAM_TIMING 0x2774 515 #define MC_ARB_DRAM_TIMING2 0x2778 516 517 #define MC_ARB_BURST_TIME 0x2808 518 #define STATE0(x) ((x) << 0) 519 #define STATE0_MASK (0x1f << 0) 520 #define STATE0_SHIFT 0 521 #define STATE1(x) ((x) << 5) 522 #define STATE1_MASK (0x1f << 5) 523 #define STATE1_SHIFT 5 524 #define STATE2(x) ((x) << 10) 525 #define STATE2_MASK (0x1f << 10) 526 #define STATE2_SHIFT 10 527 #define STATE3(x) ((x) << 15) 528 #define STATE3_MASK (0x1f << 15) 529 #define STATE3_SHIFT 15 530 531 #define MC_SEQ_TRAIN_WAKEUP_CNTL 0x28e8 532 #define TRAIN_DONE_D0 (1 << 30) 533 #define TRAIN_DONE_D1 (1U << 31) 534 535 #define MC_SEQ_SUP_CNTL 0x28c8 536 #define RUN_MASK (1 << 0) 537 #define MC_SEQ_SUP_PGM 0x28cc 538 #define MC_PMG_AUTO_CMD 0x28d0 539 540 #define MC_IO_PAD_CNTL_D0 0x29d0 541 #define MEM_FALL_OUT_CMD (1 << 8) 542 543 #define MC_SEQ_RAS_TIMING 0x28a0 544 #define MC_SEQ_CAS_TIMING 0x28a4 545 #define MC_SEQ_MISC_TIMING 0x28a8 546 #define MC_SEQ_MISC_TIMING2 0x28ac 547 #define MC_SEQ_PMG_TIMING 0x28b0 548 #define MC_SEQ_RD_CTL_D0 0x28b4 549 #define MC_SEQ_RD_CTL_D1 0x28b8 550 #define MC_SEQ_WR_CTL_D0 0x28bc 551 #define MC_SEQ_WR_CTL_D1 0x28c0 552 553 #define MC_SEQ_MISC0 0x2a00 554 #define MC_SEQ_MISC0_VEN_ID_SHIFT 8 555 #define MC_SEQ_MISC0_VEN_ID_MASK 0x00000f00 556 #define MC_SEQ_MISC0_VEN_ID_VALUE 3 557 #define MC_SEQ_MISC0_REV_ID_SHIFT 12 558 #define MC_SEQ_MISC0_REV_ID_MASK 0x0000f000 559 #define MC_SEQ_MISC0_REV_ID_VALUE 1 560 #define MC_SEQ_MISC0_GDDR5_SHIFT 28 561 #define MC_SEQ_MISC0_GDDR5_MASK 0xf0000000 562 #define MC_SEQ_MISC0_GDDR5_VALUE 5 563 #define MC_SEQ_MISC1 0x2a04 564 #define MC_SEQ_RESERVE_M 0x2a08 565 #define MC_PMG_CMD_EMRS 0x2a0c 566 567 #define MC_SEQ_IO_DEBUG_INDEX 0x2a44 568 #define MC_SEQ_IO_DEBUG_DATA 0x2a48 569 570 #define MC_SEQ_MISC5 0x2a54 571 #define MC_SEQ_MISC6 0x2a58 572 573 #define MC_SEQ_MISC7 0x2a64 574 575 #define MC_SEQ_RAS_TIMING_LP 0x2a6c 576 #define MC_SEQ_CAS_TIMING_LP 0x2a70 577 #define MC_SEQ_MISC_TIMING_LP 0x2a74 578 #define MC_SEQ_MISC_TIMING2_LP 0x2a78 579 #define MC_SEQ_WR_CTL_D0_LP 0x2a7c 580 #define MC_SEQ_WR_CTL_D1_LP 0x2a80 581 #define MC_SEQ_PMG_CMD_EMRS_LP 0x2a84 582 #define MC_SEQ_PMG_CMD_MRS_LP 0x2a88 583 584 #define MC_PMG_CMD_MRS 0x2aac 585 586 #define MC_SEQ_RD_CTL_D0_LP 0x2b1c 587 #define MC_SEQ_RD_CTL_D1_LP 0x2b20 588 589 #define MC_PMG_CMD_MRS1 0x2b44 590 #define MC_SEQ_PMG_CMD_MRS1_LP 0x2b48 591 #define MC_SEQ_PMG_TIMING_LP 0x2b4c 592 593 #define MC_SEQ_WR_CTL_2 0x2b54 594 #define MC_SEQ_WR_CTL_2_LP 0x2b58 595 #define MC_PMG_CMD_MRS2 0x2b5c 596 #define MC_SEQ_PMG_CMD_MRS2_LP 0x2b60 597 598 #define MCLK_PWRMGT_CNTL 0x2ba0 599 # define DLL_SPEED(x) ((x) << 0) 600 # define DLL_SPEED_MASK (0x1f << 0) 601 # define DLL_READY (1 << 6) 602 # define MC_INT_CNTL (1 << 7) 603 # define MRDCK0_PDNB (1 << 8) 604 # define MRDCK1_PDNB (1 << 9) 605 # define MRDCK0_RESET (1 << 16) 606 # define MRDCK1_RESET (1 << 17) 607 # define DLL_READY_READ (1 << 24) 608 #define DLL_CNTL 0x2ba4 609 # define MRDCK0_BYPASS (1 << 24) 610 # define MRDCK1_BYPASS (1 << 25) 611 612 #define MPLL_CNTL_MODE 0x2bb0 613 # define MPLL_MCLK_SEL (1 << 11) 614 #define MPLL_FUNC_CNTL 0x2bb4 615 #define BWCTRL(x) ((x) << 20) 616 #define BWCTRL_MASK (0xff << 20) 617 #define MPLL_FUNC_CNTL_1 0x2bb8 618 #define VCO_MODE(x) ((x) << 0) 619 #define VCO_MODE_MASK (3 << 0) 620 #define CLKFRAC(x) ((x) << 4) 621 #define CLKFRAC_MASK (0xfff << 4) 622 #define CLKF(x) ((x) << 16) 623 #define CLKF_MASK (0xfff << 16) 624 #define MPLL_FUNC_CNTL_2 0x2bbc 625 #define MPLL_AD_FUNC_CNTL 0x2bc0 626 #define YCLK_POST_DIV(x) ((x) << 0) 627 #define YCLK_POST_DIV_MASK (7 << 0) 628 #define MPLL_DQ_FUNC_CNTL 0x2bc4 629 #define YCLK_SEL(x) ((x) << 4) 630 #define YCLK_SEL_MASK (1 << 4) 631 632 #define MPLL_SS1 0x2bcc 633 #define CLKV(x) ((x) << 0) 634 #define CLKV_MASK (0x3ffffff << 0) 635 #define MPLL_SS2 0x2bd0 636 #define CLKS(x) ((x) << 0) 637 #define CLKS_MASK (0xfff << 0) 638 639 #define HDP_HOST_PATH_CNTL 0x2C00 640 #define CLOCK_GATING_DIS (1 << 23) 641 #define HDP_NONSURFACE_BASE 0x2C04 642 #define HDP_NONSURFACE_INFO 0x2C08 643 #define HDP_NONSURFACE_SIZE 0x2C0C 644 645 #define HDP_ADDR_CONFIG 0x2F48 646 #define HDP_MISC_CNTL 0x2F4C 647 #define HDP_FLUSH_INVALIDATE_CACHE (1 << 0) 648 #define HDP_MEM_POWER_LS 0x2F50 649 #define HDP_LS_ENABLE (1 << 0) 650 651 #define ATC_MISC_CG 0x3350 652 653 #define IH_RB_CNTL 0x3e00 654 # define IH_RB_ENABLE (1 << 0) 655 # define IH_IB_SIZE(x) ((x) << 1) /* log2 */ 656 # define IH_RB_FULL_DRAIN_ENABLE (1 << 6) 657 # define IH_WPTR_WRITEBACK_ENABLE (1 << 8) 658 # define IH_WPTR_WRITEBACK_TIMER(x) ((x) << 9) /* log2 */ 659 # define IH_WPTR_OVERFLOW_ENABLE (1 << 16) 660 # define IH_WPTR_OVERFLOW_CLEAR (1U << 31) 661 #define IH_RB_BASE 0x3e04 662 #define IH_RB_RPTR 0x3e08 663 #define IH_RB_WPTR 0x3e0c 664 # define RB_OVERFLOW (1 << 0) 665 # define WPTR_OFFSET_MASK 0x3fffc 666 #define IH_RB_WPTR_ADDR_HI 0x3e10 667 #define IH_RB_WPTR_ADDR_LO 0x3e14 668 #define IH_CNTL 0x3e18 669 # define ENABLE_INTR (1 << 0) 670 # define IH_MC_SWAP(x) ((x) << 1) 671 # define IH_MC_SWAP_NONE 0 672 # define IH_MC_SWAP_16BIT 1 673 # define IH_MC_SWAP_32BIT 2 674 # define IH_MC_SWAP_64BIT 3 675 # define RPTR_REARM (1 << 4) 676 # define MC_WRREQ_CREDIT(x) ((x) << 15) 677 # define MC_WR_CLEAN_CNT(x) ((x) << 20) 678 # define MC_VMID(x) ((x) << 25) 679 680 #define CONFIG_MEMSIZE 0x5428 681 682 #define INTERRUPT_CNTL 0x5468 683 # define IH_DUMMY_RD_OVERRIDE (1 << 0) 684 # define IH_DUMMY_RD_EN (1 << 1) 685 # define IH_REQ_NONSNOOP_EN (1 << 3) 686 # define GEN_IH_INT_EN (1 << 8) 687 #define INTERRUPT_CNTL2 0x546c 688 689 #define HDP_MEM_COHERENCY_FLUSH_CNTL 0x5480 690 691 #define BIF_FB_EN 0x5490 692 #define FB_READ_EN (1 << 0) 693 #define FB_WRITE_EN (1 << 1) 694 695 #define HDP_REG_COHERENCY_FLUSH_CNTL 0x54A0 696 697 /* DCE6 ELD audio interface */ 698 #define AZ_F0_CODEC_ENDPOINT_INDEX 0x5E00 699 # define AZ_ENDPOINT_REG_INDEX(x) (((x) & 0xff) << 0) 700 # define AZ_ENDPOINT_REG_WRITE_EN (1 << 8) 701 #define AZ_F0_CODEC_ENDPOINT_DATA 0x5E04 702 703 #define AZ_F0_CODEC_PIN_CONTROL_CHANNEL_SPEAKER 0x25 704 #define SPEAKER_ALLOCATION(x) (((x) & 0x7f) << 0) 705 #define SPEAKER_ALLOCATION_MASK (0x7f << 0) 706 #define SPEAKER_ALLOCATION_SHIFT 0 707 #define HDMI_CONNECTION (1 << 16) 708 #define DP_CONNECTION (1 << 17) 709 710 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR0 0x28 /* LPCM */ 711 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR1 0x29 /* AC3 */ 712 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR2 0x2A /* MPEG1 */ 713 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR3 0x2B /* MP3 */ 714 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR4 0x2C /* MPEG2 */ 715 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR5 0x2D /* AAC */ 716 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR6 0x2E /* DTS */ 717 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR7 0x2F /* ATRAC */ 718 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR8 0x30 /* one bit audio - leave at 0 (default) */ 719 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR9 0x31 /* Dolby Digital */ 720 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR10 0x32 /* DTS-HD */ 721 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR11 0x33 /* MAT-MLP */ 722 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR12 0x34 /* DTS */ 723 #define AZ_F0_CODEC_PIN_CONTROL_AUDIO_DESCRIPTOR13 0x35 /* WMA Pro */ 724 # define MAX_CHANNELS(x) (((x) & 0x7) << 0) 725 /* max channels minus one. 7 = 8 channels */ 726 # define SUPPORTED_FREQUENCIES(x) (((x) & 0xff) << 8) 727 # define DESCRIPTOR_BYTE_2(x) (((x) & 0xff) << 16) 728 # define SUPPORTED_FREQUENCIES_STEREO(x) (((x) & 0xff) << 24) /* LPCM only */ 729 /* SUPPORTED_FREQUENCIES, SUPPORTED_FREQUENCIES_STEREO 730 * bit0 = 32 kHz 731 * bit1 = 44.1 kHz 732 * bit2 = 48 kHz 733 * bit3 = 88.2 kHz 734 * bit4 = 96 kHz 735 * bit5 = 176.4 kHz 736 * bit6 = 192 kHz 737 */ 738 739 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_LIPSYNC 0x37 740 # define VIDEO_LIPSYNC(x) (((x) & 0xff) << 0) 741 # define AUDIO_LIPSYNC(x) (((x) & 0xff) << 8) 742 /* VIDEO_LIPSYNC, AUDIO_LIPSYNC 743 * 0 = invalid 744 * x = legal delay value 745 * 255 = sync not supported 746 */ 747 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_HBR 0x38 748 # define HBR_CAPABLE (1 << 0) /* enabled by default */ 749 750 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO0 0x3a 751 # define MANUFACTURER_ID(x) (((x) & 0xffff) << 0) 752 # define PRODUCT_ID(x) (((x) & 0xffff) << 16) 753 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO1 0x3b 754 # define SINK_DESCRIPTION_LEN(x) (((x) & 0xff) << 0) 755 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO2 0x3c 756 # define PORT_ID0(x) (((x) & 0xffffffff) << 0) 757 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO3 0x3d 758 # define PORT_ID1(x) (((x) & 0xffffffff) << 0) 759 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO4 0x3e 760 # define DESCRIPTION0(x) (((x) & 0xff) << 0) 761 # define DESCRIPTION1(x) (((x) & 0xff) << 8) 762 # define DESCRIPTION2(x) (((x) & 0xff) << 16) 763 # define DESCRIPTION3(x) (((x) & 0xff) << 24) 764 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO5 0x3f 765 # define DESCRIPTION4(x) (((x) & 0xff) << 0) 766 # define DESCRIPTION5(x) (((x) & 0xff) << 8) 767 # define DESCRIPTION6(x) (((x) & 0xff) << 16) 768 # define DESCRIPTION7(x) (((x) & 0xff) << 24) 769 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO6 0x40 770 # define DESCRIPTION8(x) (((x) & 0xff) << 0) 771 # define DESCRIPTION9(x) (((x) & 0xff) << 8) 772 # define DESCRIPTION10(x) (((x) & 0xff) << 16) 773 # define DESCRIPTION11(x) (((x) & 0xff) << 24) 774 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO7 0x41 775 # define DESCRIPTION12(x) (((x) & 0xff) << 0) 776 # define DESCRIPTION13(x) (((x) & 0xff) << 8) 777 # define DESCRIPTION14(x) (((x) & 0xff) << 16) 778 # define DESCRIPTION15(x) (((x) & 0xff) << 24) 779 #define AZ_F0_CODEC_PIN_CONTROL_SINK_INFO8 0x42 780 # define DESCRIPTION16(x) (((x) & 0xff) << 0) 781 # define DESCRIPTION17(x) (((x) & 0xff) << 8) 782 783 #define AZ_F0_CODEC_PIN_CONTROL_HOT_PLUG_CONTROL 0x54 784 # define AUDIO_ENABLED (1U << 31) 785 786 #define AZ_F0_CODEC_PIN_CONTROL_RESPONSE_CONFIGURATION_DEFAULT 0x56 787 #define PORT_CONNECTIVITY_MASK (3U << 30) 788 #define PORT_CONNECTIVITY_SHIFT 30 789 790 #define DC_LB_MEMORY_SPLIT 0x6b0c 791 #define DC_LB_MEMORY_CONFIG(x) ((x) << 20) 792 793 #define PRIORITY_A_CNT 0x6b18 794 #define PRIORITY_MARK_MASK 0x7fff 795 #define PRIORITY_OFF (1 << 16) 796 #define PRIORITY_ALWAYS_ON (1 << 20) 797 #define PRIORITY_B_CNT 0x6b1c 798 799 #define DPG_PIPE_ARBITRATION_CONTROL3 0x6cc8 800 # define LATENCY_WATERMARK_MASK(x) ((x) << 16) 801 #define DPG_PIPE_LATENCY_CONTROL 0x6ccc 802 # define LATENCY_LOW_WATERMARK(x) ((x) << 0) 803 # define LATENCY_HIGH_WATERMARK(x) ((x) << 16) 804 805 /* 0x6bb8, 0x77b8, 0x103b8, 0x10fb8, 0x11bb8, 0x127b8 */ 806 #define VLINE_STATUS 0x6bb8 807 # define VLINE_OCCURRED (1 << 0) 808 # define VLINE_ACK (1 << 4) 809 # define VLINE_STAT (1 << 12) 810 # define VLINE_INTERRUPT (1 << 16) 811 # define VLINE_INTERRUPT_TYPE (1 << 17) 812 /* 0x6bbc, 0x77bc, 0x103bc, 0x10fbc, 0x11bbc, 0x127bc */ 813 #define VBLANK_STATUS 0x6bbc 814 # define VBLANK_OCCURRED (1 << 0) 815 # define VBLANK_ACK (1 << 4) 816 # define VBLANK_STAT (1 << 12) 817 # define VBLANK_INTERRUPT (1 << 16) 818 # define VBLANK_INTERRUPT_TYPE (1 << 17) 819 820 /* 0x6b40, 0x7740, 0x10340, 0x10f40, 0x11b40, 0x12740 */ 821 #define INT_MASK 0x6b40 822 # define VBLANK_INT_MASK (1 << 0) 823 # define VLINE_INT_MASK (1 << 4) 824 825 #define DISP_INTERRUPT_STATUS 0x60f4 826 # define LB_D1_VLINE_INTERRUPT (1 << 2) 827 # define LB_D1_VBLANK_INTERRUPT (1 << 3) 828 # define DC_HPD1_INTERRUPT (1 << 17) 829 # define DC_HPD1_RX_INTERRUPT (1 << 18) 830 # define DACA_AUTODETECT_INTERRUPT (1 << 22) 831 # define DACB_AUTODETECT_INTERRUPT (1 << 23) 832 # define DC_I2C_SW_DONE_INTERRUPT (1 << 24) 833 # define DC_I2C_HW_DONE_INTERRUPT (1 << 25) 834 #define DISP_INTERRUPT_STATUS_CONTINUE 0x60f8 835 # define LB_D2_VLINE_INTERRUPT (1 << 2) 836 # define LB_D2_VBLANK_INTERRUPT (1 << 3) 837 # define DC_HPD2_INTERRUPT (1 << 17) 838 # define DC_HPD2_RX_INTERRUPT (1 << 18) 839 # define DISP_TIMER_INTERRUPT (1 << 24) 840 #define DISP_INTERRUPT_STATUS_CONTINUE2 0x60fc 841 # define LB_D3_VLINE_INTERRUPT (1 << 2) 842 # define LB_D3_VBLANK_INTERRUPT (1 << 3) 843 # define DC_HPD3_INTERRUPT (1 << 17) 844 # define DC_HPD3_RX_INTERRUPT (1 << 18) 845 #define DISP_INTERRUPT_STATUS_CONTINUE3 0x6100 846 # define LB_D4_VLINE_INTERRUPT (1 << 2) 847 # define LB_D4_VBLANK_INTERRUPT (1 << 3) 848 # define DC_HPD4_INTERRUPT (1 << 17) 849 # define DC_HPD4_RX_INTERRUPT (1 << 18) 850 #define DISP_INTERRUPT_STATUS_CONTINUE4 0x614c 851 # define LB_D5_VLINE_INTERRUPT (1 << 2) 852 # define LB_D5_VBLANK_INTERRUPT (1 << 3) 853 # define DC_HPD5_INTERRUPT (1 << 17) 854 # define DC_HPD5_RX_INTERRUPT (1 << 18) 855 #define DISP_INTERRUPT_STATUS_CONTINUE5 0x6150 856 # define LB_D6_VLINE_INTERRUPT (1 << 2) 857 # define LB_D6_VBLANK_INTERRUPT (1 << 3) 858 # define DC_HPD6_INTERRUPT (1 << 17) 859 # define DC_HPD6_RX_INTERRUPT (1 << 18) 860 861 /* 0x6858, 0x7458, 0x10058, 0x10c58, 0x11858, 0x12458 */ 862 #define GRPH_INT_STATUS 0x6858 863 # define GRPH_PFLIP_INT_OCCURRED (1 << 0) 864 # define GRPH_PFLIP_INT_CLEAR (1 << 8) 865 /* 0x685c, 0x745c, 0x1005c, 0x10c5c, 0x1185c, 0x1245c */ 866 #define GRPH_INT_CONTROL 0x685c 867 # define GRPH_PFLIP_INT_MASK (1 << 0) 868 # define GRPH_PFLIP_INT_TYPE (1 << 8) 869 870 #define DAC_AUTODETECT_INT_CONTROL 0x67c8 871 872 #define DC_HPD1_INT_STATUS 0x601c 873 #define DC_HPD2_INT_STATUS 0x6028 874 #define DC_HPD3_INT_STATUS 0x6034 875 #define DC_HPD4_INT_STATUS 0x6040 876 #define DC_HPD5_INT_STATUS 0x604c 877 #define DC_HPD6_INT_STATUS 0x6058 878 # define DC_HPDx_INT_STATUS (1 << 0) 879 # define DC_HPDx_SENSE (1 << 1) 880 # define DC_HPDx_RX_INT_STATUS (1 << 8) 881 882 #define DC_HPD1_INT_CONTROL 0x6020 883 #define DC_HPD2_INT_CONTROL 0x602c 884 #define DC_HPD3_INT_CONTROL 0x6038 885 #define DC_HPD4_INT_CONTROL 0x6044 886 #define DC_HPD5_INT_CONTROL 0x6050 887 #define DC_HPD6_INT_CONTROL 0x605c 888 # define DC_HPDx_INT_ACK (1 << 0) 889 # define DC_HPDx_INT_POLARITY (1 << 8) 890 # define DC_HPDx_INT_EN (1 << 16) 891 # define DC_HPDx_RX_INT_ACK (1 << 20) 892 # define DC_HPDx_RX_INT_EN (1 << 24) 893 894 #define DC_HPD1_CONTROL 0x6024 895 #define DC_HPD2_CONTROL 0x6030 896 #define DC_HPD3_CONTROL 0x603c 897 #define DC_HPD4_CONTROL 0x6048 898 #define DC_HPD5_CONTROL 0x6054 899 #define DC_HPD6_CONTROL 0x6060 900 # define DC_HPDx_CONNECTION_TIMER(x) ((x) << 0) 901 # define DC_HPDx_RX_INT_TIMER(x) ((x) << 16) 902 # define DC_HPDx_EN (1 << 28) 903 904 #define DPG_PIPE_STUTTER_CONTROL 0x6cd4 905 # define STUTTER_ENABLE (1 << 0) 906 907 /* 0x6e98, 0x7a98, 0x10698, 0x11298, 0x11e98, 0x12a98 */ 908 #define CRTC_STATUS_FRAME_COUNT 0x6e98 909 910 /* Audio clocks */ 911 #define DCCG_AUDIO_DTO_SOURCE 0x05ac 912 # define DCCG_AUDIO_DTO0_SOURCE_SEL(x) ((x) << 0) /* crtc0 - crtc5 */ 913 # define DCCG_AUDIO_DTO_SEL (1 << 4) /* 0=dto0 1=dto1 */ 914 915 #define DCCG_AUDIO_DTO0_PHASE 0x05b0 916 #define DCCG_AUDIO_DTO0_MODULE 0x05b4 917 #define DCCG_AUDIO_DTO1_PHASE 0x05c0 918 #define DCCG_AUDIO_DTO1_MODULE 0x05c4 919 920 #define DENTIST_DISPCLK_CNTL 0x0490 921 # define DENTIST_DPREFCLK_WDIVIDER(x) (((x) & 0x7f) << 24) 922 # define DENTIST_DPREFCLK_WDIVIDER_MASK (0x7f << 24) 923 # define DENTIST_DPREFCLK_WDIVIDER_SHIFT 24 924 925 #define AFMT_AUDIO_SRC_CONTROL 0x713c 926 #define AFMT_AUDIO_SRC_SELECT(x) (((x) & 7) << 0) 927 /* AFMT_AUDIO_SRC_SELECT 928 * 0 = stream0 929 * 1 = stream1 930 * 2 = stream2 931 * 3 = stream3 932 * 4 = stream4 933 * 5 = stream5 934 */ 935 936 #define GRBM_CNTL 0x8000 937 #define GRBM_READ_TIMEOUT(x) ((x) << 0) 938 939 #define GRBM_STATUS2 0x8008 940 #define RLC_RQ_PENDING (1 << 0) 941 #define RLC_BUSY (1 << 8) 942 #define TC_BUSY (1 << 9) 943 944 #define GRBM_STATUS 0x8010 945 #define CMDFIFO_AVAIL_MASK 0x0000000F 946 #define RING2_RQ_PENDING (1 << 4) 947 #define SRBM_RQ_PENDING (1 << 5) 948 #define RING1_RQ_PENDING (1 << 6) 949 #define CF_RQ_PENDING (1 << 7) 950 #define PF_RQ_PENDING (1 << 8) 951 #define GDS_DMA_RQ_PENDING (1 << 9) 952 #define GRBM_EE_BUSY (1 << 10) 953 #define DB_CLEAN (1 << 12) 954 #define CB_CLEAN (1 << 13) 955 #define TA_BUSY (1 << 14) 956 #define GDS_BUSY (1 << 15) 957 #define VGT_BUSY (1 << 17) 958 #define IA_BUSY_NO_DMA (1 << 18) 959 #define IA_BUSY (1 << 19) 960 #define SX_BUSY (1 << 20) 961 #define SPI_BUSY (1 << 22) 962 #define BCI_BUSY (1 << 23) 963 #define SC_BUSY (1 << 24) 964 #define PA_BUSY (1 << 25) 965 #define DB_BUSY (1 << 26) 966 #define CP_COHERENCY_BUSY (1 << 28) 967 #define CP_BUSY (1 << 29) 968 #define CB_BUSY (1 << 30) 969 #define GUI_ACTIVE (1 << 31) 970 #define GRBM_STATUS_SE0 0x8014 971 #define GRBM_STATUS_SE1 0x8018 972 #define SE_DB_CLEAN (1 << 1) 973 #define SE_CB_CLEAN (1 << 2) 974 #define SE_BCI_BUSY (1 << 22) 975 #define SE_VGT_BUSY (1 << 23) 976 #define SE_PA_BUSY (1 << 24) 977 #define SE_TA_BUSY (1 << 25) 978 #define SE_SX_BUSY (1 << 26) 979 #define SE_SPI_BUSY (1 << 27) 980 #define SE_SC_BUSY (1 << 29) 981 #define SE_DB_BUSY (1 << 30) 982 #define SE_CB_BUSY (1 << 31) 983 984 #define GRBM_SOFT_RESET 0x8020 985 #define SOFT_RESET_CP (1 << 0) 986 #define SOFT_RESET_CB (1 << 1) 987 #define SOFT_RESET_RLC (1 << 2) 988 #define SOFT_RESET_DB (1 << 3) 989 #define SOFT_RESET_GDS (1 << 4) 990 #define SOFT_RESET_PA (1 << 5) 991 #define SOFT_RESET_SC (1 << 6) 992 #define SOFT_RESET_BCI (1 << 7) 993 #define SOFT_RESET_SPI (1 << 8) 994 #define SOFT_RESET_SX (1 << 10) 995 #define SOFT_RESET_TC (1 << 11) 996 #define SOFT_RESET_TA (1 << 12) 997 #define SOFT_RESET_VGT (1 << 14) 998 #define SOFT_RESET_IA (1 << 15) 999 1000 #define GRBM_GFX_INDEX 0x802C 1001 #define INSTANCE_INDEX(x) ((x) << 0) 1002 #define SH_INDEX(x) ((x) << 8) 1003 #define SE_INDEX(x) ((x) << 16) 1004 #define SH_BROADCAST_WRITES (1 << 29) 1005 #define INSTANCE_BROADCAST_WRITES (1 << 30) 1006 #define SE_BROADCAST_WRITES (1U << 31) 1007 1008 #define GRBM_INT_CNTL 0x8060 1009 # define RDERR_INT_ENABLE (1 << 0) 1010 # define GUI_IDLE_INT_ENABLE (1 << 19) 1011 1012 #define CP_STRMOUT_CNTL 0x84FC 1013 #define SCRATCH_REG0 0x8500 1014 #define SCRATCH_REG1 0x8504 1015 #define SCRATCH_REG2 0x8508 1016 #define SCRATCH_REG3 0x850C 1017 #define SCRATCH_REG4 0x8510 1018 #define SCRATCH_REG5 0x8514 1019 #define SCRATCH_REG6 0x8518 1020 #define SCRATCH_REG7 0x851C 1021 1022 #define SCRATCH_UMSK 0x8540 1023 #define SCRATCH_ADDR 0x8544 1024 1025 #define CP_SEM_WAIT_TIMER 0x85BC 1026 1027 #define CP_SEM_INCOMPLETE_TIMER_CNTL 0x85C8 1028 1029 #define CP_ME_CNTL 0x86D8 1030 #define CP_CE_HALT (1 << 24) 1031 #define CP_PFP_HALT (1 << 26) 1032 #define CP_ME_HALT (1 << 28) 1033 1034 #define CP_COHER_CNTL2 0x85E8 1035 1036 #define CP_RB2_RPTR 0x86f8 1037 #define CP_RB1_RPTR 0x86fc 1038 #define CP_RB0_RPTR 0x8700 1039 #define CP_RB_WPTR_DELAY 0x8704 1040 1041 #define CP_QUEUE_THRESHOLDS 0x8760 1042 #define ROQ_IB1_START(x) ((x) << 0) 1043 #define ROQ_IB2_START(x) ((x) << 8) 1044 #define CP_MEQ_THRESHOLDS 0x8764 1045 #define MEQ1_START(x) ((x) << 0) 1046 #define MEQ2_START(x) ((x) << 8) 1047 1048 #define CP_PERFMON_CNTL 0x87FC 1049 1050 #define VGT_VTX_VECT_EJECT_REG 0x88B0 1051 1052 #define VGT_CACHE_INVALIDATION 0x88C4 1053 #define CACHE_INVALIDATION(x) ((x) << 0) 1054 #define VC_ONLY 0 1055 #define TC_ONLY 1 1056 #define VC_AND_TC 2 1057 #define AUTO_INVLD_EN(x) ((x) << 6) 1058 #define NO_AUTO 0 1059 #define ES_AUTO 1 1060 #define GS_AUTO 2 1061 #define ES_AND_GS_AUTO 3 1062 #define VGT_ESGS_RING_SIZE 0x88C8 1063 #define VGT_GSVS_RING_SIZE 0x88CC 1064 1065 #define VGT_GS_VERTEX_REUSE 0x88D4 1066 1067 #define VGT_PRIMITIVE_TYPE 0x8958 1068 #define VGT_INDEX_TYPE 0x895C 1069 1070 #define VGT_NUM_INDICES 0x8970 1071 #define VGT_NUM_INSTANCES 0x8974 1072 1073 #define VGT_TF_RING_SIZE 0x8988 1074 1075 #define VGT_HS_OFFCHIP_PARAM 0x89B0 1076 1077 #define VGT_TF_MEMORY_BASE 0x89B8 1078 1079 #define CC_GC_SHADER_ARRAY_CONFIG 0x89bc 1080 #define INACTIVE_CUS_MASK 0xFFFF0000 1081 #define INACTIVE_CUS_SHIFT 16 1082 #define GC_USER_SHADER_ARRAY_CONFIG 0x89c0 1083 1084 #define PA_CL_ENHANCE 0x8A14 1085 #define CLIP_VTX_REORDER_ENA (1 << 0) 1086 #define NUM_CLIP_SEQ(x) ((x) << 1) 1087 1088 #define PA_SU_LINE_STIPPLE_VALUE 0x8A60 1089 1090 #define PA_SC_LINE_STIPPLE_STATE 0x8B10 1091 1092 #define PA_SC_FORCE_EOV_MAX_CNTS 0x8B24 1093 #define FORCE_EOV_MAX_CLK_CNT(x) ((x) << 0) 1094 #define FORCE_EOV_MAX_REZ_CNT(x) ((x) << 16) 1095 1096 #define PA_SC_FIFO_SIZE 0x8BCC 1097 #define SC_FRONTEND_PRIM_FIFO_SIZE(x) ((x) << 0) 1098 #define SC_BACKEND_PRIM_FIFO_SIZE(x) ((x) << 6) 1099 #define SC_HIZ_TILE_FIFO_SIZE(x) ((x) << 15) 1100 #define SC_EARLYZ_TILE_FIFO_SIZE(x) ((x) << 23) 1101 1102 #define PA_SC_ENHANCE 0x8BF0 1103 1104 #define SQ_CONFIG 0x8C00 1105 1106 #define SQC_CACHES 0x8C08 1107 1108 #define SQ_POWER_THROTTLE 0x8e58 1109 #define MIN_POWER(x) ((x) << 0) 1110 #define MIN_POWER_MASK (0x3fff << 0) 1111 #define MIN_POWER_SHIFT 0 1112 #define MAX_POWER(x) ((x) << 16) 1113 #define MAX_POWER_MASK (0x3fff << 16) 1114 #define MAX_POWER_SHIFT 0 1115 #define SQ_POWER_THROTTLE2 0x8e5c 1116 #define MAX_POWER_DELTA(x) ((x) << 0) 1117 #define MAX_POWER_DELTA_MASK (0x3fff << 0) 1118 #define MAX_POWER_DELTA_SHIFT 0 1119 #define STI_SIZE(x) ((x) << 16) 1120 #define STI_SIZE_MASK (0x3ff << 16) 1121 #define STI_SIZE_SHIFT 16 1122 #define LTI_RATIO(x) ((x) << 27) 1123 #define LTI_RATIO_MASK (0xf << 27) 1124 #define LTI_RATIO_SHIFT 27 1125 1126 #define SX_DEBUG_1 0x9060 1127 1128 #define SPI_STATIC_THREAD_MGMT_1 0x90E0 1129 #define SPI_STATIC_THREAD_MGMT_2 0x90E4 1130 #define SPI_STATIC_THREAD_MGMT_3 0x90E8 1131 #define SPI_PS_MAX_WAVE_ID 0x90EC 1132 1133 #define SPI_CONFIG_CNTL 0x9100 1134 1135 #define SPI_CONFIG_CNTL_1 0x913C 1136 #define VTX_DONE_DELAY(x) ((x) << 0) 1137 #define INTERP_ONE_PRIM_PER_ROW (1 << 4) 1138 1139 #define CGTS_TCC_DISABLE 0x9148 1140 #define CGTS_USER_TCC_DISABLE 0x914C 1141 #define TCC_DISABLE_MASK 0xFFFF0000 1142 #define TCC_DISABLE_SHIFT 16 1143 #define CGTS_SM_CTRL_REG 0x9150 1144 #define OVERRIDE (1 << 21) 1145 #define LS_OVERRIDE (1 << 22) 1146 1147 #define SPI_LB_CU_MASK 0x9354 1148 1149 #define TA_CNTL_AUX 0x9508 1150 #define TA_CS_BC_BASE_ADDR 0x950C 1151 1152 #define CC_RB_BACKEND_DISABLE 0x98F4 1153 #define BACKEND_DISABLE(x) ((x) << 16) 1154 #define GB_ADDR_CONFIG 0x98F8 1155 #define NUM_PIPES(x) ((x) << 0) 1156 #define NUM_PIPES_MASK 0x00000007 1157 #define NUM_PIPES_SHIFT 0 1158 #define PIPE_INTERLEAVE_SIZE(x) ((x) << 4) 1159 #define PIPE_INTERLEAVE_SIZE_MASK 0x00000070 1160 #define PIPE_INTERLEAVE_SIZE_SHIFT 4 1161 #define NUM_SHADER_ENGINES(x) ((x) << 12) 1162 #define NUM_SHADER_ENGINES_MASK 0x00003000 1163 #define NUM_SHADER_ENGINES_SHIFT 12 1164 #define SHADER_ENGINE_TILE_SIZE(x) ((x) << 16) 1165 #define SHADER_ENGINE_TILE_SIZE_MASK 0x00070000 1166 #define SHADER_ENGINE_TILE_SIZE_SHIFT 16 1167 #define NUM_GPUS(x) ((x) << 20) 1168 #define NUM_GPUS_MASK 0x00700000 1169 #define NUM_GPUS_SHIFT 20 1170 #define MULTI_GPU_TILE_SIZE(x) ((x) << 24) 1171 #define MULTI_GPU_TILE_SIZE_MASK 0x03000000 1172 #define MULTI_GPU_TILE_SIZE_SHIFT 24 1173 #define ROW_SIZE(x) ((x) << 28) 1174 #define ROW_SIZE_MASK 0x30000000 1175 #define ROW_SIZE_SHIFT 28 1176 1177 #define GB_TILE_MODE0 0x9910 1178 # define MICRO_TILE_MODE(x) ((x) << 0) 1179 # define ADDR_SURF_DISPLAY_MICRO_TILING 0 1180 # define ADDR_SURF_THIN_MICRO_TILING 1 1181 # define ADDR_SURF_DEPTH_MICRO_TILING 2 1182 # define ARRAY_MODE(x) ((x) << 2) 1183 # define ARRAY_LINEAR_GENERAL 0 1184 # define ARRAY_LINEAR_ALIGNED 1 1185 # define ARRAY_1D_TILED_THIN1 2 1186 # define ARRAY_2D_TILED_THIN1 4 1187 # define PIPE_CONFIG(x) ((x) << 6) 1188 # define ADDR_SURF_P2 0 1189 # define ADDR_SURF_P4_8x16 4 1190 # define ADDR_SURF_P4_16x16 5 1191 # define ADDR_SURF_P4_16x32 6 1192 # define ADDR_SURF_P4_32x32 7 1193 # define ADDR_SURF_P8_16x16_8x16 8 1194 # define ADDR_SURF_P8_16x32_8x16 9 1195 # define ADDR_SURF_P8_32x32_8x16 10 1196 # define ADDR_SURF_P8_16x32_16x16 11 1197 # define ADDR_SURF_P8_32x32_16x16 12 1198 # define ADDR_SURF_P8_32x32_16x32 13 1199 # define ADDR_SURF_P8_32x64_32x32 14 1200 # define TILE_SPLIT(x) ((x) << 11) 1201 # define ADDR_SURF_TILE_SPLIT_64B 0 1202 # define ADDR_SURF_TILE_SPLIT_128B 1 1203 # define ADDR_SURF_TILE_SPLIT_256B 2 1204 # define ADDR_SURF_TILE_SPLIT_512B 3 1205 # define ADDR_SURF_TILE_SPLIT_1KB 4 1206 # define ADDR_SURF_TILE_SPLIT_2KB 5 1207 # define ADDR_SURF_TILE_SPLIT_4KB 6 1208 # define BANK_WIDTH(x) ((x) << 14) 1209 # define ADDR_SURF_BANK_WIDTH_1 0 1210 # define ADDR_SURF_BANK_WIDTH_2 1 1211 # define ADDR_SURF_BANK_WIDTH_4 2 1212 # define ADDR_SURF_BANK_WIDTH_8 3 1213 # define BANK_HEIGHT(x) ((x) << 16) 1214 # define ADDR_SURF_BANK_HEIGHT_1 0 1215 # define ADDR_SURF_BANK_HEIGHT_2 1 1216 # define ADDR_SURF_BANK_HEIGHT_4 2 1217 # define ADDR_SURF_BANK_HEIGHT_8 3 1218 # define MACRO_TILE_ASPECT(x) ((x) << 18) 1219 # define ADDR_SURF_MACRO_ASPECT_1 0 1220 # define ADDR_SURF_MACRO_ASPECT_2 1 1221 # define ADDR_SURF_MACRO_ASPECT_4 2 1222 # define ADDR_SURF_MACRO_ASPECT_8 3 1223 # define NUM_BANKS(x) ((x) << 20) 1224 # define ADDR_SURF_2_BANK 0 1225 # define ADDR_SURF_4_BANK 1 1226 # define ADDR_SURF_8_BANK 2 1227 # define ADDR_SURF_16_BANK 3 1228 1229 #define CB_PERFCOUNTER0_SELECT0 0x9a20 1230 #define CB_PERFCOUNTER0_SELECT1 0x9a24 1231 #define CB_PERFCOUNTER1_SELECT0 0x9a28 1232 #define CB_PERFCOUNTER1_SELECT1 0x9a2c 1233 #define CB_PERFCOUNTER2_SELECT0 0x9a30 1234 #define CB_PERFCOUNTER2_SELECT1 0x9a34 1235 #define CB_PERFCOUNTER3_SELECT0 0x9a38 1236 #define CB_PERFCOUNTER3_SELECT1 0x9a3c 1237 1238 #define CB_CGTT_SCLK_CTRL 0x9a60 1239 1240 #define GC_USER_RB_BACKEND_DISABLE 0x9B7C 1241 #define BACKEND_DISABLE_MASK 0x00FF0000 1242 #define BACKEND_DISABLE_SHIFT 16 1243 1244 #define TCP_CHAN_STEER_LO 0xac0c 1245 #define TCP_CHAN_STEER_HI 0xac10 1246 1247 #define CP_RB0_BASE 0xC100 1248 #define CP_RB0_CNTL 0xC104 1249 #define RB_BUFSZ(x) ((x) << 0) 1250 #define RB_BLKSZ(x) ((x) << 8) 1251 #define BUF_SWAP_32BIT (2 << 16) 1252 #define RB_NO_UPDATE (1 << 27) 1253 #define RB_RPTR_WR_ENA (1U << 31) 1254 1255 #define CP_RB0_RPTR_ADDR 0xC10C 1256 #define CP_RB0_RPTR_ADDR_HI 0xC110 1257 #define CP_RB0_WPTR 0xC114 1258 1259 #define CP_PFP_UCODE_ADDR 0xC150 1260 #define CP_PFP_UCODE_DATA 0xC154 1261 #define CP_ME_RAM_RADDR 0xC158 1262 #define CP_ME_RAM_WADDR 0xC15C 1263 #define CP_ME_RAM_DATA 0xC160 1264 1265 #define CP_CE_UCODE_ADDR 0xC168 1266 #define CP_CE_UCODE_DATA 0xC16C 1267 1268 #define CP_RB1_BASE 0xC180 1269 #define CP_RB1_CNTL 0xC184 1270 #define CP_RB1_RPTR_ADDR 0xC188 1271 #define CP_RB1_RPTR_ADDR_HI 0xC18C 1272 #define CP_RB1_WPTR 0xC190 1273 #define CP_RB2_BASE 0xC194 1274 #define CP_RB2_CNTL 0xC198 1275 #define CP_RB2_RPTR_ADDR 0xC19C 1276 #define CP_RB2_RPTR_ADDR_HI 0xC1A0 1277 #define CP_RB2_WPTR 0xC1A4 1278 #define CP_INT_CNTL_RING0 0xC1A8 1279 #define CP_INT_CNTL_RING1 0xC1AC 1280 #define CP_INT_CNTL_RING2 0xC1B0 1281 # define CNTX_BUSY_INT_ENABLE (1 << 19) 1282 # define CNTX_EMPTY_INT_ENABLE (1 << 20) 1283 # define WAIT_MEM_SEM_INT_ENABLE (1 << 21) 1284 # define TIME_STAMP_INT_ENABLE (1 << 26) 1285 # define CP_RINGID2_INT_ENABLE (1 << 29) 1286 # define CP_RINGID1_INT_ENABLE (1 << 30) 1287 # define CP_RINGID0_INT_ENABLE (1 << 31) 1288 #define CP_INT_STATUS_RING0 0xC1B4 1289 #define CP_INT_STATUS_RING1 0xC1B8 1290 #define CP_INT_STATUS_RING2 0xC1BC 1291 # define WAIT_MEM_SEM_INT_STAT (1 << 21) 1292 # define TIME_STAMP_INT_STAT (1 << 26) 1293 # define CP_RINGID2_INT_STAT (1 << 29) 1294 # define CP_RINGID1_INT_STAT (1 << 30) 1295 # define CP_RINGID0_INT_STAT (1 << 31) 1296 1297 #define CP_MEM_SLP_CNTL 0xC1E4 1298 # define CP_MEM_LS_EN (1 << 0) 1299 1300 #define CP_DEBUG 0xC1FC 1301 1302 #define RLC_CNTL 0xC300 1303 # define RLC_ENABLE (1 << 0) 1304 #define RLC_RL_BASE 0xC304 1305 #define RLC_RL_SIZE 0xC308 1306 #define RLC_LB_CNTL 0xC30C 1307 # define LOAD_BALANCE_ENABLE (1 << 0) 1308 #define RLC_SAVE_AND_RESTORE_BASE 0xC310 1309 #define RLC_LB_CNTR_MAX 0xC314 1310 #define RLC_LB_CNTR_INIT 0xC318 1311 1312 #define RLC_CLEAR_STATE_RESTORE_BASE 0xC320 1313 1314 #define RLC_UCODE_ADDR 0xC32C 1315 #define RLC_UCODE_DATA 0xC330 1316 1317 #define RLC_GPU_CLOCK_COUNT_LSB 0xC338 1318 #define RLC_GPU_CLOCK_COUNT_MSB 0xC33C 1319 #define RLC_CAPTURE_GPU_CLOCK_COUNT 0xC340 1320 #define RLC_MC_CNTL 0xC344 1321 #define RLC_UCODE_CNTL 0xC348 1322 #define RLC_STAT 0xC34C 1323 # define RLC_BUSY_STATUS (1 << 0) 1324 # define GFX_POWER_STATUS (1 << 1) 1325 # define GFX_CLOCK_STATUS (1 << 2) 1326 # define GFX_LS_STATUS (1 << 3) 1327 1328 #define RLC_PG_CNTL 0xC35C 1329 # define GFX_PG_ENABLE (1 << 0) 1330 # define GFX_PG_SRC (1 << 1) 1331 1332 #define RLC_CGTT_MGCG_OVERRIDE 0xC400 1333 #define RLC_CGCG_CGLS_CTRL 0xC404 1334 # define CGCG_EN (1 << 0) 1335 # define CGLS_EN (1 << 1) 1336 1337 #define RLC_TTOP_D 0xC414 1338 # define RLC_PUD(x) ((x) << 0) 1339 # define RLC_PUD_MASK (0xff << 0) 1340 # define RLC_PDD(x) ((x) << 8) 1341 # define RLC_PDD_MASK (0xff << 8) 1342 # define RLC_TTPD(x) ((x) << 16) 1343 # define RLC_TTPD_MASK (0xff << 16) 1344 # define RLC_MSD(x) ((x) << 24) 1345 # define RLC_MSD_MASK (0xff << 24) 1346 1347 #define RLC_LB_INIT_CU_MASK 0xC41C 1348 1349 #define RLC_PG_AO_CU_MASK 0xC42C 1350 #define RLC_MAX_PG_CU 0xC430 1351 # define MAX_PU_CU(x) ((x) << 0) 1352 # define MAX_PU_CU_MASK (0xff << 0) 1353 #define RLC_AUTO_PG_CTRL 0xC434 1354 # define AUTO_PG_EN (1 << 0) 1355 # define GRBM_REG_SGIT(x) ((x) << 3) 1356 # define GRBM_REG_SGIT_MASK (0xffff << 3) 1357 # define PG_AFTER_GRBM_REG_ST(x) ((x) << 19) 1358 # define PG_AFTER_GRBM_REG_ST_MASK (0x1fff << 19) 1359 1360 #define RLC_SERDES_WR_MASTER_MASK_0 0xC454 1361 #define RLC_SERDES_WR_MASTER_MASK_1 0xC458 1362 #define RLC_SERDES_WR_CTRL 0xC45C 1363 1364 #define RLC_SERDES_MASTER_BUSY_0 0xC464 1365 #define RLC_SERDES_MASTER_BUSY_1 0xC468 1366 1367 #define RLC_GCPM_GENERAL_3 0xC478 1368 1369 #define DB_RENDER_CONTROL 0x28000 1370 1371 #define DB_DEPTH_INFO 0x2803c 1372 1373 #define PA_SC_RASTER_CONFIG 0x28350 1374 # define RASTER_CONFIG_RB_MAP_0 0 1375 # define RASTER_CONFIG_RB_MAP_1 1 1376 # define RASTER_CONFIG_RB_MAP_2 2 1377 # define RASTER_CONFIG_RB_MAP_3 3 1378 1379 #define VGT_EVENT_INITIATOR 0x28a90 1380 # define SAMPLE_STREAMOUTSTATS1 (1 << 0) 1381 # define SAMPLE_STREAMOUTSTATS2 (2 << 0) 1382 # define SAMPLE_STREAMOUTSTATS3 (3 << 0) 1383 # define CACHE_FLUSH_TS (4 << 0) 1384 # define CACHE_FLUSH (6 << 0) 1385 # define CS_PARTIAL_FLUSH (7 << 0) 1386 # define VGT_STREAMOUT_RESET (10 << 0) 1387 # define END_OF_PIPE_INCR_DE (11 << 0) 1388 # define END_OF_PIPE_IB_END (12 << 0) 1389 # define RST_PIX_CNT (13 << 0) 1390 # define VS_PARTIAL_FLUSH (15 << 0) 1391 # define PS_PARTIAL_FLUSH (16 << 0) 1392 # define CACHE_FLUSH_AND_INV_TS_EVENT (20 << 0) 1393 # define ZPASS_DONE (21 << 0) 1394 # define CACHE_FLUSH_AND_INV_EVENT (22 << 0) 1395 # define PERFCOUNTER_START (23 << 0) 1396 # define PERFCOUNTER_STOP (24 << 0) 1397 # define PIPELINESTAT_START (25 << 0) 1398 # define PIPELINESTAT_STOP (26 << 0) 1399 # define PERFCOUNTER_SAMPLE (27 << 0) 1400 # define SAMPLE_PIPELINESTAT (30 << 0) 1401 # define SAMPLE_STREAMOUTSTATS (32 << 0) 1402 # define RESET_VTX_CNT (33 << 0) 1403 # define VGT_FLUSH (36 << 0) 1404 # define BOTTOM_OF_PIPE_TS (40 << 0) 1405 # define DB_CACHE_FLUSH_AND_INV (42 << 0) 1406 # define FLUSH_AND_INV_DB_DATA_TS (43 << 0) 1407 # define FLUSH_AND_INV_DB_META (44 << 0) 1408 # define FLUSH_AND_INV_CB_DATA_TS (45 << 0) 1409 # define FLUSH_AND_INV_CB_META (46 << 0) 1410 # define CS_DONE (47 << 0) 1411 # define PS_DONE (48 << 0) 1412 # define FLUSH_AND_INV_CB_PIXEL_DATA (49 << 0) 1413 # define THREAD_TRACE_START (51 << 0) 1414 # define THREAD_TRACE_STOP (52 << 0) 1415 # define THREAD_TRACE_FLUSH (54 << 0) 1416 # define THREAD_TRACE_FINISH (55 << 0) 1417 1418 /* PIF PHY0 registers idx/data 0x8/0xc */ 1419 #define PB0_PIF_CNTL 0x10 1420 # define LS2_EXIT_TIME(x) ((x) << 17) 1421 # define LS2_EXIT_TIME_MASK (0x7 << 17) 1422 # define LS2_EXIT_TIME_SHIFT 17 1423 #define PB0_PIF_PAIRING 0x11 1424 # define MULTI_PIF (1 << 25) 1425 #define PB0_PIF_PWRDOWN_0 0x12 1426 # define PLL_POWER_STATE_IN_TXS2_0(x) ((x) << 7) 1427 # define PLL_POWER_STATE_IN_TXS2_0_MASK (0x7 << 7) 1428 # define PLL_POWER_STATE_IN_TXS2_0_SHIFT 7 1429 # define PLL_POWER_STATE_IN_OFF_0(x) ((x) << 10) 1430 # define PLL_POWER_STATE_IN_OFF_0_MASK (0x7 << 10) 1431 # define PLL_POWER_STATE_IN_OFF_0_SHIFT 10 1432 # define PLL_RAMP_UP_TIME_0(x) ((x) << 24) 1433 # define PLL_RAMP_UP_TIME_0_MASK (0x7 << 24) 1434 # define PLL_RAMP_UP_TIME_0_SHIFT 24 1435 #define PB0_PIF_PWRDOWN_1 0x13 1436 # define PLL_POWER_STATE_IN_TXS2_1(x) ((x) << 7) 1437 # define PLL_POWER_STATE_IN_TXS2_1_MASK (0x7 << 7) 1438 # define PLL_POWER_STATE_IN_TXS2_1_SHIFT 7 1439 # define PLL_POWER_STATE_IN_OFF_1(x) ((x) << 10) 1440 # define PLL_POWER_STATE_IN_OFF_1_MASK (0x7 << 10) 1441 # define PLL_POWER_STATE_IN_OFF_1_SHIFT 10 1442 # define PLL_RAMP_UP_TIME_1(x) ((x) << 24) 1443 # define PLL_RAMP_UP_TIME_1_MASK (0x7 << 24) 1444 # define PLL_RAMP_UP_TIME_1_SHIFT 24 1445 1446 #define PB0_PIF_PWRDOWN_2 0x17 1447 # define PLL_POWER_STATE_IN_TXS2_2(x) ((x) << 7) 1448 # define PLL_POWER_STATE_IN_TXS2_2_MASK (0x7 << 7) 1449 # define PLL_POWER_STATE_IN_TXS2_2_SHIFT 7 1450 # define PLL_POWER_STATE_IN_OFF_2(x) ((x) << 10) 1451 # define PLL_POWER_STATE_IN_OFF_2_MASK (0x7 << 10) 1452 # define PLL_POWER_STATE_IN_OFF_2_SHIFT 10 1453 # define PLL_RAMP_UP_TIME_2(x) ((x) << 24) 1454 # define PLL_RAMP_UP_TIME_2_MASK (0x7 << 24) 1455 # define PLL_RAMP_UP_TIME_2_SHIFT 24 1456 #define PB0_PIF_PWRDOWN_3 0x18 1457 # define PLL_POWER_STATE_IN_TXS2_3(x) ((x) << 7) 1458 # define PLL_POWER_STATE_IN_TXS2_3_MASK (0x7 << 7) 1459 # define PLL_POWER_STATE_IN_TXS2_3_SHIFT 7 1460 # define PLL_POWER_STATE_IN_OFF_3(x) ((x) << 10) 1461 # define PLL_POWER_STATE_IN_OFF_3_MASK (0x7 << 10) 1462 # define PLL_POWER_STATE_IN_OFF_3_SHIFT 10 1463 # define PLL_RAMP_UP_TIME_3(x) ((x) << 24) 1464 # define PLL_RAMP_UP_TIME_3_MASK (0x7 << 24) 1465 # define PLL_RAMP_UP_TIME_3_SHIFT 24 1466 /* PIF PHY1 registers idx/data 0x10/0x14 */ 1467 #define PB1_PIF_CNTL 0x10 1468 #define PB1_PIF_PAIRING 0x11 1469 #define PB1_PIF_PWRDOWN_0 0x12 1470 #define PB1_PIF_PWRDOWN_1 0x13 1471 1472 #define PB1_PIF_PWRDOWN_2 0x17 1473 #define PB1_PIF_PWRDOWN_3 0x18 1474 /* PCIE registers idx/data 0x30/0x34 */ 1475 #define PCIE_CNTL2 0x1c /* PCIE */ 1476 # define SLV_MEM_LS_EN (1 << 16) 1477 # define SLV_MEM_AGGRESSIVE_LS_EN (1 << 17) 1478 # define MST_MEM_LS_EN (1 << 18) 1479 # define REPLAY_MEM_LS_EN (1 << 19) 1480 #define PCIE_LC_STATUS1 0x28 /* PCIE */ 1481 # define LC_REVERSE_RCVR (1 << 0) 1482 # define LC_REVERSE_XMIT (1 << 1) 1483 # define LC_OPERATING_LINK_WIDTH_MASK (0x7 << 2) 1484 # define LC_OPERATING_LINK_WIDTH_SHIFT 2 1485 # define LC_DETECTED_LINK_WIDTH_MASK (0x7 << 5) 1486 # define LC_DETECTED_LINK_WIDTH_SHIFT 5 1487 1488 #define PCIE_P_CNTL 0x40 /* PCIE */ 1489 # define P_IGNORE_EDB_ERR (1 << 6) 1490 1491 /* PCIE PORT registers idx/data 0x38/0x3c */ 1492 #define PCIE_LC_CNTL 0xa0 1493 # define LC_L0S_INACTIVITY(x) ((x) << 8) 1494 # define LC_L0S_INACTIVITY_MASK (0xf << 8) 1495 # define LC_L0S_INACTIVITY_SHIFT 8 1496 # define LC_L1_INACTIVITY(x) ((x) << 12) 1497 # define LC_L1_INACTIVITY_MASK (0xf << 12) 1498 # define LC_L1_INACTIVITY_SHIFT 12 1499 # define LC_PMI_TO_L1_DIS (1 << 16) 1500 # define LC_ASPM_TO_L1_DIS (1 << 24) 1501 #define PCIE_LC_LINK_WIDTH_CNTL 0xa2 /* PCIE_P */ 1502 # define LC_LINK_WIDTH_SHIFT 0 1503 # define LC_LINK_WIDTH_MASK 0x7 1504 # define LC_LINK_WIDTH_X0 0 1505 # define LC_LINK_WIDTH_X1 1 1506 # define LC_LINK_WIDTH_X2 2 1507 # define LC_LINK_WIDTH_X4 3 1508 # define LC_LINK_WIDTH_X8 4 1509 # define LC_LINK_WIDTH_X16 6 1510 # define LC_LINK_WIDTH_RD_SHIFT 4 1511 # define LC_LINK_WIDTH_RD_MASK 0x70 1512 # define LC_RECONFIG_ARC_MISSING_ESCAPE (1 << 7) 1513 # define LC_RECONFIG_NOW (1 << 8) 1514 # define LC_RENEGOTIATION_SUPPORT (1 << 9) 1515 # define LC_RENEGOTIATE_EN (1 << 10) 1516 # define LC_SHORT_RECONFIG_EN (1 << 11) 1517 # define LC_UPCONFIGURE_SUPPORT (1 << 12) 1518 # define LC_UPCONFIGURE_DIS (1 << 13) 1519 # define LC_DYN_LANES_PWR_STATE(x) ((x) << 21) 1520 # define LC_DYN_LANES_PWR_STATE_MASK (0x3 << 21) 1521 # define LC_DYN_LANES_PWR_STATE_SHIFT 21 1522 #define PCIE_LC_N_FTS_CNTL 0xa3 /* PCIE_P */ 1523 # define LC_XMIT_N_FTS(x) ((x) << 0) 1524 # define LC_XMIT_N_FTS_MASK (0xff << 0) 1525 # define LC_XMIT_N_FTS_SHIFT 0 1526 # define LC_XMIT_N_FTS_OVERRIDE_EN (1 << 8) 1527 # define LC_N_FTS_MASK (0xffU << 24) 1528 #define PCIE_LC_SPEED_CNTL 0xa4 /* PCIE_P */ 1529 # define LC_GEN2_EN_STRAP (1 << 0) 1530 # define LC_GEN3_EN_STRAP (1 << 1) 1531 # define LC_TARGET_LINK_SPEED_OVERRIDE_EN (1 << 2) 1532 # define LC_TARGET_LINK_SPEED_OVERRIDE_MASK (0x3 << 3) 1533 # define LC_TARGET_LINK_SPEED_OVERRIDE_SHIFT 3 1534 # define LC_FORCE_EN_SW_SPEED_CHANGE (1 << 5) 1535 # define LC_FORCE_DIS_SW_SPEED_CHANGE (1 << 6) 1536 # define LC_FORCE_EN_HW_SPEED_CHANGE (1 << 7) 1537 # define LC_FORCE_DIS_HW_SPEED_CHANGE (1 << 8) 1538 # define LC_INITIATE_LINK_SPEED_CHANGE (1 << 9) 1539 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_MASK (0x3 << 10) 1540 # define LC_SPEED_CHANGE_ATTEMPTS_ALLOWED_SHIFT 10 1541 # define LC_CURRENT_DATA_RATE_MASK (0x3 << 13) /* 0/1/2 = gen1/2/3 */ 1542 # define LC_CURRENT_DATA_RATE_SHIFT 13 1543 # define LC_CLR_FAILED_SPD_CHANGE_CNT (1 << 16) 1544 # define LC_OTHER_SIDE_EVER_SENT_GEN2 (1 << 18) 1545 # define LC_OTHER_SIDE_SUPPORTS_GEN2 (1 << 19) 1546 # define LC_OTHER_SIDE_EVER_SENT_GEN3 (1 << 20) 1547 # define LC_OTHER_SIDE_SUPPORTS_GEN3 (1 << 21) 1548 1549 #define PCIE_LC_CNTL2 0xb1 1550 # define LC_ALLOW_PDWN_IN_L1 (1 << 17) 1551 # define LC_ALLOW_PDWN_IN_L23 (1 << 18) 1552 1553 #define PCIE_LC_CNTL3 0xb5 /* PCIE_P */ 1554 # define LC_GO_TO_RECOVERY (1 << 30) 1555 #define PCIE_LC_CNTL4 0xb6 /* PCIE_P */ 1556 # define LC_REDO_EQ (1 << 5) 1557 # define LC_SET_QUIESCE (1 << 13) 1558 1559 /* 1560 * UVD 1561 */ 1562 #define UVD_UDEC_ADDR_CONFIG 0xEF4C 1563 #define UVD_UDEC_DB_ADDR_CONFIG 0xEF50 1564 #define UVD_UDEC_DBW_ADDR_CONFIG 0xEF54 1565 #define UVD_NO_OP 0xEFFC 1566 #define UVD_RBC_RB_RPTR 0xF690 1567 #define UVD_RBC_RB_WPTR 0xF694 1568 #define UVD_STATUS 0xf6bc 1569 1570 #define UVD_CGC_CTRL 0xF4B0 1571 # define DCM (1 << 0) 1572 # define CG_DT(x) ((x) << 2) 1573 # define CG_DT_MASK (0xf << 2) 1574 # define CLK_OD(x) ((x) << 6) 1575 # define CLK_OD_MASK (0x1f << 6) 1576 1577 /* UVD CTX indirect */ 1578 #define UVD_CGC_MEM_CTRL 0xC0 1579 #define UVD_CGC_CTRL2 0xC1 1580 # define DYN_OR_EN (1 << 0) 1581 # define DYN_RR_EN (1 << 1) 1582 # define G_DIV_ID(x) ((x) << 2) 1583 # define G_DIV_ID_MASK (0x7 << 2) 1584 1585 /* 1586 * PM4 1587 */ 1588 #define PACKET0(reg, n) ((RADEON_PACKET_TYPE0 << 30) | \ 1589 (((reg) >> 2) & 0xFFFF) | \ 1590 ((n) & 0x3FFF) << 16) 1591 #define CP_PACKET2 0x80000000 1592 #define PACKET2_PAD_SHIFT 0 1593 #define PACKET2_PAD_MASK (0x3fffffff << 0) 1594 1595 #define PACKET2(v) (CP_PACKET2 | REG_SET(PACKET2_PAD, (v))) 1596 1597 #define PACKET3(op, n) ((RADEON_PACKET_TYPE3 << 30) | \ 1598 (((op) & 0xFF) << 8) | \ 1599 ((n) & 0x3FFF) << 16) 1600 1601 #define PACKET3_COMPUTE(op, n) (PACKET3(op, n) | 1 << 1) 1602 1603 /* Packet 3 types */ 1604 #define PACKET3_NOP 0x10 1605 #define PACKET3_SET_BASE 0x11 1606 #define PACKET3_BASE_INDEX(x) ((x) << 0) 1607 #define GDS_PARTITION_BASE 2 1608 #define CE_PARTITION_BASE 3 1609 #define PACKET3_CLEAR_STATE 0x12 1610 #define PACKET3_INDEX_BUFFER_SIZE 0x13 1611 #define PACKET3_DISPATCH_DIRECT 0x15 1612 #define PACKET3_DISPATCH_INDIRECT 0x16 1613 #define PACKET3_ALLOC_GDS 0x1B 1614 #define PACKET3_WRITE_GDS_RAM 0x1C 1615 #define PACKET3_ATOMIC_GDS 0x1D 1616 #define PACKET3_ATOMIC 0x1E 1617 #define PACKET3_OCCLUSION_QUERY 0x1F 1618 #define PACKET3_SET_PREDICATION 0x20 1619 #define PACKET3_REG_RMW 0x21 1620 #define PACKET3_COND_EXEC 0x22 1621 #define PACKET3_PRED_EXEC 0x23 1622 #define PACKET3_DRAW_INDIRECT 0x24 1623 #define PACKET3_DRAW_INDEX_INDIRECT 0x25 1624 #define PACKET3_INDEX_BASE 0x26 1625 #define PACKET3_DRAW_INDEX_2 0x27 1626 #define PACKET3_CONTEXT_CONTROL 0x28 1627 #define PACKET3_INDEX_TYPE 0x2A 1628 #define PACKET3_DRAW_INDIRECT_MULTI 0x2C 1629 #define PACKET3_DRAW_INDEX_AUTO 0x2D 1630 #define PACKET3_DRAW_INDEX_IMMD 0x2E 1631 #define PACKET3_NUM_INSTANCES 0x2F 1632 #define PACKET3_DRAW_INDEX_MULTI_AUTO 0x30 1633 #define PACKET3_INDIRECT_BUFFER_CONST 0x31 1634 #define PACKET3_INDIRECT_BUFFER 0x32 1635 #define PACKET3_STRMOUT_BUFFER_UPDATE 0x34 1636 #define PACKET3_DRAW_INDEX_OFFSET_2 0x35 1637 #define PACKET3_DRAW_INDEX_MULTI_ELEMENT 0x36 1638 #define PACKET3_WRITE_DATA 0x37 1639 #define WRITE_DATA_DST_SEL(x) ((x) << 8) 1640 /* 0 - register 1641 * 1 - memory (sync - via GRBM) 1642 * 2 - tc/l2 1643 * 3 - gds 1644 * 4 - reserved 1645 * 5 - memory (async - direct) 1646 */ 1647 #define WR_ONE_ADDR (1 << 16) 1648 #define WR_CONFIRM (1 << 20) 1649 #define WRITE_DATA_ENGINE_SEL(x) ((x) << 30) 1650 /* 0 - me 1651 * 1 - pfp 1652 * 2 - ce 1653 */ 1654 #define PACKET3_DRAW_INDEX_INDIRECT_MULTI 0x38 1655 #define PACKET3_MEM_SEMAPHORE 0x39 1656 #define PACKET3_MPEG_INDEX 0x3A 1657 #define PACKET3_COPY_DW 0x3B 1658 #define PACKET3_WAIT_REG_MEM 0x3C 1659 #define WAIT_REG_MEM_FUNCTION(x) ((x) << 0) 1660 /* 0 - always 1661 * 1 - < 1662 * 2 - <= 1663 * 3 - == 1664 * 4 - != 1665 * 5 - >= 1666 * 6 - > 1667 */ 1668 #define WAIT_REG_MEM_MEM_SPACE(x) ((x) << 4) 1669 /* 0 - reg 1670 * 1 - mem 1671 */ 1672 #define WAIT_REG_MEM_ENGINE(x) ((x) << 8) 1673 /* 0 - me 1674 * 1 - pfp 1675 */ 1676 #define PACKET3_MEM_WRITE 0x3D 1677 #define PACKET3_COPY_DATA 0x40 1678 #define PACKET3_CP_DMA 0x41 1679 /* 1. header 1680 * 2. SRC_ADDR_LO or DATA [31:0] 1681 * 3. CP_SYNC [31] | SRC_SEL [30:29] | ENGINE [27] | DST_SEL [21:20] | 1682 * SRC_ADDR_HI [7:0] 1683 * 4. DST_ADDR_LO [31:0] 1684 * 5. DST_ADDR_HI [7:0] 1685 * 6. COMMAND [30:21] | BYTE_COUNT [20:0] 1686 */ 1687 # define PACKET3_CP_DMA_DST_SEL(x) ((x) << 20) 1688 /* 0 - DST_ADDR 1689 * 1 - GDS 1690 */ 1691 # define PACKET3_CP_DMA_ENGINE(x) ((x) << 27) 1692 /* 0 - ME 1693 * 1 - PFP 1694 */ 1695 # define PACKET3_CP_DMA_SRC_SEL(x) ((x) << 29) 1696 /* 0 - SRC_ADDR 1697 * 1 - GDS 1698 * 2 - DATA 1699 */ 1700 # define PACKET3_CP_DMA_CP_SYNC (1 << 31) 1701 /* COMMAND */ 1702 # define PACKET3_CP_DMA_DIS_WC (1 << 21) 1703 # define PACKET3_CP_DMA_CMD_SRC_SWAP(x) ((x) << 22) 1704 /* 0 - none 1705 * 1 - 8 in 16 1706 * 2 - 8 in 32 1707 * 3 - 8 in 64 1708 */ 1709 # define PACKET3_CP_DMA_CMD_DST_SWAP(x) ((x) << 24) 1710 /* 0 - none 1711 * 1 - 8 in 16 1712 * 2 - 8 in 32 1713 * 3 - 8 in 64 1714 */ 1715 # define PACKET3_CP_DMA_CMD_SAS (1 << 26) 1716 /* 0 - memory 1717 * 1 - register 1718 */ 1719 # define PACKET3_CP_DMA_CMD_DAS (1 << 27) 1720 /* 0 - memory 1721 * 1 - register 1722 */ 1723 # define PACKET3_CP_DMA_CMD_SAIC (1 << 28) 1724 # define PACKET3_CP_DMA_CMD_DAIC (1 << 29) 1725 # define PACKET3_CP_DMA_CMD_RAW_WAIT (1 << 30) 1726 #define PACKET3_PFP_SYNC_ME 0x42 1727 #define PACKET3_SURFACE_SYNC 0x43 1728 # define PACKET3_DEST_BASE_0_ENA (1 << 0) 1729 # define PACKET3_DEST_BASE_1_ENA (1 << 1) 1730 # define PACKET3_CB0_DEST_BASE_ENA (1 << 6) 1731 # define PACKET3_CB1_DEST_BASE_ENA (1 << 7) 1732 # define PACKET3_CB2_DEST_BASE_ENA (1 << 8) 1733 # define PACKET3_CB3_DEST_BASE_ENA (1 << 9) 1734 # define PACKET3_CB4_DEST_BASE_ENA (1 << 10) 1735 # define PACKET3_CB5_DEST_BASE_ENA (1 << 11) 1736 # define PACKET3_CB6_DEST_BASE_ENA (1 << 12) 1737 # define PACKET3_CB7_DEST_BASE_ENA (1 << 13) 1738 # define PACKET3_DB_DEST_BASE_ENA (1 << 14) 1739 # define PACKET3_DEST_BASE_2_ENA (1 << 19) 1740 # define PACKET3_DEST_BASE_3_ENA (1 << 21) 1741 # define PACKET3_TCL1_ACTION_ENA (1 << 22) 1742 # define PACKET3_TC_ACTION_ENA (1 << 23) 1743 # define PACKET3_CB_ACTION_ENA (1 << 25) 1744 # define PACKET3_DB_ACTION_ENA (1 << 26) 1745 # define PACKET3_SH_KCACHE_ACTION_ENA (1 << 27) 1746 # define PACKET3_SH_ICACHE_ACTION_ENA (1 << 29) 1747 #define PACKET3_ME_INITIALIZE 0x44 1748 #define PACKET3_ME_INITIALIZE_DEVICE_ID(x) ((x) << 16) 1749 #define PACKET3_COND_WRITE 0x45 1750 #define PACKET3_EVENT_WRITE 0x46 1751 #define EVENT_TYPE(x) ((x) << 0) 1752 #define EVENT_INDEX(x) ((x) << 8) 1753 /* 0 - any non-TS event 1754 * 1 - ZPASS_DONE 1755 * 2 - SAMPLE_PIPELINESTAT 1756 * 3 - SAMPLE_STREAMOUTSTAT* 1757 * 4 - *S_PARTIAL_FLUSH 1758 * 5 - EOP events 1759 * 6 - EOS events 1760 * 7 - CACHE_FLUSH, CACHE_FLUSH_AND_INV_EVENT 1761 */ 1762 #define INV_L2 (1 << 20) 1763 /* INV TC L2 cache when EVENT_INDEX = 7 */ 1764 #define PACKET3_EVENT_WRITE_EOP 0x47 1765 #define DATA_SEL(x) ((x) << 29) 1766 /* 0 - discard 1767 * 1 - send low 32bit data 1768 * 2 - send 64bit data 1769 * 3 - send 64bit counter value 1770 */ 1771 #define INT_SEL(x) ((x) << 24) 1772 /* 0 - none 1773 * 1 - interrupt only (DATA_SEL = 0) 1774 * 2 - interrupt when data write is confirmed 1775 */ 1776 #define PACKET3_EVENT_WRITE_EOS 0x48 1777 #define PACKET3_PREAMBLE_CNTL 0x4A 1778 # define PACKET3_PREAMBLE_BEGIN_CLEAR_STATE (2 << 28) 1779 # define PACKET3_PREAMBLE_END_CLEAR_STATE (3 << 28) 1780 #define PACKET3_ONE_REG_WRITE 0x57 1781 #define PACKET3_LOAD_CONFIG_REG 0x5F 1782 #define PACKET3_LOAD_CONTEXT_REG 0x60 1783 #define PACKET3_LOAD_SH_REG 0x61 1784 #define PACKET3_SET_CONFIG_REG 0x68 1785 #define PACKET3_SET_CONFIG_REG_START 0x00008000 1786 #define PACKET3_SET_CONFIG_REG_END 0x0000b000 1787 #define PACKET3_SET_CONTEXT_REG 0x69 1788 #define PACKET3_SET_CONTEXT_REG_START 0x00028000 1789 #define PACKET3_SET_CONTEXT_REG_END 0x00029000 1790 #define PACKET3_SET_CONTEXT_REG_INDIRECT 0x73 1791 #define PACKET3_SET_RESOURCE_INDIRECT 0x74 1792 #define PACKET3_SET_SH_REG 0x76 1793 #define PACKET3_SET_SH_REG_START 0x0000b000 1794 #define PACKET3_SET_SH_REG_END 0x0000c000 1795 #define PACKET3_SET_SH_REG_OFFSET 0x77 1796 #define PACKET3_ME_WRITE 0x7A 1797 #define PACKET3_SCRATCH_RAM_WRITE 0x7D 1798 #define PACKET3_SCRATCH_RAM_READ 0x7E 1799 #define PACKET3_CE_WRITE 0x7F 1800 #define PACKET3_LOAD_CONST_RAM 0x80 1801 #define PACKET3_WRITE_CONST_RAM 0x81 1802 #define PACKET3_WRITE_CONST_RAM_OFFSET 0x82 1803 #define PACKET3_DUMP_CONST_RAM 0x83 1804 #define PACKET3_INCREMENT_CE_COUNTER 0x84 1805 #define PACKET3_INCREMENT_DE_COUNTER 0x85 1806 #define PACKET3_WAIT_ON_CE_COUNTER 0x86 1807 #define PACKET3_WAIT_ON_DE_COUNTER 0x87 1808 #define PACKET3_WAIT_ON_DE_COUNTER_DIFF 0x88 1809 #define PACKET3_SET_CE_DE_COUNTERS 0x89 1810 #define PACKET3_WAIT_ON_AVAIL_BUFFER 0x8A 1811 #define PACKET3_SWITCH_BUFFER 0x8B 1812 1813 /* ASYNC DMA - first instance at 0xd000, second at 0xd800 */ 1814 #define DMA0_REGISTER_OFFSET 0x0 /* not a register */ 1815 #define DMA1_REGISTER_OFFSET 0x800 /* not a register */ 1816 1817 #define DMA_RB_CNTL 0xd000 1818 # define DMA_RB_ENABLE (1 << 0) 1819 # define DMA_RB_SIZE(x) ((x) << 1) /* log2 */ 1820 # define DMA_RB_SWAP_ENABLE (1 << 9) /* 8IN32 */ 1821 # define DMA_RPTR_WRITEBACK_ENABLE (1 << 12) 1822 # define DMA_RPTR_WRITEBACK_SWAP_ENABLE (1 << 13) /* 8IN32 */ 1823 # define DMA_RPTR_WRITEBACK_TIMER(x) ((x) << 16) /* log2 */ 1824 #define DMA_RB_BASE 0xd004 1825 #define DMA_RB_RPTR 0xd008 1826 #define DMA_RB_WPTR 0xd00c 1827 1828 #define DMA_RB_RPTR_ADDR_HI 0xd01c 1829 #define DMA_RB_RPTR_ADDR_LO 0xd020 1830 1831 #define DMA_IB_CNTL 0xd024 1832 # define DMA_IB_ENABLE (1 << 0) 1833 # define DMA_IB_SWAP_ENABLE (1 << 4) 1834 #define DMA_IB_RPTR 0xd028 1835 #define DMA_CNTL 0xd02c 1836 # define TRAP_ENABLE (1 << 0) 1837 # define SEM_INCOMPLETE_INT_ENABLE (1 << 1) 1838 # define SEM_WAIT_INT_ENABLE (1 << 2) 1839 # define DATA_SWAP_ENABLE (1 << 3) 1840 # define FENCE_SWAP_ENABLE (1 << 4) 1841 # define CTXEMPTY_INT_ENABLE (1 << 28) 1842 #define DMA_STATUS_REG 0xd034 1843 # define DMA_IDLE (1 << 0) 1844 #define DMA_TILING_CONFIG 0xd0b8 1845 1846 #define DMA_POWER_CNTL 0xd0bc 1847 # define MEM_POWER_OVERRIDE (1 << 8) 1848 #define DMA_CLK_CTRL 0xd0c0 1849 1850 #define DMA_PG 0xd0d4 1851 # define PG_CNTL_ENABLE (1 << 0) 1852 #define DMA_PGFSM_CONFIG 0xd0d8 1853 #define DMA_PGFSM_WRITE 0xd0dc 1854 1855 #define DMA_PACKET(cmd, b, t, s, n) ((((uint32_t)(cmd) & 0xF) << 28) | \ 1856 (((b) & 0x1) << 26) | \ 1857 (((t) & 0x1) << 23) | \ 1858 (((s) & 0x1) << 22) | \ 1859 (((n) & 0xFFFFF) << 0)) 1860 1861 #define DMA_IB_PACKET(cmd, vmid, n) ((((cmd) & 0xF) << 28) | \ 1862 (((vmid) & 0xF) << 20) | \ 1863 (((n) & 0xFFFFF) << 0)) 1864 1865 #define DMA_PTE_PDE_PACKET(n) ((2 << 28) | \ 1866 (1 << 26) | \ 1867 (1 << 21) | \ 1868 (((n) & 0xFFFFF) << 0)) 1869 1870 /* async DMA Packet types */ 1871 #define DMA_PACKET_WRITE 0x2 1872 #define DMA_PACKET_COPY 0x3 1873 #define DMA_PACKET_INDIRECT_BUFFER 0x4 1874 #define DMA_PACKET_SEMAPHORE 0x5 1875 #define DMA_PACKET_FENCE 0x6 1876 #define DMA_PACKET_TRAP 0x7 1877 #define DMA_PACKET_SRBM_WRITE 0x9 1878 #define DMA_PACKET_CONSTANT_FILL 0xd 1879 #define DMA_PACKET_POLL_REG_MEM 0xe 1880 #define DMA_PACKET_NOP 0xf 1881 1882 #define VCE_STATUS 0x20004 1883 #define VCE_VCPU_CNTL 0x20014 1884 #define VCE_CLK_EN (1 << 0) 1885 #define VCE_VCPU_CACHE_OFFSET0 0x20024 1886 #define VCE_VCPU_CACHE_SIZE0 0x20028 1887 #define VCE_VCPU_CACHE_OFFSET1 0x2002c 1888 #define VCE_VCPU_CACHE_SIZE1 0x20030 1889 #define VCE_VCPU_CACHE_OFFSET2 0x20034 1890 #define VCE_VCPU_CACHE_SIZE2 0x20038 1891 #define VCE_VCPU_SCRATCH7 0x200dc 1892 #define VCE_SOFT_RESET 0x20120 1893 #define VCE_ECPU_SOFT_RESET (1 << 0) 1894 #define VCE_FME_SOFT_RESET (1 << 2) 1895 #define VCE_RB_BASE_LO2 0x2016c 1896 #define VCE_RB_BASE_HI2 0x20170 1897 #define VCE_RB_SIZE2 0x20174 1898 #define VCE_RB_RPTR2 0x20178 1899 #define VCE_RB_WPTR2 0x2017c 1900 #define VCE_RB_BASE_LO 0x20180 1901 #define VCE_RB_BASE_HI 0x20184 1902 #define VCE_RB_SIZE 0x20188 1903 #define VCE_RB_RPTR 0x2018c 1904 #define VCE_RB_WPTR 0x20190 1905 #define VCE_CLOCK_GATING_A 0x202f8 1906 # define CGC_DYN_CLOCK_MODE (1 << 16) 1907 #define VCE_CLOCK_GATING_B 0x202fc 1908 #define VCE_UENC_CLOCK_GATING 0x205bc 1909 #define VCE_UENC_REG_CLOCK_GATING 0x205c0 1910 #define VCE_FW_REG_STATUS 0x20e10 1911 # define VCE_FW_REG_STATUS_BUSY (1 << 0) 1912 # define VCE_FW_REG_STATUS_PASS (1 << 3) 1913 # define VCE_FW_REG_STATUS_DONE (1 << 11) 1914 #define VCE_LMI_FW_START_KEYSEL 0x20e18 1915 #define VCE_LMI_FW_PERIODIC_CTRL 0x20e20 1916 #define VCE_LMI_CTRL2 0x20e74 1917 #define VCE_LMI_CTRL 0x20e98 1918 #define VCE_LMI_VM_CTRL 0x20ea0 1919 #define VCE_LMI_SWAP_CNTL 0x20eb4 1920 #define VCE_LMI_SWAP_CNTL1 0x20eb8 1921 #define VCE_LMI_CACHE_CTRL 0x20ef4 1922 1923 #define VCE_CMD_NO_OP 0x00000000 1924 #define VCE_CMD_END 0x00000001 1925 #define VCE_CMD_IB 0x00000002 1926 #define VCE_CMD_FENCE 0x00000003 1927 #define VCE_CMD_TRAP 0x00000004 1928 #define VCE_CMD_IB_AUTO 0x00000005 1929 #define VCE_CMD_SEMAPHORE 0x00000006 1930 1931 /* discrete vce clocks */ 1932 #define CG_VCEPLL_FUNC_CNTL 0xc0030600 1933 # define VCEPLL_RESET_MASK 0x00000001 1934 # define VCEPLL_SLEEP_MASK 0x00000002 1935 # define VCEPLL_BYPASS_EN_MASK 0x00000004 1936 # define VCEPLL_CTLREQ_MASK 0x00000008 1937 # define VCEPLL_VCO_MODE_MASK 0x00000600 1938 # define VCEPLL_REF_DIV_MASK 0x003F0000 1939 # define VCEPLL_CTLACK_MASK 0x40000000 1940 # define VCEPLL_CTLACK2_MASK 0x80000000 1941 #define CG_VCEPLL_FUNC_CNTL_2 0xc0030601 1942 # define VCEPLL_PDIV_A(x) ((x) << 0) 1943 # define VCEPLL_PDIV_A_MASK 0x0000007F 1944 # define VCEPLL_PDIV_B(x) ((x) << 8) 1945 # define VCEPLL_PDIV_B_MASK 0x00007F00 1946 # define EVCLK_SRC_SEL(x) ((x) << 20) 1947 # define EVCLK_SRC_SEL_MASK 0x01F00000 1948 # define ECCLK_SRC_SEL(x) ((x) << 25) 1949 # define ECCLK_SRC_SEL_MASK 0x3E000000 1950 #define CG_VCEPLL_FUNC_CNTL_3 0xc0030602 1951 # define VCEPLL_FB_DIV(x) ((x) << 0) 1952 # define VCEPLL_FB_DIV_MASK 0x01FFFFFF 1953 #define CG_VCEPLL_FUNC_CNTL_4 0xc0030603 1954 #define CG_VCEPLL_FUNC_CNTL_5 0xc0030604 1955 #define CG_VCEPLL_SPREAD_SPECTRUM 0xc0030606 1956 # define VCEPLL_SSEN_MASK 0x00000001 1957 1958 #endif 1959
Indexes created Sat Sep 20 22:09:52 GMT 2025