1 /* $NetBSD: veritefbreg.h,v 1.1 2026/07/11 15:18:21 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Register definitions for the Rendition Verite. 33 */ 34 35 #ifndef VERITEFBREG_H 36 #define VERITEFBREG_H 37 38 #define VFB_IO_BAR 0x14 /* I/O registers */ 39 #define VFB_FB_BAR 0x10 /* linear framebuffer aperture */ 40 #define VFB_MMIO_BAR 0x18 /* MMIO register/FIFO window */ 41 42 #define VFB_MMIO_REG_BASE 0x20000 43 44 /* 45 * Input FIFO windows: 32-bit writes, byte-swap variant selected by 46 * address. 47 */ 48 #define VFB_FIFO_SWAP_NO 0x00 /* no byte swap */ 49 #define VFB_FIFO_SWAP_END 0x04 /* swap bytes 3<>0, 2<>1 */ 50 #define VFB_FIFO_SWAP_INHW 0x08 /* swap bytes 3<>2, 1<>0 */ 51 #define VFB_FIFO_SWAP_HW 0x0c /* swap half-words */ 52 53 #define VFB_FIFOINFREE 0x40 /* input FIFO free entry count */ 54 #define VFB_FIFOINFREE_MASK 0x1f 55 #define VFB_FIFO_SIZE 0x1f 56 #define VFB_FIFOOUTVALID 0x41 /* output FIFO valid entry count */ 57 #define VFB_FIFOOUTVALID_MASK 0x07 58 59 #define VFB_COMM 0x42 /* dual 4-bit comm ports */ 60 #define VFB_COMM_SYSSTATUS_MASK 0x0f /* host -> RISC */ 61 #define VFB_COMM_RISCSTATUS_MASK 0xf0 /* RISC -> host, r/o */ 62 63 #define VFB_MEMENDIAN 0x43 /* aperture byte-swap policy */ 64 #define VFB_MEMENDIAN_NO 0 /* no byte swap */ 65 #define VFB_MEMENDIAN_END 1 /* swap bytes 3<>0, 2<>1 */ 66 #define VFB_MEMENDIAN_INHW 2 /* swap bytes 3<>2, 1<>0 */ 67 #define VFB_MEMENDIAN_HW 3 /* swap half-words */ 68 #define VFB_MEMENDIAN_MASK 3 69 70 #define VFB_INTR 0x44 /* interrupt status */ 71 #define VFB_INTREN 0x46 /* interrupt enable */ 72 #define VFB_INTR_VERT 0x01 /* vertical retrace */ 73 #define VFB_INTR_FIFOLOW 0x02 /* input FIFO above low water */ 74 #define VFB_INTR_RISC 0x04 /* RISC firmware interrupt */ 75 #define VFB_INTR_HALT 0x08 /* RISC halted */ 76 #define VFB_INTR_FIFOERROR 0x10 /* FIFO under/overflow */ 77 #define VFB_INTR_DMAERROR 0x20 /* PCI error during DMA */ 78 #define VFB_INTR_DMA 0x40 /* DMA done */ 79 #define VFB_INTR_X 0x80 /* external device passthrough */ 80 81 #define VFB_DEBUG 0x48 /* reset and RISC debug control */ 82 #define VFB_DEBUG_SOFTRESET 0x01 /* soft reset chip */ 83 #define VFB_DEBUG_HOLDRISC 0x02 /* hold RISC while set */ 84 #define VFB_DEBUG_STEPRISC 0x04 /* single-step RISC */ 85 #define VFB_DEBUG_DIRECTSCLK 0x08 /* no divide-by-2 for sys clock */ 86 #define VFB_DEBUG_SOFTVGARESET 0x10 /* assert VGA reset */ 87 #define VFB_DEBUG_SOFTXRESET 0x20 /* assert XReset to ext devices */ 88 89 #define VFB_LOWWATERMARK 0x49 /* input FIFO low water mark */ 90 91 #define VFB_STATUS 0x4a /* V2x00 only: busy blocks */ 92 #define VFB_STATUS_HOLD_MASK 0x8c /* must all be set before hold */ 93 #define VFB_STATUS_HELD 0x02 /* mirrors the Debug hold bit */ 94 95 #define VFB_XBUSCTL 0x4b /* V2x00 only */ 96 97 #define VFB_DMACMDPTR 0x50 /* DMA command list pointer */ 98 #define VFB_DMAADDRESS 0x54 /* DMA data address */ 99 #define VFB_DMACOUNT 0x58 /* DMA remaining transfer count */ 100 101 /* RISC state access window (debug port). */ 102 #define VFB_STATEINDEX 0x60 103 #define VFB_STATEDATA 0x64 104 #define VFB_STATEINDEX_IR 128 /* decoder instruction register */ 105 #define VFB_STATEINDEX_PC 129 /* program counter */ 106 #define VFB_STATEINDEX_S1 130 /* S1 operand bus */ 107 108 #define VFB_SCLKPLL 0x68 /* V2x00 only: system clock PLL */ 109 110 #define VFB_SCRATCH 0x70 /* 16-bit BIOS scratch space */ 111 112 #define VFB_MODE 0x72 /* legacy VGA vs native mode */ 113 #define VFB_MODE_VESA 0x01 /* enable 0xA0000 in native mode */ 114 #define VFB_MODE_VGA 0x02 /* VGA mode if set, else native */ 115 #define VFB_MODE_VGA32 0x04 /* enable VGA 32-bit accesses */ 116 #define VFB_MODE_DMAEN 0x08 /* enable DMA accesses */ 117 #define VFB_MODE_NATIVE 0x00 /* not VESA and not VGA */ 118 119 #define VFB_BANKSELECT 0x74 /* local memory to 0xA0000 mapping */ 120 121 /* CRTC */ 122 #define VFB_CRTCTEST 0x80 123 #define VFB_CRTCTEST_VIDEOLATENCY_MASK 0x1f 124 #define VFB_CRTCTEST_NOTVBLANK 0x10000 125 #define VFB_CRTCTEST_VBLANK 0x40000 126 127 #define VFB_CRTCCTL 0x84 128 #define VFB_CRTCCTL_SCRNFMT_MASK 0xf 129 #define VFB_CRTCCTL_VIDEOFIFOSIZE128 0x10 130 #define VFB_CRTCCTL_ENABLEDDC 0x20 131 #define VFB_CRTCCTL_DDCOUTPUT 0x40 132 #define VFB_CRTCCTL_DDCDATA 0x80 133 #define VFB_CRTCCTL_VSYNCHI 0x100 134 #define VFB_CRTCCTL_HSYNCHI 0x200 135 #define VFB_CRTCCTL_VSYNCENABLE 0x400 136 #define VFB_CRTCCTL_HSYNCENABLE 0x800 137 #define VFB_CRTCCTL_VIDEOENABLE 0x1000 138 #define VFB_CRTCCTL_STEREOSCOPIC 0x2000 139 #define VFB_CRTCCTL_FRAMEDISPLAYED 0x4000 140 #define VFB_CRTCCTL_FRAMEBUFFERBGR 0x8000 141 #define VFB_CRTCCTL_EVENFRAME 0x10000 142 #define VFB_CRTCCTL_LINEDOUBLE 0x20000 143 #define VFB_CRTCCTL_FRAMESWITCHED 0x40000 144 #define VFB_CRTCCTL_VIDEOFIFOSIZE256 0x800000 /* V2x00 only */ 145 146 /* 147 * CRTC horizontal timing 148 */ 149 #define VFB_CRTCHORZ 0x88 150 #define VFB_CRTCHORZ_ACTIVE_MASK 0xff 151 #define VFB_CRTCHORZ_BACKPORCH_MASK 0x7e00 152 #define VFB_CRTCHORZ_SYNC_MASK 0x1f0000 153 #define VFB_CRTCHORZ_FRONTPORCH_MASK 0xe00000 154 155 /* CRTC vertical timing */ 156 #define VFB_CRTCVERT 0x8c 157 #define VFB_CRTCVERT_ACTIVE_MASK 0x7ff 158 #define VFB_CRTCVERT_BACKPORCH_MASK 0x1f800 159 #define VFB_CRTCVERT_SYNC_MASK 0xe0000 160 #define VFB_CRTCVERT_FRONTPORCH_MASK 0x03f00000 161 162 #define VFB_FRAMEBASEB 0x90 /* stereoscopic frame base B */ 163 #define VFB_FRAMEBASEA 0x94 /* frame base A */ 164 165 #define VFB_CRTCOFFSET 0x98 166 #define VFB_CRTCOFFSET_MASK 0xffff 167 #define VFB_VIDEOFIFO_BYTES 128 /* with CRTCCTL VIDEOFIFOSIZE128 */ 168 #define VFB_CRTCSTATUS 0x9c /* video scan position */ 169 #define VFB_CRTCSTATUS_VERT_MASK 0xc00000 170 #define VFB_CRTCSTATUS_VERT_FPORCH 0x400000 171 #define VFB_CRTCSTATUS_VERT_SYNC 0xc00000 172 #define VFB_CRTCSTATUS_VERT_BPORCH 0x800000 173 #define VFB_CRTCSTATUS_VERT_ACTIVE 0x000000 174 175 /* 176 * Memory controller 177 */ 178 #define VFB_MEMCTL 0xa0 179 #define VFB_MEMCTL_ADRSWIZZLE_MASK 0x1800 180 #define VFB_MEMCTL_HOLDREFRESH 0x2000 181 #define VFB_MEMCTL_WREFRESH_MASK 0xff0000 182 #define VFB_MEMCTL_WREFRESH_DEFAULT 0x330000 183 184 #define VFB_MEMDIAG 0xa4 /* V2x00 only */ 185 #define VFB_CURSORBASE 0xac /* V2x00 only: bits [23:10] */ 186 187 /* 188 * Start of the register block that exists ONLY in PCI I/O space 189 */ 190 #define VFB_IOONLY_BASE 0xb0 191 192 /* RAMDAC, byte-wide registers */ 193 #define VFB_DACRAMWRITEADR 0xb0 194 #define VFB_DACRAMDATA 0xb1 195 #define VFB_DACPIXELMSK 0xb2 196 #define VFB_DACRAMREADADR 0xb3 197 #define VFB_DACOVSWRITEADR 0xb4 198 #define VFB_DACOVSDATA 0xb5 199 #define VFB_DACCOMMAND0 0xb6 200 #define VFB_DACOVSREADADR 0xb7 201 #define VFB_DACCOMMAND1 0xb8 202 #define VFB_DACCOMMAND2 0xb9 203 #define VFB_DACSTATUS 0xba 204 #define VFB_DACCOMMAND3 0xba /* via unlocking/indexing */ 205 #define VFB_DACCURSORDATA 0xbb 206 #define VFB_DACCURSORXLOW 0xbc 207 #define VFB_DACCURSORXHIGH 0xbd 208 #define VFB_DACCURSORYLOW 0xbe 209 #define VFB_DACCURSORYHIGH 0xbf 210 211 /* 212 * Pixel clock PLL (V2x00) 213 */ 214 #define VFB_PCLKPLL 0xc0 215 #define VFB_PCLKPLL_M_MASK __BITS(8, 0) 216 #define VFB_PCLKPLL_P_MASK __BITS(12, 9) 217 #define VFB_PCLKPLL_N_MASK __BITS(18, 13) 218 /* divider search bounds (the reference driver stays below field max) */ 219 #define VFB_PLL_M_MAX 0xff 220 #define VFB_PLL_N_MAX 0x3f 221 #define VFB_PLL_P_MAX 0x0f 222 /* the constraints above, in units of 10 Hz */ 223 #define VFB_PLL_PCF_MIN 100000 /* 1 MHz */ 224 #define VFB_PLL_PCF_MAX 300000 /* 3 MHz */ 225 #define VFB_PLL_VCO_MIN 12500000 /* 125 MHz */ 226 #define VFB_PLL_VCO_MAX 25000000 /* 250 MHz */ 227 #define VFB_PLL_STABILIZE_US 500 /* spec: 200 us */ 228 229 /* 230 * System/memory clock PLL (V2x00) 231 */ 232 #define VFB_SCLKPLL_DEFAULT 0xa484d 233 234 /* CRTCCTL ScrnFmt pixel format codes */ 235 #define VFB_PIXFMT_332 1 236 #define VFB_PIXFMT_8I 2 /* 8bpp indexed */ 237 #define VFB_PIXFMT_565 4 238 #define VFB_PIXFMT_4444 5 239 #define VFB_PIXFMT_1555 6 240 #define VFB_PIXFMT_8888 12 241 242 /* 243 * RAMDAC command register bits (Bt485-compatible core) 244 */ 245 #define VFB_DACCMD0_EXTENDED 0x80 /* enable cmd3 access */ 246 #define VFB_DACCMD0_8BITDAC 0x02 247 #define VFB_DACCMD1_24BPP 0x00 248 #define VFB_DACCMD1_16BPP 0x20 249 #define VFB_DACCMD1_8BPP 0x40 250 #define VFB_DACCMD1_BYPASS_CLUT 0x10 251 #define VFB_DACCMD1_565 0x08 252 #define VFB_DACCMD1_PORT_AB 0x00 253 #define VFB_DACCMD2_PIXEL_INPUT_GATE 0x20 254 #define VFB_DACCMD2_DISABLE_CURSOR 0x00 255 #define VFB_DACCMD2_CURSOR_MASK 0x03 256 #define VFB_DACCMD3_INDEX 0x01 /* index via DACRAMWRITEADR */ 257 #define VFB_DACCMD3_CLK_DOUBLER 0x08 258 259 #endif /* VERITEFBREG_H */ 260
Indexes created Sun Jul 12 00:26:10 UTC 2026