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    Searched defs:VGPR (Results 1 - 3 of 3) sorted by relevancy

  /src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
SIPeepholeSDWA.cpp 1182 Register VGPR = MRI->createVirtualRegister(&AMDGPU::VGPR_32RegClass);
1184 TII->get(AMDGPU::V_MOV_B32_e32), VGPR);
1190 Op.ChangeToRegister(VGPR, false);
SIFrameLowering.cpp 66 // 1: If there is already a VGPR with free lanes, use it. We
67 // may already have to pay the penalty for spilling a CSR VGPR.
79 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane
94 // so we're forced to spill another VGPR to use for the spill.
100 << printReg(Spill.VGPR, TRI) << ':' << Spill.Lane << '\n';);
715 // A StackID of SGPRSpill implies that this is a spill from SGPR to VGPR.
756 // VGPRs used for SGPR->VGPR spills
766 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, Reg.VGPR,
772 auto VGPR = Reg.first;
781 buildPrologSpill(ST, TRI, *FuncInfo, LiveRegs, MF, MBB, MBBI, VGPR, *FI)
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SIMachineFunctionInfo.h 442 Register VGPR;
446 SpilledReg(Register R, int L) : VGPR (R), Lane (L) {}
449 bool hasReg() { return VGPR != 0;}
453 // VGPR used for SGPR spills
454 Register VGPR;
456 // If the VGPR is is used for SGPR spills in a non-entrypoint function, the
460 SGPRSpillVGPR(Register V, Optional<int> F) : VGPR(V), FI(F) {}
468 // Map WWM VGPR to a stack slot that is used to save/restore it in the
473 // Track VGPR + wave index for each subregister of the SGPR spilled to
481 // AGPRs used for VGPR spills
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