1 /* 2 * Copyright 1998-2008 VIA Technologies, Inc. All Rights Reserved. 3 * Copyright 2001-2008 S3 Graphics, Inc. All Rights Reserved. 4 * 5 * Permission is hereby granted, free of charge, to any person obtaining a 6 * copy of this software and associated documentation files (the "Software"), 7 * to deal in the Software without restriction, including without limitation 8 * the rights to use, copy, modify, merge, publish, distribute, sub license, 9 * and/or sell copies of the Software, and to permit persons to whom the 10 * Software is furnished to do so, subject to the following conditions: 11 * 12 * The above copyright notice and this permission notice (including the 13 * next paragraph) shall be included in all copies or substantial portions 14 * of the Software. 15 * 16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR 17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, 18 * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. IN NO EVENT SHALL 19 * THE AUTHOR(S) OR COPYRIGHT HOLDER(S) BE LIABLE FOR ANY CLAIM, DAMAGES OR 20 * OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, 21 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER 22 * DEALINGS IN THE SOFTWARE. 23 */ 24 25 /************************************************************************* 26 * 27 * File: via_regs.c 28 * Content: The defines of Via registers 29 * 30 ************************************************************************/ 31 32 #ifndef _VIA_REGS_H_ 33 #define _VIA_REGS_H_ 1 34 35 #include "via_driver.h" 36 37 /*#define VIA_SERIES(chip) (chip == VIA_CLE266)*/ 38 39 40 /* Chip tags. These are used to group the adapters into 41 * related families. 42 */ 43 44 enum VIACHIPTAGS { 45 VIA_UNKNOWN = 0, 46 VIA_CLE266, 47 VIA_KM400, 48 VIA_K8M800, 49 VIA_PM800, 50 VIA_P4M800PRO, /* VT3314 */ 51 VIA_CX700, /* VT3324 */ 52 #ifdef VIA_VT3293_SUPPORT 53 VIA_CN750, /* VT3293 */ 54 #endif 55 VIA_P4M890, /* VT3327 */ 56 VIA_K8M890, /* VT3336 */ 57 VIA_P4M900, /* VT3364 */ 58 VIA_VX800, /* VT3353 */ 59 VIA_VX855, /* VT3409*/ 60 VIA_VX900, /* VT3410*/ 61 VIA_LAST 62 }; 63 64 65 #define PCI_VIA_VENDOR_ID 0x1106 66 67 #define PCI_CHIP_CLE3122 0x3122 /* CLE266 */ 68 #define PCI_CHIP_VT3205 0x7205 /* KM400 */ 69 #define PCI_CHIP_VT3204 0x3108 /* K8M800 */ 70 #define PCI_CHIP_VT3259 0x3118 /* PM800 */ 71 #define PCI_CHIP_VT3314 0x3344 /* P4M800 Pro */ 72 #define PCI_CHIP_VT3324 0x3157 /* CX700 */ 73 #ifdef VIA_VT3293_SUPPORT 74 #define PCI_CHIP_VT3293 0x3225 /* CN750 */ 75 #endif 76 #define PCI_CHIP_VT3327 0x3343 /* P4M890 */ 77 #define PCI_CHIP_VT3336 0x3230 /* K8M890 */ 78 #define PCI_CHIP_VT3364 0x3371 /* P4M900 */ 79 #define PCI_CHIP_VT3353 0x1122 /* VX800 */ 80 #define PCI_CHIP_VT3409 0x5122 /* VX855/VX875 */ 81 #define PCI_CHIP_VT3410 0x7122 /* VX900 */ 82 83 /* There is some conflicting information about the two major revisions of 84 * the CLE266, often labelled Ax and Cx. The dividing line seems to be 85 * either 0x0f or 0x10. */ 86 #define CLE266_REV_IS_AX(x) ((x) < 0x10) 87 #define CLE266_REV_IS_CX(x) ((x) >= 0x10) 88 89 #define BIOS_BSIZE 1024 90 #define BIOS_BASE 0xc0000 91 92 93 #define VIA_MMIO_REGSIZE 0xD000 /* DisplayPort: 0xC610~0xC7D4 */ 94 #define VIA_MMIO_REGBASE 0x0 95 #define VIA_MMIO_VGABASE 0x8000 96 #define VIA_MMIO_BLTBASE 0x200000 97 #define VIA_MMIO_BLTSIZE 0x200000 98 99 #define VIA_MMIO_INTEGRATED_TV_BASE 0xC000 100 #define VIA_MMIO_INTEGRATED_TV_SIZE 256 101 102 /* defines for VIA 2D registers */ 103 #define VIA_REG_GECMD 0x000 104 #define VIA_REG_GEMODE 0x004 105 #define VIA_REG_GESTATUS 0x004 /* as same as VIA_REG_GEMODE */ 106 #define VIA_REG_SRCPOS 0x008 107 #define VIA_REG_DSTPOS 0x00C 108 #define VIA_REG_LINE_K1K2 0x008 109 #define VIA_REG_LINE_XY 0x00C 110 #define VIA_REG_DIMENSION 0x010 /* width and height */ 111 #define VIA_REG_PATADDR 0x014 112 #define VIA_REG_FGCOLOR 0x018 113 #define VIA_REG_DSTCOLORKEY 0x018 /* as same as VIA_REG_FG */ 114 #define VIA_REG_BGCOLOR 0x01C 115 #define VIA_REG_SRCCOLORKEY 0x01C /* as same as VIA_REG_BG */ 116 #define VIA_REG_CLIPTL 0x020 /* top and left of clipping */ 117 #define VIA_REG_CLIPBR 0x024 /* bottom and right of clipping */ 118 #define VIA_REG_OFFSET 0x028 119 #define VIA_REG_LINE_ERROR 0x028 120 #define VIA_REG_KEYCONTROL 0x02C /* color key control */ 121 #define VIA_REG_SRCBASE 0x030 122 #define VIA_REG_DSTBASE 0x034 123 #define VIA_REG_PITCH 0x038 /* pitch of src and dst */ 124 #define VIA_REG_MONOPAT0 0x03C 125 #define VIA_REG_MONOPAT1 0x040 126 #define VIA_REG_ROT_TMP_ADDR 0x044 /* Rotation Temporary Base Address */ 127 #define VIA_REG_ROTSRC 0x048 /* Resolution X,Y of Rotation Source */ 128 #define VIA_REG_ROT_TMP_PITCH 0x04C /* Pitch of Rotation Temporary Memory */ 129 #define VIA_REG_ROTDST 0x050 /* Resolution X,Y of Rotation Destination*/ 130 #define VIA_REG_COLORPAT 0x100 /* from 0x100 to 0x1ff */ 131 132 /* defines for VIA 2D registers for vt3353 (M1 engine)*/ 133 #define VIA_REG_GECMD_M1 0x000 134 #define VIA_REG_GEMODE_M1 0x004 135 #define VIA_REG_GESTATUS_M1 0x004 /* as same as VIA_REG_GEMODE + rotate 410*/ 136 #define VIA_REG_PITCH_M1 0x008 /* pitch of src and dst */ 137 #define VIA_REG_DIMENSION_M1 0x00C /* width and height */ 138 #define VIA_REG_DSTPOS_M1 0x010 139 #define VIA_REG_LINE_XY_M1 0x010 140 #define VIA_REG_DSTBASE_M1 0x014 141 #define VIA_REG_SRCPOS_M1 0x018 142 #define VIA_REG_LINE_K1K2_M1 0x018 143 #define VIA_REG_SRCBASE_M1 0x01C 144 #define VIA_REG_PATADDR_M1 0x020 145 #define VIA_REG_MONOPAT0_M1 0x024 146 #define VIA_REG_MONOPAT1_M1 0x028 147 #define VIA_REG_OFFSET_M1 0x02C 148 #define VIA_REG_LINE_ERROR_M1 0x02C 149 #define VIA_REG_CLIPTL_M1 0x040 /* top and left of clipping */ 150 #define VIA_REG_CLIPBR_M1 0x044 /* bottom and right of clipping */ 151 #define VIA_REG_KEYCONTROL_M1 0x048 /* color key control */ 152 #define VIA_REG_FGCOLOR_M1 0x04C 153 #define VIA_REG_DSTCOLORKEY_M1 0x04C /* as same as VIA_REG_FG */ 154 #define VIA_REG_BGCOLOR_M1 0x050 155 #define VIA_REG_SRCCOLORKEY_M1 0x050 /* as same as VIA_REG_BG */ 156 #define VIA_REG_MONOPATFGC_M1 0x058 /* VT3353 Add Backgroung color of Pattern. */ 157 #define VIA_REG_MONOPATBGC_M1 0x05C /* VT3353 Add Foregroung color of Pattern. */ 158 #define VIA_REG_COLORPAT_M1 0x100 /* from 0x100 to 0x1ff */ 159 160 /*410*/ 161 #define VIA_REG_CFC 0x030 162 #define VIA_REG_SCALEFACTOR 0x034 163 #define VIA_REG_SCALINGMODE 0x038 164 #define VIA_REG_23DIDCLT 0x060 165 #define VIA_REG_23DWAITCLT 0x06C 166 /* defines for VIA video registers */ 167 #define VIA_REG_INTERRUPT 0x200 168 #define VIA_REG_CRTCSTART 0x214 169 170 171 /* defines for VIA HW cursor registers */ 172 #define VIA_REG_CURSOR_MODE 0x2D0 173 #define VIA_REG_CURSOR_POS 0x2D4 174 #define VIA_REG_CURSOR_ORG 0x2D8 175 #define VIA_REG_CURSOR_BG 0x2DC 176 #define VIA_REG_CURSOR_FG 0x2E0 177 178 179 /* defines for VIA 3D registers */ 180 #define VIA_REG_STATUS 0x400 181 #define VIA_REG_TRANSET 0x43C 182 #define VIA_REG_TRANSPACE 0x440 183 184 /* VIA_REG_STATUS(0x400): Engine Status */ 185 #define VIA_CMD_RGTR_BUSY 0x00000080 /* Command Regulator is busy */ 186 #define VIA_2D_ENG_BUSY 0x00000002 /* 2D Engine is busy */ 187 #define VIA_3D_ENG_BUSY 0x00000001 /* 3D Engine is busy */ 188 #define VIA_VR_QUEUE_EMPTY 0x00020000 /* Virtual Queue is empty */ 189 190 /* VIA_REG_STATUS(0x400): Engine Status for H5 */ 191 #define VIA_CMD_RGTR_BUSY_H5 0x00000010 /* Command Regulator is busy */ 192 #define VIA_2D_ENG_BUSY_H5 0x00000002 /* 2D Engine is busy */ 193 #define VIA_3D_ENG_BUSY_H5 0x00001FE1 /* 3D Engine is busy */ 194 #define VIA_VR_QUEUE_BUSY_H5 0x00000004 /* Virtual Queue is busy */ 195 196 /* VIA_REG_STATUS(0x400): Engine Status for VT3353 */ 197 #define VIA_CMD_RGTR_BUSY_M1 0x00000010 /* Command Regulator is busy */ 198 #define VIA_2D_ENG_BUSY_M1 0x00000002 /* 2D Engine is busy */ 199 #define VIA_3D_ENG_BUSY_M1 0x00001FE1 /* 3D Engine is busy */ 200 #define VIA_VR_QUEUE_BUSY_M1 0x00000004 /* Virtual Queue is busy */ 201 202 /* VIA_REG_GECMD(0x00): 2D Engine Command */ 203 #define VIA_GEC_NOOP 0x00000000 204 #define VIA_GEC_BLT 0x00000001 205 #define VIA_GEC_LINE 0x00000005 206 /*410 GECMD*/ 207 #define VIA_GEC_ALPHA 0x00000003 208 #define VIA_GEC_BLT_ROT 0x00000009 209 #define VIA_GEC_MONOTEX 0x00000002 210 #define VIA_GEC_ALPHA_ROT_MONOTEX 0x0000000a 211 212 #define VIA_GEC_ROT 0x00000008 /* Rotate Command */ 213 214 #define VIA_GEC_SRC_XY 0x00000000 215 #define VIA_GEC_SRC_LINEAR 0x00000010 216 #define VIA_GEC_DST_XY 0x00000000 217 #define VIA_GEC_DST_LINRAT 0x00000020 218 219 #define VIA_GEC_SRC_FB 0x00000000 220 #define VIA_GEC_SRC_SYS 0x00000040 221 #define VIA_GEC_DST_FB 0x00000000 222 #define VIA_GEC_DST_SYS 0x00000080 223 224 #define VIA_GEC_SRC_MONO 0x00000100 /* source is mono */ 225 #define VIA_GEC_PAT_MONO 0x00000200 /* pattern is mono */ 226 227 #define VIA_GEC_MSRC_OPAQUE 0x00000000 /* mono src is opaque */ 228 #define VIA_GEC_MSRC_TRANS 0x00000400 /* mono src is transparent */ 229 230 #define VIA_GEC_PAT_FB 0x00000000 /* pattern is in frame buffer */ 231 #define VIA_GEC_PAT_REG 0x00000800 /* pattern is from reg setting */ 232 233 #define VIA_GEC_CLIP_DISABLE 0x00000000 234 #define VIA_GEC_CLIP_ENABLE 0x00001000 235 236 #define VIA_GEC_FIXCOLOR_PAT 0x00002000 237 238 #define VIA_GEC_INCX 0x00000000 239 #define VIA_GEC_DECY 0x00004000 240 #define VIA_GEC_INCY 0x00000000 241 #define VIA_GEC_DECX 0x00008000 242 243 #define VIA_GEC_MPAT_OPAQUE 0x00000000 /* mono pattern is opaque */ 244 #define VIA_GEC_MPAT_TRANS 0x00010000 /* mono pattern is transparent */ 245 246 #define VIA_GEC_MONO_UNPACK 0x00000000 247 #define VIA_GEC_MONO_PACK 0x00020000 248 #define VIA_GEC_MONO_DWORD 0x00000000 249 #define VIA_GEC_MONO_WORD 0x00040000 250 #define VIA_GEC_MONO_BYTE 0x00080000 251 252 #define VIA_GEC_LASTPIXEL_ON 0x00000000 253 #define VIA_GEC_LASTPIXEL_OFF 0x00100000 254 #define VIA_GEC_X_MAJOR 0x00000000 255 #define VIA_GEC_Y_MAJOR 0x00200000 256 #define VIA_GEC_QUICK_START 0x00800000 257 258 259 /* VIA_REG_GEMODE(0x04): GE mode */ 260 #define VIA_GEM_8bpp 0x00000000 261 #define VIA_GEM_16bpp 0x00000100 262 #define VIA_GEM_32bpp 0x00000300 263 /*410 GEM*/ 264 #define VIA_GEM_ALPHA 0x00100000 265 #define VIA_GEM_degree90 0x00000001 266 #define VIA_GEM_degree180 0x00000002 267 #define VIA_GEM_degree270 0x00000303 268 #define VIA_GEM_ALPHA_CNT_EN 0x00100000 269 #define VIA_GEM_SETALPHA8(cnst) (cnst>>24)<<12 270 /*410 SCALE*/ 271 #define VIA_SCALEF_VFactor8(cnst) cnst<<20 272 #define VIA_SCALEF_HFactor8(cnst) cnst<<4 273 #define VIA_SCALEM_En 0x80000000 274 #define VIA_SCALEM_Shrink 0x40000000 275 #define VIA_SCALEM_BW 0x00000000 276 #define VIA_SCALEM_WB 0x10000000 277 #define VIA_SCALEM_CC 0x20000000 278 #define VIA_SCALEM_Half 0x30000000 279 #define VIA_SCALEM_SrcDimenH12(cnst) (cnst-1)<<16 280 #define VIA_SCALEM_SrcDimenW12(cnst) (cnst-1)<<0 281 /*410 CFC new 2D pipline must set ??*/ 282 #define VIA_CFC_en 0x80000000 283 #define VIA_CFC_EXT_en 0x40000000 284 #define VIA_CFC_DITH_en 0x20000000 285 #define VIA_CFC_DesCF16_555 0x00000000 286 #define VIA_CFC_DesCF16_565 0x00000100 287 #define VIA_CFC_DesCF32_888 0x00000000 288 #define VIA_CFC_DesCF32_000 0x00000100 289 #define VIA_CFC_SrcDep8 0x00000000 290 #define VIA_CFC_SrcDep16 0x00000050 291 #define VIA_CFC_SrcDep32 0x000000c0 292 #define VIA_CFC_SrcCF16_555 0x00000000 293 #define VIA_CFC_SrcCF16_565 0x00000001 294 #define VIA_CFC_SrcCF32_888 0x00000000 295 #define VIA_CFC_SrcCF32_000 0x00000001 296 297 #define VIA_GEM_640 0x00000000 /* 640*480 */ 298 #define VIA_GEM_800 0x00000400 /* 800*600 */ 299 #define VIA_GEM_1024 0x00000800 /* 1024*768 */ 300 #define VIA_GEM_1280 0x00000C00 /* 1280*1024 */ 301 #define VIA_GEM_1600 0x00001000 /* 1600*1200 */ 302 #define VIA_GEM_2048 0x00001400 /* 2048*1536 */ 303 304 #define VIA_GEM_ROTATE_90 0x00000001 /* Rotate anticlockwise 90 degree */ 305 #define VIA_GEM_ROTATE_180 0x00000002 /* Rotate anticlockwise 180 degree */ 306 #define VIA_GEM_ROTATE_270 0x00000003 /* Rotate anticlockwise 270 degree */ 307 308 /* VIA_REG_PITCH(0x38): Pitch Setting */ 309 #define VIA_PITCH_ENABLE 0x80000000 310 311 312 #define MAXLOOP 0xffffff 313 314 315 #define VerticalRetraceWait() \ 316 { \ 317 VGAOUT8(vgaCRIndex, 0x17); \ 318 if (VGAIN8(vgaCRReg) & 0x80) { \ 319 while ((VGAIN8(vgaIOBase + 0x0a) & 0x08) == 0x00) ; \ 320 while ((VGAIN8(vgaIOBase + 0x0a) & 0x08) == 0x08) ; \ 321 while ((VGAIN8(vgaIOBase + 0x0a) & 0x08) == 0x00) ; \ 322 } \ 323 } 324 325 326 #define VIASETREG(addr, data) *(volatile unsigned int *)(pVia->MapBase + (addr)) = (data) 327 #define VIAGETREG(addr) *(volatile unsigned int *)(pVia->MapBase + (addr)) 328 329 330 #endif /* _VIA_REGS_H_ */ 331
Indexes created Sun Aug 09 00:24:28 UTC 2026