1 /* $NetBSD: cx23885reg.h,v 1.2 2011/08/09 11:26:40 jmcneill Exp $ */ 2 3 /* 4 * Copyright (c) 2008, 2011 Jonathan A. Kollasch 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 18 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 19 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR 20 * CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, 21 * EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, 22 * PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; 23 * OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, 24 * WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR 25 * OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF 26 * ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 27 */ 28 29 #ifndef _DEV_PCI_CX23885REG_H 30 #define _DEV_PCI_CX23885REG_H 31 32 #include <dev/pci/pcireg.h> 33 34 #define CX23885_MMBASE PCI_BAR(0) 35 36 /* misc. registers */ 37 38 #define DEV_CNTRL2 0x040000 39 #define PCI_INT_MSK 0x040010 40 #define PCI_INT_STAT 0x040014 41 #define PCI_INT_MSTAT 0x040018 42 43 #define VID_C_INT_MSK 0x040040 44 #define VID_C_INT_STAT 0x040044 45 #define VID_C_INT_MSTAT 0x040048 46 #define VID_C_INT_SSTAT 0x04004c 47 48 #define DMA5_PTR1 0x100010 49 #define DMA5_PTR2 0x100050 50 #define DMA5_CNT1 0x100090 51 #define DMA5_CNT2 0x1000d0 52 53 /* GPIO */ 54 #define GP0_IO 0x110010 55 #define GPIO_ISM 0x110014 56 #define SOFT_RESET 0x11001c 57 58 #define CLK_DELAY 0x110048 59 #define PAD_CTRL 0x11004c 60 61 /* Video C Interface */ 62 #define VID_C_GPCNT 0x130220 63 #define VID_C_GPCNT_CTL 0x130230 64 #define VBI_C_GPCNT_CTL 0x130234 65 #define VID_C_DMA_CTL 0x130240 66 #define VID_C_LNGTH 0x130250 67 #define VID_C_HW_SOP_CTL 0x130254 68 #define VID_C_GEN_CTL 0x130258 69 #define VID_C_BD_PKT_STATUS 0x13025c 70 #define VID_C_SOP_STATUS 0x130260 71 #define VID_C_FIFO_OVFL_STAT 0x130264 72 #define VID_C_VLD_MISC 0x130268 73 #define VID_C_TS_CLK_EN 0x13026c 74 75 /* serial controllers */ 76 #define I2C_BASE 0x180000 77 #define I2C_SIZE 0x010000 78 #define I2C_NUM 3 79 80 /* RISC instructions */ 81 82 #define CX_RISC_WRITECR 0xd0000000 83 #define CX_RISC_WRITECM 0xc0000000 84 #define CX_RISC_WRITERM 0xb0000000 85 #define CX_RISC_READC 0xa0000000 86 #define CX_RISC_READ 0x90000000 87 #define CX_RISC_SYNC 0x80000000 88 #define CX_RISC_JUMP 0x70000000 89 #define CX_RISC_WRITEC 0x50000000 90 #define CX_RISC_SKIP 0x20000000 91 #define CX_RISC_WRITE 0x10000000 92 #define CX_RISC_SOL 0x08000000 93 #define CX_RISC_EOL 0x04000000 94 #define CX_RISC_IRQ2 0x02000000 95 #define CX_RISC_IRQ1 0x01000000 96 #define CX_RISC_IMM 0x00000001 97 #define CX_RISC_SRP 0x00000001 98 99 #define CX_CNT_CTL_NOOP 0x0 100 #define CX_CNT_CTL_INCR 0x1 101 #define CX_CNT_CTL_ZERO 0x3 102 #define CX_RISC_CNT_CTL __BITS(17,16) 103 #define CX_RISC_CNT_CTL_NOOP __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_NOOP) 104 #define CX_RISC_CNT_CTL_INCR __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_INCR) 105 #define CX_RISC_CNT_CTL_ZERO __SHIFTIN(CX_RISC_CNT_CTL,CX_CNT_CTL_ZERO) 106 107 /* Channel Management Data Structure */ 108 /* offsets */ 109 #define CMDS_O_IRPC 0x00 110 #define CMDS_O_CDTB 0x08 111 #define CMDS_O_CDTS 0x0c 112 #define CMDS_O_IQB 0x10 113 #define CMDS_O_IQS 0x14 114 115 /* bits */ 116 #define CMDS_IQS_ISRP __BIT(31) 117 118 #endif /* !_DEV_PCI_CX23885REG_H */ 119
Indexes created Mon Sep 22 10:09:38 GMT 2025