1 /* $NetBSD: intel_sideband.h,v 1.3 2021/12/19 11:38:04 riastradh Exp $ */ 2 3 /* SPDX-License-Identifier: MIT */ 4 5 #ifndef _INTEL_SIDEBAND_H_ 6 #define _INTEL_SIDEBAND_H_ 7 8 #include <linux/bitops.h> 9 #include <linux/types.h> 10 11 #include <sys/file.h> 12 #define pipe pipe_drmhack /* see intel_display.h */ 13 14 struct drm_i915_private; 15 enum pipe; 16 17 enum intel_sbi_destination { 18 SBI_ICLK, 19 SBI_MPHY, 20 }; 21 22 enum { 23 VLV_IOSF_SB_BUNIT, 24 VLV_IOSF_SB_CCK, 25 VLV_IOSF_SB_CCU, 26 VLV_IOSF_SB_DPIO, 27 VLV_IOSF_SB_FLISDSI, 28 VLV_IOSF_SB_GPIO, 29 VLV_IOSF_SB_NC, 30 VLV_IOSF_SB_PUNIT, 31 }; 32 33 void vlv_iosf_sb_get(struct drm_i915_private *i915, unsigned long ports); 34 u32 vlv_iosf_sb_read(struct drm_i915_private *i915, u8 port, u32 reg); 35 void vlv_iosf_sb_write(struct drm_i915_private *i915, 36 u8 port, u32 reg, u32 val); 37 void vlv_iosf_sb_put(struct drm_i915_private *i915, unsigned long ports); 38 39 static inline void vlv_bunit_get(struct drm_i915_private *i915) 40 { 41 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_BUNIT)); 42 } 43 44 u32 vlv_bunit_read(struct drm_i915_private *i915, u32 reg); 45 void vlv_bunit_write(struct drm_i915_private *i915, u32 reg, u32 val); 46 47 static inline void vlv_bunit_put(struct drm_i915_private *i915) 48 { 49 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_BUNIT)); 50 } 51 52 static inline void vlv_cck_get(struct drm_i915_private *i915) 53 { 54 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCK)); 55 } 56 57 u32 vlv_cck_read(struct drm_i915_private *i915, u32 reg); 58 void vlv_cck_write(struct drm_i915_private *i915, u32 reg, u32 val); 59 60 static inline void vlv_cck_put(struct drm_i915_private *i915) 61 { 62 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCK)); 63 } 64 65 static inline void vlv_ccu_get(struct drm_i915_private *i915) 66 { 67 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_CCU)); 68 } 69 70 u32 vlv_ccu_read(struct drm_i915_private *i915, u32 reg); 71 void vlv_ccu_write(struct drm_i915_private *i915, u32 reg, u32 val); 72 73 static inline void vlv_ccu_put(struct drm_i915_private *i915) 74 { 75 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_CCU)); 76 } 77 78 static inline void vlv_dpio_get(struct drm_i915_private *i915) 79 { 80 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_DPIO)); 81 } 82 83 u32 vlv_dpio_read(struct drm_i915_private *i915, enum pipe pipe, int reg); 84 void vlv_dpio_write(struct drm_i915_private *i915, 85 enum pipe pipe, int reg, u32 val); 86 87 static inline void vlv_dpio_put(struct drm_i915_private *i915) 88 { 89 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_DPIO)); 90 } 91 92 static inline void vlv_flisdsi_get(struct drm_i915_private *i915) 93 { 94 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_FLISDSI)); 95 } 96 97 u32 vlv_flisdsi_read(struct drm_i915_private *i915, u32 reg); 98 void vlv_flisdsi_write(struct drm_i915_private *i915, u32 reg, u32 val); 99 100 static inline void vlv_flisdsi_put(struct drm_i915_private *i915) 101 { 102 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_FLISDSI)); 103 } 104 105 static inline void vlv_nc_get(struct drm_i915_private *i915) 106 { 107 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_NC)); 108 } 109 110 u32 vlv_nc_read(struct drm_i915_private *i915, u8 addr); 111 112 static inline void vlv_nc_put(struct drm_i915_private *i915) 113 { 114 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_NC)); 115 } 116 117 static inline void vlv_punit_get(struct drm_i915_private *i915) 118 { 119 vlv_iosf_sb_get(i915, BIT(VLV_IOSF_SB_PUNIT)); 120 } 121 122 u32 vlv_punit_read(struct drm_i915_private *i915, u32 addr); 123 int vlv_punit_write(struct drm_i915_private *i915, u32 addr, u32 val); 124 125 static inline void vlv_punit_put(struct drm_i915_private *i915) 126 { 127 vlv_iosf_sb_put(i915, BIT(VLV_IOSF_SB_PUNIT)); 128 } 129 130 u32 intel_sbi_read(struct drm_i915_private *i915, u16 reg, 131 enum intel_sbi_destination destination); 132 void intel_sbi_write(struct drm_i915_private *i915, u16 reg, u32 value, 133 enum intel_sbi_destination destination); 134 135 int sandybridge_pcode_read(struct drm_i915_private *i915, u32 mbox, 136 u32 *val, u32 *val1); 137 int sandybridge_pcode_write_timeout(struct drm_i915_private *i915, u32 mbox, 138 u32 val, int fast_timeout_us, 139 int slow_timeout_ms); 140 #define sandybridge_pcode_write(i915, mbox, val) \ 141 sandybridge_pcode_write_timeout(i915, mbox, val, 500, 0) 142 143 int skl_pcode_request(struct drm_i915_private *i915, u32 mbox, u32 request, 144 u32 reply_mask, u32 reply, int timeout_base_ms); 145 146 #endif /* _INTEL_SIDEBAND_H */ 147