1 /* $NetBSD: vme_tworeg.h,v 1.2 2008/04/28 20:23:54 martin Exp $ */ 2 3 /*- 4 * Copyright (c) 1999, 2002 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Steve C. Woodford. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE NETBSD FOUNDATION, INC. AND CONTRIBUTORS 20 * ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED 21 * TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR 22 * PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE FOUNDATION OR CONTRIBUTORS 23 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 24 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 25 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 26 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 27 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 28 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 29 * POSSIBILITY OF SUCH DAMAGE. 30 */ 31 32 #ifndef _MVME_VME_TWOREG_H 33 #define _MVME_VME_TWOREG_H 34 35 /* 36 * Where the VMEchip2's registers live relative to the start 37 * of the VMEChip2's register space. 38 */ 39 #define VME2REG_LCSR_OFFSET 0x0000 40 #define VME2REG_GCSR_OFFSET 0x0100 41 42 43 /* 44 * Register map of the Type 2 VMEchip found on many MVME boards. 45 * Note: Only responds to D32 accesses. 46 */ 47 48 /* 49 * Slave window configuration registers 50 */ 51 #define VME2_SLAVE_WINDOWS 2 52 #define VME2LCSR_SLAVE_ADDRESS(x) (0x00 + ((x) * 4)) 53 #define VME2_SLAVE_ADDRESS_START_SHIFT 16 54 #define VME2_SLAVE_ADDRESS_START_MASK (0x0000ffffu) 55 #define VME2_SLAVE_ADDRESS_END_SHIFT 0 56 #define VME2_SLAVE_ADDRESS_END_MASK (0xffff0000u) 57 58 #define VME2LCSR_SLAVE_TRANS(x) (0x08 + ((x) * 4)) 59 #define VME2_SLAVE_TRANS_SELECT_SHIFT 16 60 #define VME2_SLAVE_TRANS_SELECT_MASK (0x0000ffffu) 61 #define VME2_SLAVE_TRANS_ADDRESS_SHIFT 0 62 #define VME2_SLAVE_TRANS_ADDRESS_MASK (0xffff0000u) 63 64 #define VME2LCSR_SLAVE_CTRL 0x10 65 #define VME2_SLAVE_AMSEL_DAT(x) (1u << (0 + ((x) * 16))) 66 #define VME2_SLAVE_AMSEL_PGM(x) (1u << (1 + ((x) * 16))) 67 #define VME2_SLAVE_AMSEL_BLK(x) (1u << (2 + ((x) * 16))) 68 #define VME2_SLAVE_AMSEL_BLKD64(x) (1u << (3 + ((x) * 16))) 69 #define VME2_SLAVE_AMSEL_A24(x) (1u << (4 + ((x) * 16))) 70 #define VME2_SLAVE_AMSEL_A32(x) (1u << (5 + ((x) * 16))) 71 #define VME2_SLAVE_AMSEL_USR(x) (1u << (6 + ((x) * 16))) 72 #define VME2_SLAVE_AMSEL_SUP(x) (1u << (7 + ((x) * 16))) 73 #define VME2_SLAVE_CTRL_WP(x) (1u << (8 + ((x) * 16))) 74 #define VME2_SLAVE_CTRL_SNOOP_INHIBIT(x) (0u << (9 + ((x) * 16))) 75 #define VME2_SLAVE_CTRL_SNOOP_WRSINK(x) (1u << (9 + ((x) * 16))) 76 #define VME2_SLAVE_CTRL_SNOOP_WRINVAL(x) (2u << (9 + ((x) * 16))) 77 #define VME2_SLAVE_CTRL_ADDER(x) (1u << (11 + ((x) * 16))) 78 79 /* 80 * Master window address control registers 81 */ 82 #define VME2_MASTER_WINDOWS 4 83 #define VME2LCSR_MASTER_ADDRESS(x) (0x14 + ((x) * 4)) 84 #define VME2_MAST_ADDRESS_START_SHIFT 16 85 #define VME2_MAST_ADDRESS_START_MASK (0x0000ffffu) 86 #define VME2_MAST_ADDRESS_END_SHIFT 0 87 #define VME2_MAST_ADDRESS_END_MASK (0xffff0000u) 88 89 #define VME2LCSR_MAST4_TRANS 0x24 90 #define VME2_MAST4_TRANS_SELECT_SHIFT 16 91 #define VME2_MAST4_TRANS_SELECT_MASK (0x0000ffffu) 92 #define VME2_MAST4_TRANS_ADDRESS_SHIFT 0 93 #define VME2_MAST4_TRANS_ADDRESS_MASK (0xffff0000u) 94 95 /* 96 * VMEbus master attribute control register 97 */ 98 #define VME2LCSR_MASTER_ATTR 0x28 99 #define VME2_MASTER_ATTR_AM_SHIFT(x) ((x) * 8) 100 #define VME2_MASTER_ATTR_AM_MASK (0x0000003fu) 101 #define VME2_MASTER_ATTR_WP (1u << 6) 102 #define VME2_MASTER_ATTR_D16 (1u << 7) 103 104 /* 105 * GCSR Group/Board addresses, and 106 * VMEbus Master Enable Control register, and 107 * Local to VMEbus I/O Control register, and 108 * ROM Control register (unused). 109 */ 110 #define VME2LCSR_GCSR_ADDRESS 0x2c 111 #define VME2_GCSR_ADDRESS_SHIFT 16 112 #define VME2_GCSR_ADDRESS_MASK (0xfff00000u) 113 114 #define VME2LCSR_MASTER_ENABLE 0x2c 115 #define VME2_MASTER_ENABLE_MASK (0x000f0000u) 116 #define VME2_MASTER_ENABLE(x) (1u << ((x) + 16)) 117 118 #define VME2LCSR_IO_CONTROL 0x2c 119 #define VME2_IO_CONTROL_SHIFT 8 120 #define VME2_IO_CONTROL_MASK (0x0000ff00u) 121 #define VME2_IO_CONTROL_I1SU (1u << 8) 122 #define VME2_IO_CONTROL_I1WP (1u << 9) 123 #define VME2_IO_CONTROL_I1D16 (1u << 10) 124 #define VME2_IO_CONTROL_I1EN (1u << 11) 125 #define VME2_IO_CONTROL_I2PD (1u << 12) 126 #define VME2_IO_CONTROL_I2SU (1u << 13) 127 #define VME2_IO_CONTROL_I2WP (1u << 14) 128 #define VME2_IO_CONTROL_I2EN (1u << 15) 129 130 /* 131 * VMEChip2 PROM Decoder, SRAM and DMA Control register 132 */ 133 #define VME2LCSR_PROM_SRAM_DMA_CTRL 0x30 134 #define VME2_PSD_SRAMS_MASK (0x00ff0000u) 135 #define VME2_PSD_SRAMS_CLKS6 (0u << 16) 136 #define VME2_PSD_SRAMS_CLKS5 (1u << 16) 137 #define VME2_PSD_SRAMS_CLKS4 (2u << 16) 138 #define VME2_PSD_SRAMS_CLKS3 (3u << 16) 139 #define VME2_PSD_TBLSC_INHIB (0u << 18) 140 #define VME2_PSD_TBLSC_WRSINK (1u << 18) 141 #define VME2_PSD_TBLSC_WRINV (2u << 18) 142 #define VME2_PSD_ROM0 (1u << 20) 143 #define VME2_PSD_WAITRMW (1u << 21) 144 145 /* 146 * VMEbus requester control register 147 */ 148 #define VME2LCSR_VME_REQUESTER_CONTROL 0x30 149 #define VME2_VMEREQ_CTRL_MASK (0x0000ff00u) 150 #define VME2_VMEREQ_CTRL_LVREQL_MASK (0x00000300u) 151 #define VME2_VMEREQ_CTRL_LVREQL(x) ((u_int)(x) << 8) 152 #define VME2_VMEREQ_CTRL_LVRWD (1u << 10) 153 #define VME2_VMEREQ_CTRL_LVFAIR (1u << 11) 154 #define VME2_VMEREQ_CTRL_DWB (1u << 13) 155 #define VME2_VMEREQ_CTRL_DHB (1u << 14) 156 #define VME2_VMEREQ_CTRL_ROBN (1u << 15) 157 158 /* 159 * DMAC control register 160 */ 161 #define VME2LCSR_DMAC_CONTROL1 0x30 162 #define VME2_DMAC_CTRL1_MASK (0x000000ffu) 163 #define VME2_DMAC_CTRL1_DREQL_MASK (0x00000003u) 164 #define VME2_DMAC_CTRL1_DREQL(x) ((u_int)(x) << 0) 165 #define VME2_DMAC_CTRL1_DRELM_MASK (0x0000000cu) 166 #define VME2_DMAC_CTRL1_DRELM(x) ((u_int)(x) << 2) 167 #define VME2_DMAC_CTRL1_DFAIR (1u << 4) 168 #define VME2_DMAC_CTRL1_DTBL (1u << 5) 169 #define VME2_DMAC_CTRL1_DEN (1u << 6) 170 #define VME2_DMAC_CTRL1_DHALT (1u << 7) 171 172 /* 173 * DMA Control register #2 174 */ 175 #define VME2LCSR_DMAC_CONTROL2 0x34 176 #define VME2_DMAC_CTRL2_MASK (0x0000ffffu) 177 #define VME2_DMAC_CTRL2_SHIFT 0 178 #define VME2_DMAC_CTRL2_AM_MASK (0x0000003fu) 179 #define VME2_DMAC_CTRL2_BLK_D32 (1u << 6) 180 #define VME2_DMAC_CTRL2_BLK_D64 (3u << 6) 181 #define VME2_DMAC_CTRL2_D16 (1u << 8) 182 #define VME2_DMAC_CTRL2_TVME (1u << 9) 183 #define VME2_DMAC_CTRL2_LINC (1u << 10) 184 #define VME2_DMAC_CTRL2_VINC (1u << 11) 185 #define VME2_DMAC_CTRL2_SNOOP_INHIB (0u << 13) 186 #define VME2_DMAC_CTRL2_SNOOP_WRSNK (1u << 13) 187 #define VME2_DMAC_CTRL2_SNOOP_WRINV (2u << 13) 188 #define VME2_DMAC_CTRL2_INTE (1u << 15) 189 190 /* 191 * DMA Controller Local Bus and VMEbus Addresses, Byte 192 * Counter and Table Address Counter registers 193 */ 194 #define VME2LCSR_DMAC_LOCAL_ADDRESS 0x38 195 #define VME2LCSR_DMAC_VME_ADDRESS 0x3c 196 #define VME2LCSR_DMAC_BYTE_COUNTER 0x40 197 #define VME2LCSR_DMAC_TABLE_ADDRESS 0x44 198 199 /* 200 * VMEbus Interrupter Control register 201 */ 202 #define VME2LCSR_INTERRUPT_CONTROL 0x48 203 #define VME2_INT_CTRL_MASK (0xff000000u) 204 #define VME2_INT_CTRL_SHIFT 24 205 #define VME2_INT_CTRL_IRQL_MASK (0x07000000u) 206 #define VME2_INT_CTRL_IRQS (1u << 27) 207 #define VME2_INT_CTRL_IRQC (1u << 28) 208 #define VME2_INT_CTRL_IRQ1S_INT (0u << 29) 209 #define VME2_INT_CTRL_IRQ1S_TICK1 (1u << 29) 210 #define VME2_INT_CTRL_IRQ1S_TICK2 (3u << 29) 211 212 /* 213 * VMEbus Interrupt Vector register 214 */ 215 #define VME2LCSR_INTERRUPT_VECTOR 0x48 216 #define VME2_INTERRUPT_VECTOR_MASK (0x00ff0000u) 217 #define VME2_INTERRUPT_VECTOR_SHIFT 16 218 219 /* 220 * MPU Status register 221 */ 222 #define VME2LCSR_MPU_STATUS 0x48 223 #define VME2_MPU_STATUS_MLOB (1u << 0) 224 #define VME2_MPU_STATUS_MLPE (1u << 1) 225 #define VME2_MPU_STATUS_MLBE (1u << 2) 226 #define VME2_MPU_STATUS_MCLR (1u << 3) 227 228 /* 229 * DMA Interrupt Count register 230 */ 231 #define VME2LCSR_DMAC_INTERRUPT_CONTROL 0x48 232 #define VME2_DMAC_INT_COUNT_MASK (0x0000f000u) 233 #define VME2_DMAC_INT_COUNT_SHIFT 12 234 235 /* 236 * DMA Controller Status register 237 */ 238 #define VME2LCSR_DMAC_STATUS 0x48 239 #define VME2_DMAC_STATUS_DONE (1u << 0) 240 #define VME2_DMAC_STATUS_VME (1u << 1) 241 #define VME2_DMAC_STATUS_TBL (1u << 2) 242 #define VME2_DMAC_STATUS_DLTO (1u << 3) 243 #define VME2_DMAC_STATUS_DLOB (1u << 4) 244 #define VME2_DMAC_STATUS_DLPE (1u << 5) 245 #define VME2_DMAC_STATUS_DLBE (1u << 6) 246 #define VME2_DMAC_STATUS_MLTO (1u << 7) 247 248 249 /* 250 * VMEbus Arbiter Time-out register 251 */ 252 #define VME2LCSR_VME_ARB_TIMEOUT 0x4c 253 #define VME2_VME_ARB_TIMEOUT_ENAB (1u << 24) 254 255 /* 256 * DMA Controller Timers and VMEbus Global Time-out Control registers 257 */ 258 #define VME2LCSR_DMAC_TIME_ONOFF 0x4c 259 #define VME2_DMAC_TIME_ON_MASK (0x001c0000u) 260 #define VME2_DMAC_TIME_ON_16US (0u << 18) 261 #define VME2_DMAC_TIME_ON_32US (1u << 18) 262 #define VME2_DMAC_TIME_ON_64US (2u << 18) 263 #define VME2_DMAC_TIME_ON_128US (3u << 18) 264 #define VME2_DMAC_TIME_ON_256US (4u << 18) 265 #define VME2_DMAC_TIME_ON_512US (5u << 18) 266 #define VME2_DMAC_TIME_ON_1024US (6u << 18) 267 #define VME2_DMAC_TIME_ON_DONE (7u << 18) 268 #define VME2_DMAC_TIME_OFF_MASK (0x00e00000u) 269 #define VME2_DMAC_TIME_OFF_0US (0u << 21) 270 #define VME2_DMAC_TIME_OFF_16US (1u << 21) 271 #define VME2_DMAC_TIME_OFF_32US (2u << 21) 272 #define VME2_DMAC_TIME_OFF_64US (3u << 21) 273 #define VME2_DMAC_TIME_OFF_128US (4u << 21) 274 #define VME2_DMAC_TIME_OFF_256US (5u << 21) 275 #define VME2_DMAC_TIME_OFF_512US (6u << 21) 276 #define VME2_DMAC_TIME_OFF_1024US (7u << 21) 277 #define VME2_VME_GLOBAL_TO_MASK (0x00030000u) 278 #define VME2_VME_GLOBAL_TO_8US (0u << 16) 279 #define VME2_VME_GLOBAL_TO_16US (1u << 16) 280 #define VME2_VME_GLOBAL_TO_256US (2u << 16) 281 #define VME2_VME_GLOBAL_TO_DISABLE (3u << 16) 282 283 /* 284 * VME Access, Local Bus and Watchdog Time-out Control register 285 */ 286 #define VME2LCSR_VME_ACCESS_TIMEOUT 0x4c 287 #define VME2_VME_ACCESS_TIMEOUT_MASK (0x0000c000u) 288 #define VME2_VME_ACCESS_TIMEOUT_64US (0u << 14) 289 #define VME2_VME_ACCESS_TIMEOUT_1MS (1u << 14) 290 #define VME2_VME_ACCESS_TIMEOUT_32MS (2u << 14) 291 #define VME2_VME_ACCESS_TIMEOUT_DISABLE (3u << 14) 292 293 #define VME2LCSR_LOCAL_BUS_TIMEOUT 0x4c 294 #define VME2_LOCAL_BUS_TIMEOUT_MASK (0x00003000u) 295 #define VME2_LOCAL_BUS_TIMEOUT_64US (0u << 12) 296 #define VME2_LOCAL_BUS_TIMEOUT_1MS (1u << 12) 297 #define VME2_LOCAL_BUS_TIMEOUT_32MS (2u << 12) 298 #define VME2_LOCAL_BUS_TIMEOUT_DISABLE (3u << 12) 299 300 #define VME2LCSR_WATCHDOG_TIMEOUT 0x4c 301 #define VME2_WATCHDOG_TIMEOUT_MASK (0x00000f00u) 302 #define VME2_WATCHDOG_TIMEOUT_512US (0u << 8) 303 #define VME2_WATCHDOG_TIMEOUT_1MS (1u << 8) 304 #define VME2_WATCHDOG_TIMEOUT_2MS (2u << 8) 305 #define VME2_WATCHDOG_TIMEOUT_4MS (3u << 8) 306 #define VME2_WATCHDOG_TIMEOUT_8MS (4u << 8) 307 #define VME2_WATCHDOG_TIMEOUT_16MS (5u << 8) 308 #define VME2_WATCHDOG_TIMEOUT_32MS (6u << 8) 309 #define VME2_WATCHDOG_TIMEOUT_64MS (7u << 8) 310 #define VME2_WATCHDOG_TIMEOUT_128MS (8u << 8) 311 #define VME2_WATCHDOG_TIMEOUT_256MS (9u << 8) 312 #define VME2_WATCHDOG_TIMEOUT_512MS (10u << 8) 313 #define VME2_WATCHDOG_TIMEOUT_1S (11u << 8) 314 #define VME2_WATCHDOG_TIMEOUT_4S (12u << 8) 315 #define VME2_WATCHDOG_TIMEOUT_16S (13u << 8) 316 #define VME2_WATCHDOG_TIMEOUT_32S (14u << 8) 317 #define VME2_WATCHDOG_TIMEOUT_64S (15u << 8) 318 319 /* 320 * Prescaler Control register 321 */ 322 #define VME2LCSR_PRESCALER_CONTROL 0x4c 323 #define VME2_PRESCALER_MASK (0x000000ffu) 324 #define VME2_PRESCALER_SHIFT 0 325 #define VME2_PRESCALER_CTRL(c) (256 - (c)) 326 327 /* 328 * Tick Timer registers 329 */ 330 #define VME2LCSR_TIMER_COMPARE(x) (0x50 + ((x) * 8)) 331 #define VME2LCSR_TIMER_COUNTER(x) (0x54 + ((x) * 8)) 332 333 334 /* 335 * Board Control register 336 */ 337 #define VME2LCSR_BOARD_CONTROL 0x60 338 #define VME2_BOARD_CONTROL_RSWE (1u << 24) 339 #define VME2_BOARD_CONTROL_BDFLO (1u << 25) 340 #define VME2_BOARD_CONTROL_CPURS (1u << 26) 341 #define VME2_BOARD_CONTROL_PURS (1u << 27) 342 #define VME2_BOARD_CONTROL_BRFLI (1u << 28) 343 #define VME2_BOARD_CONTROL_SFFL (1u << 29) 344 #define VME2_BOARD_CONTROL_SCON (1u << 30) 345 346 /* 347 * Watchdog Timer Control register 348 */ 349 #define VME2LCSR_WATCHDOG_TIMER_CONTROL 0x60 350 #define VME2_WATCHDOG_TCONTROL_WDEN (1u << 16) 351 #define VME2_WATCHDOG_TCONTTRL_WDRSE (1u << 17) 352 #define VME2_WATCHDOG_TCONTTRL_WDSL (1u << 18) 353 #define VME2_WATCHDOG_TCONTTRL_WDBFE (1u << 19) 354 #define VME2_WATCHDOG_TCONTTRL_WDTO (1u << 20) 355 #define VME2_WATCHDOG_TCONTTRL_WDCC (1u << 21) 356 #define VME2_WATCHDOG_TCONTTRL_WDCS (1u << 22) 357 #define VME2_WATCHDOG_TCONTTRL_SRST (1u << 23) 358 359 /* 360 * Tick Timer Control registers 361 */ 362 #define VME2LCSR_TIMER_CONTROL 0x60 363 #define VME2_TIMER_CONTROL_EN(x) (1u << (0 + ((x) * 8))) 364 #define VME2_TIMER_CONTROL_COC(x) (1u << (1 + ((x) * 8))) 365 #define VME2_TIMER_CONTROL_COF(x) (1u << (2 + ((x) * 8))) 366 #define VME2_TIMER_CONTROL_OVF_SHIFT(x) (4 + ((x) * 8)) 367 #define VME2_TIMER_CONTROL_OVF_MASK(x) (0x000000f0u << (4 + ((x) * 8))) 368 369 /* 370 * Prescaler Counter register 371 */ 372 #define VME2LCSR_PRESCALER_COUNTER 0x64 373 374 /* 375 * Local Bus Interrupter Status/Enable/Clear registers 376 */ 377 #define VME2LCSR_LOCAL_INTERRUPT_STATUS 0x68 378 #define VME2LCSR_LOCAL_INTERRUPT_ENABLE 0x6c 379 #define VME2LCSR_LOCAL_INTERRUPT_CLEAR 0x74 380 #define VME2_LOCAL_INTERRUPT(x) (1u << (x)) 381 #define VME2_LOCAL_INTERRUPT_VME(x) (1u << ((x) - 1)) 382 #define VME2_LOCAL_INTERRUPT_SWINT(x) (1u << ((x) + 8)) 383 #define VME2_LOCAL_INTERRUPT_LM(x) (1u << ((x) + 16)) 384 #define VME2_LOCAL_INTERRUPT_SIG(x) (1u << ((x) + 18)) 385 #define VME2_LOCAL_INTERRUPT_DMAC (1u << 22) 386 #define VME2_LOCAL_INTERRUPT_VIA (1u << 23) 387 #define VME2_LOCAL_INTERRUPT_TIC(x) (1u << ((x) + 24)) 388 #define VME2_LOCAL_INTERRUPT_VI1E (1u << 26) 389 #define VME2_LOCAL_INTERRUPT_PE (1u << 27) 390 #define VME2_LOCAL_INTERRUPT_MWP (1u << 28) 391 #define VME2_LOCAL_INTERRUPT_SYSF (1u << 29) 392 #define VME2_LOCAL_INTERRUPT_ABORT (1u << 30) 393 #define VME2_LOCAL_INTERRUPT_ACFAIL (1u << 31) 394 #define VME2_LOCAL_INTERRUPT_CLEAR_ALL (0xffffff00u) 395 396 /* 397 * Software Interrupt Set register 398 */ 399 #define VME2LCSR_SOFTINT_SET 0x70 400 #define VME2_SOFTINT_SET(x) (1u << ((x) + 8)) 401 402 /* 403 * Interrupt Level registers 404 */ 405 #define VME2LCSR_INTERRUPT_LEVEL_BASE 0x78 406 #define VME2_NUM_IL_REGS 4 407 #define VME2_ILOFFSET_FROM_VECTOR(v) (((((VME2_NUM_IL_REGS*8)-1)-(v))/8)<<2) 408 #define VME2_ILSHIFT_FROM_VECTOR(v) (((v) & 7) * 4) 409 #define VME2_INTERRUPT_LEVEL_MASK (0x0fu) 410 411 /* 412 * Vector Base register 413 */ 414 #define VME2LCSR_VECTOR_BASE 0x88 415 #define VME2_VECTOR_BASE_MASK (0xff000000u) 416 #define VME2_VECTOR_BASE_REG_VALUE (0x76000000u) 417 #define VME2_VECTOR_BASE (0x60u) 418 #define VME2_VECTOR_LOCAL_OFFSET (0x08u) 419 #define VME2_VECTOR_LOCAL_MIN (VME2_VECTOR_BASE + 0x08u) 420 #define VME2_VECTOR_LOCAL_MAX (VME2_VECTOR_BASE + 0x1fu) 421 #define VME2_VEC_SOFT0 (VME2_VECTOR_BASE + 0x08u) 422 #define VME2_VEC_SOFT1 (VME2_VECTOR_BASE + 0x09u) 423 #define VME2_VEC_SOFT2 (VME2_VECTOR_BASE + 0x0au) 424 #define VME2_VEC_SOFT3 (VME2_VECTOR_BASE + 0x0bu) 425 #define VME2_VEC_SOFT4 (VME2_VECTOR_BASE + 0x0cu) 426 #define VME2_VEC_SOFT5 (VME2_VECTOR_BASE + 0x0du) 427 #define VME2_VEC_SOFT6 (VME2_VECTOR_BASE + 0x0eu) 428 #define VME2_VEC_SOFT7 (VME2_VECTOR_BASE + 0x0fu) 429 #define VME2_VEC_GCSRLM0 (VME2_VECTOR_BASE + 0x10u) 430 #define VME2_VEC_GCSRLM1 (VME2_VECTOR_BASE + 0x11u) 431 #define VME2_VEC_GCSRSIG0 (VME2_VECTOR_BASE + 0x12u) 432 #define VME2_VEC_GCSRSIG1 (VME2_VECTOR_BASE + 0x13u) 433 #define VME2_VEC_GCSRSIG2 (VME2_VECTOR_BASE + 0x14u) 434 #define VME2_VEC_GCSRSIG3 (VME2_VECTOR_BASE + 0x15u) 435 #define VME2_VEC_DMAC (VME2_VECTOR_BASE + 0x16u) 436 #define VME2_VEC_VIA (VME2_VECTOR_BASE + 0x17u) 437 #define VME2_VEC_TT1 (VME2_VECTOR_BASE + 0x18u) 438 #define VME2_VEC_TT2 (VME2_VECTOR_BASE + 0x19u) 439 #define VME2_VEC_IRQ1 (VME2_VECTOR_BASE + 0x1au) 440 #define VME2_VEC_PARITY_ERROR (VME2_VECTOR_BASE + 0x1bu) 441 #define VME2_VEC_MWP_ERROR (VME2_VECTOR_BASE + 0x1cu) 442 #define VME2_VEC_SYSFAIL (VME2_VECTOR_BASE + 0x1du) 443 #define VME2_VEC_ABORT (VME2_VECTOR_BASE + 0x1eu) 444 #define VME2_VEC_ACFAIL (VME2_VECTOR_BASE + 0x1fu) 445 446 /* 447 * I/O Control register #1 448 */ 449 #define VME2LCSR_GPIO_DIRECTION 0x88 450 #define VME2_GPIO_DIRECTION_OUT(x) (1u << ((x) + 16)) 451 452 /* 453 * Misc. Status register 454 */ 455 #define VME2LCSR_MISC_STATUS 0x88 456 #define VME2_MISC_STATUS_ABRTL (1u << 20) 457 #define VME2_MISC_STATUS_ACFL (1u << 21) 458 #define VME2_MISC_STATUS_SYSFL (1u << 22) 459 #define VME2_MISC_STATUS_MIEN (1u << 23) 460 461 /* 462 * GPIO Status register 463 */ 464 #define VME2LCSR_GPIO_STATUS 0x88 465 #define VME2_GPIO_STATUS(x) (1u << ((x) + 8)) 466 467 /* 468 * GPIO Control register #2 469 */ 470 #define VME2LCSR_GPIO_CONTROL 0x88 471 #define VME2_GPIO_CONTROL_SET(x) (1u << ((x) + 12)) 472 473 /* 474 * General purpose input registers 475 */ 476 #define VME2LCSR_GP_INPUTS 0x88 477 #define VME2_GP_INPUT(x) (1u << (x)) 478 479 /* 480 * Miscellaneous Control register 481 */ 482 #define VME2LCSR_MISC_CONTROL 0x8c 483 #define VME2_MISC_CONTROL_DISBGN (1u << 0) 484 #define VME2_MISC_CONTROL_ENINT (1u << 1) 485 #define VME2_MISC_CONTROL_DISBSYT (1u << 2) 486 #define VME2_MISC_CONTROL_NOELBBSY (1u << 3) 487 #define VME2_MISC_CONTROL_DISMST (1u << 4) 488 #define VME2_MISC_CONTROL_DISSRAM (1u << 5) 489 #define VME2_MISC_CONTROL_REVEROM (1u << 6) 490 #define VME2_MISC_CONTROL_MPIRQEN (1u << 7) 491 492 #define VME2LCSR_SIZE 0x90 493 494 495 #define vme2_lcsr_read(s,r) \ 496 bus_space_read_4((s)->sc_mvmebus.sc_bust, (s)->sc_lcrh, (r)) 497 #define vme2_lcsr_write(s,r,v) \ 498 bus_space_write_4((s)->sc_mvmebus.sc_bust, (s)->sc_lcrh, (r), (v)) 499 500 501 /* 502 * Locations of the three fixed VMEbus I/O ranges 503 */ 504 #define VME2_IO0_LOCAL_START (0xffff0000u) 505 #define VME2_IO0_MASK (0x0000ffffu) 506 #define VME2_IO0_VME_START (0x00000000u) 507 #define VME2_IO0_VME_END (0x0000ffffu) 508 509 #define VME2_IO1_LOCAL_START (0xf0000000u) 510 #define VME2_IO1_MASK (0x00ffffffu) 511 #define VME2_IO1_VME_START (0x00000000u) 512 #define VME2_IO1_VME_END (0x00ffffffu) 513 514 #define VME2_IO2_LOCAL_START (0x00000000u) 515 #define VME2_IO2_MASK (0xffffffffu) 516 #define VME2_IO2_VME_START (0xf1000000u) /* Maybe starts@ 0x0? */ 517 #define VME2_IO2_VME_END (0xff7fffffu) 518 519 #endif /* _MVME_VME_TWOREG_H */ 520
Indexes created Mon Sep 22 21:09:42 GMT 2025