1 /* $NetBSD: stm32mp1-clks.h,v 1.1.1.4 2021/11/07 16:49:57 jmcneill Exp $ */ 2 3 /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */ 4 /* 5 * Copyright (C) STMicroelectronics 2018 - All Rights Reserved 6 * Author: Gabriel Fernandez <gabriel.fernandez (at) st.com> for STMicroelectronics. 7 */ 8 9 #ifndef _DT_BINDINGS_STM32MP1_CLKS_H_ 10 #define _DT_BINDINGS_STM32MP1_CLKS_H_ 11 12 /* OSCILLATOR clocks */ 13 #define CK_HSE 0 14 #define CK_CSI 1 15 #define CK_LSI 2 16 #define CK_LSE 3 17 #define CK_HSI 4 18 #define CK_HSE_DIV2 5 19 20 /* Bus clocks */ 21 #define TIM2 6 22 #define TIM3 7 23 #define TIM4 8 24 #define TIM5 9 25 #define TIM6 10 26 #define TIM7 11 27 #define TIM12 12 28 #define TIM13 13 29 #define TIM14 14 30 #define LPTIM1 15 31 #define SPI2 16 32 #define SPI3 17 33 #define USART2 18 34 #define USART3 19 35 #define UART4 20 36 #define UART5 21 37 #define UART7 22 38 #define UART8 23 39 #define I2C1 24 40 #define I2C2 25 41 #define I2C3 26 42 #define I2C5 27 43 #define SPDIF 28 44 #define CEC 29 45 #define DAC12 30 46 #define MDIO 31 47 #define TIM1 32 48 #define TIM8 33 49 #define TIM15 34 50 #define TIM16 35 51 #define TIM17 36 52 #define SPI1 37 53 #define SPI4 38 54 #define SPI5 39 55 #define USART6 40 56 #define SAI1 41 57 #define SAI2 42 58 #define SAI3 43 59 #define DFSDM 44 60 #define FDCAN 45 61 #define LPTIM2 46 62 #define LPTIM3 47 63 #define LPTIM4 48 64 #define LPTIM5 49 65 #define SAI4 50 66 #define SYSCFG 51 67 #define VREF 52 68 #define TMPSENS 53 69 #define PMBCTRL 54 70 #define HDP 55 71 #define LTDC 56 72 #define DSI 57 73 #define IWDG2 58 74 #define USBPHY 59 75 #define STGENRO 60 76 #define SPI6 61 77 #define I2C4 62 78 #define I2C6 63 79 #define USART1 64 80 #define RTCAPB 65 81 #define TZC1 66 82 #define TZPC 67 83 #define IWDG1 68 84 #define BSEC 69 85 #define STGEN 70 86 #define DMA1 71 87 #define DMA2 72 88 #define DMAMUX 73 89 #define ADC12 74 90 #define USBO 75 91 #define SDMMC3 76 92 #define DCMI 77 93 #define CRYP2 78 94 #define HASH2 79 95 #define RNG2 80 96 #define CRC2 81 97 #define HSEM 82 98 #define IPCC 83 99 #define GPIOA 84 100 #define GPIOB 85 101 #define GPIOC 86 102 #define GPIOD 87 103 #define GPIOE 88 104 #define GPIOF 89 105 #define GPIOG 90 106 #define GPIOH 91 107 #define GPIOI 92 108 #define GPIOJ 93 109 #define GPIOK 94 110 #define GPIOZ 95 111 #define CRYP1 96 112 #define HASH1 97 113 #define RNG1 98 114 #define BKPSRAM 99 115 #define MDMA 100 116 #define GPU 101 117 #define ETHCK 102 118 #define ETHTX 103 119 #define ETHRX 104 120 #define ETHMAC 105 121 #define FMC 106 122 #define QSPI 107 123 #define SDMMC1 108 124 #define SDMMC2 109 125 #define CRC1 110 126 #define USBH 111 127 #define ETHSTP 112 128 #define TZC2 113 129 130 /* Kernel clocks */ 131 #define SDMMC1_K 118 132 #define SDMMC2_K 119 133 #define SDMMC3_K 120 134 #define FMC_K 121 135 #define QSPI_K 122 136 #define ETHCK_K 123 137 #define RNG1_K 124 138 #define RNG2_K 125 139 #define GPU_K 126 140 #define USBPHY_K 127 141 #define STGEN_K 128 142 #define SPDIF_K 129 143 #define SPI1_K 130 144 #define SPI2_K 131 145 #define SPI3_K 132 146 #define SPI4_K 133 147 #define SPI5_K 134 148 #define SPI6_K 135 149 #define CEC_K 136 150 #define I2C1_K 137 151 #define I2C2_K 138 152 #define I2C3_K 139 153 #define I2C4_K 140 154 #define I2C5_K 141 155 #define I2C6_K 142 156 #define LPTIM1_K 143 157 #define LPTIM2_K 144 158 #define LPTIM3_K 145 159 #define LPTIM4_K 146 160 #define LPTIM5_K 147 161 #define USART1_K 148 162 #define USART2_K 149 163 #define USART3_K 150 164 #define UART4_K 151 165 #define UART5_K 152 166 #define USART6_K 153 167 #define UART7_K 154 168 #define UART8_K 155 169 #define DFSDM_K 156 170 #define FDCAN_K 157 171 #define SAI1_K 158 172 #define SAI2_K 159 173 #define SAI3_K 160 174 #define SAI4_K 161 175 #define ADC12_K 162 176 #define DSI_K 163 177 #define DSI_PX 164 178 #define ADFSDM_K 165 179 #define USBO_K 166 180 #define LTDC_PX 167 181 #define DAC12_K 168 182 #define ETHPTP_K 169 183 184 /* PLL */ 185 #define PLL1 176 186 #define PLL2 177 187 #define PLL3 178 188 #define PLL4 179 189 190 /* ODF */ 191 #define PLL1_P 180 192 #define PLL1_Q 181 193 #define PLL1_R 182 194 #define PLL2_P 183 195 #define PLL2_Q 184 196 #define PLL2_R 185 197 #define PLL3_P 186 198 #define PLL3_Q 187 199 #define PLL3_R 188 200 #define PLL4_P 189 201 #define PLL4_Q 190 202 #define PLL4_R 191 203 204 /* AUX */ 205 #define RTC 192 206 207 /* MCLK */ 208 #define CK_PER 193 209 #define CK_MPU 194 210 #define CK_AXI 195 211 #define CK_MCU 196 212 213 /* Time base */ 214 #define TIM2_K 197 215 #define TIM3_K 198 216 #define TIM4_K 199 217 #define TIM5_K 200 218 #define TIM6_K 201 219 #define TIM7_K 202 220 #define TIM12_K 203 221 #define TIM13_K 204 222 #define TIM14_K 205 223 #define TIM1_K 206 224 #define TIM8_K 207 225 #define TIM15_K 208 226 #define TIM16_K 209 227 #define TIM17_K 210 228 229 /* MCO clocks */ 230 #define CK_MCO1 211 231 #define CK_MCO2 212 232 233 /* TRACE & DEBUG clocks */ 234 #define CK_DBG 214 235 #define CK_TRACE 215 236 237 /* DDR */ 238 #define DDRC1 220 239 #define DDRC1LP 221 240 #define DDRC2 222 241 #define DDRC2LP 223 242 #define DDRPHYC 224 243 #define DDRPHYCLP 225 244 #define DDRCAPB 226 245 #define DDRCAPBLP 227 246 #define AXIDCG 228 247 #define DDRPHYCAPB 229 248 #define DDRPHYCAPBLP 230 249 #define DDRPERFM 231 250 251 #define STM32MP1_LAST_CLK 232 252 253 /* SCMI clock identifiers */ 254 #define CK_SCMI0_HSE 0 255 #define CK_SCMI0_HSI 1 256 #define CK_SCMI0_CSI 2 257 #define CK_SCMI0_LSE 3 258 #define CK_SCMI0_LSI 4 259 #define CK_SCMI0_PLL2_Q 5 260 #define CK_SCMI0_PLL2_R 6 261 #define CK_SCMI0_MPU 7 262 #define CK_SCMI0_AXI 8 263 #define CK_SCMI0_BSEC 9 264 #define CK_SCMI0_CRYP1 10 265 #define CK_SCMI0_GPIOZ 11 266 #define CK_SCMI0_HASH1 12 267 #define CK_SCMI0_I2C4 13 268 #define CK_SCMI0_I2C6 14 269 #define CK_SCMI0_IWDG1 15 270 #define CK_SCMI0_RNG1 16 271 #define CK_SCMI0_RTC 17 272 #define CK_SCMI0_RTCAPB 18 273 #define CK_SCMI0_SPI6 19 274 #define CK_SCMI0_USART1 20 275 276 #define CK_SCMI1_PLL3_Q 0 277 #define CK_SCMI1_PLL3_R 1 278 #define CK_SCMI1_MCU 2 279 280 #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ 281
Indexes created Sat Sep 20 22:09:52 GMT 2025