1 /* $NetBSD: veritefb_ucode.h,v 1.1 2026/07/11 15:18:21 rkujawa Exp $ */ 2 3 /* 4 * Copyright (c) 2026 The NetBSD Foundation, Inc. 5 * All rights reserved. 6 * 7 * This code is derived from software contributed to The NetBSD Foundation 8 * by Radoslaw Kujawa. 9 * 10 * Redistribution and use in source and binary forms, with or without 11 * modification, are permitted provided that the following conditions 12 * are met: 13 * 1. Redistributions of source code must retain the above copyright 14 * notice, this list of conditions and the following disclaimer. 15 * 2. Redistributions in binary form must reproduce the above copyright 16 * notice, this list of conditions and the following disclaimer in the 17 * documentation and/or other materials provided with the distribution. 18 * 19 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 20 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 21 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 22 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 23 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 24 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 25 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 26 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 28 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 29 */ 30 31 /* 32 * Rendition Verite RISC and 2D microcode interface definitions. 33 * 34 * Command numbers are taken from the dispatch table extracted from the 35 * V2x00 2D microcode blob itself (v20002d.uc, dispatch table at 0x5140). 36 */ 37 38 #ifndef VERITEFB_UCODE_H 39 #define VERITEFB_UCODE_H 40 41 /* 42 * VRAM layout: the first VFB_MC_SIZE bytes are reserved for microcode, 43 * the framebuffer starts right after... 44 * 45 * The context-switch monitor (csucode) lives at VFB_CSUCODE_BASE. 46 */ 47 #define VFB_MC_SIZE 0x10000 48 #define VFB_CSUCODE_BASE 0x800 49 #define VFB_CSUCODE_SEM0 0x7f8 50 #define VFB_CSUCODE_SEM1 0x7fc 51 52 /* csucode monitor commands (first FIFO word after starting the monitor) */ 53 #define VFB_CSUCODE_INIT 0 /* a1=ctx store area, a2, entry */ 54 #define VFB_CSUCODE_SYNC 2 /* wait for pixel engine idle */ 55 56 /* 57 * Host->RISC commands: 32-bit words into the input FIFO, 58 * command index in bits 15:0, first parameter in bits 31:16. 59 */ 60 #define VFB_CMDW(param, cmd) (((uint32_t)(uint16_t)(param) << 16) | \ 61 (uint16_t)(cmd)) 62 #define VFB_P2(x, y) VFB_CMDW(x, y) 63 64 #define VCMD_FILLRECTSOLID 1 /* prefer the ROP variant */ 65 #define VCMD_PIXENGSYNC 8 /* -> 0xffffffff in output FIFO */ 66 #define VCMD_GETPIXEL 9 /* P2(x,y) -> pixel in output FIFO */ 67 #define VCMD_SETSCREENINFO 10 68 #define VCMD_SCREENBLT 12 69 #define VCMD_MONOSOURCEBLT 22 70 #define VCMD_SETUP 32 /* 6 words total */ 71 #define VCMD_SETPALETTE 33 72 #define VCMD_SETPIXEL 34 73 #define VCMD_DRAWGLYPHS 35 74 #define VCMD_SETCLIPPING 36 75 #define VCMD_FILLRECTSOLIDROP 41 76 77 #define VFB_SYNC_TOKEN 0xffffffffU 78 79 /* 2D blob layout facts, for RISC program counter classification. */ 80 #define VFB_UC_BASE 0x1000 /* link base; dispatch loop here */ 81 #define VFB_UC_DISPATCH_END 0x101c /* end of the dispatch idle loop */ 82 #define VFB_UC_TRAP 0x1050 /* invalid-command self-branch */ 83 #define VFB_UC_TRAP_END 0x1058 /* including the delay slot */ 84 #define VFB_UC_END 0x5000 /* end of the command handlers */ 85 #define VFB_RISC_ROM_BASE 0xfffe0000 /* boot ROM, RISC view */ 86 87 /* DstMode for 2D: ALUMode in bits 3:0, other bits zero. */ 88 #define VFB_ROP_COPY 0xc 89 90 /* 91 * RISC register file indices and instruction encodings, for driving the 92 * processor through the STATEINDEX/STATEDATA debug port. 93 */ 94 #define VRISC_FLAG 37 /* flags register */ 95 #define VRISC_SP 252 /* stack pointer / scratch */ 96 #define VRISC_RA 254 /* link / scratch */ 97 #define VRISC_FP 255 /* frame pointer / scratch */ 98 99 #define VRISC_NOP 0x00000000 /* addi zero, zero, 0 */ 100 101 #define VRISC_ADDI_OP 0x00 102 #define VRISC_ADD_OP 0x10 103 #define VRISC_ANDN_OP 0x12 104 #define VRISC_OR_OP 0x15 105 #define VRISC_ADDIFI_OP 0x40 106 #define VRISC_ADDSL8_OP 0x4b 107 #define VRISC_SPRI_OP 0x4f 108 #define VRISC_JMP_OP 0x6c 109 #define VRISC_LB_OP 0x70 110 #define VRISC_LH_OP 0x71 111 #define VRISC_LW_OP 0x72 112 #define VRISC_LI_OP 0x76 113 #define VRISC_LUI_OP 0x77 114 #define VRISC_SB_OP 0x78 115 #define VRISC_SH_OP 0x79 116 #define VRISC_SW_OP 0x7a 117 118 #define VRISC_INT(op, d, s2, s1) \ 119 (((uint32_t)(op) << 24) | ((uint32_t)(d) << 16) | \ 120 ((uint32_t)(s2) << 8) | ((uint32_t)(s1) & 0xff)) 121 #define VRISC_LD(op, d, off8, s1) \ 122 (((uint32_t)(op) << 24) | ((uint32_t)(d) << 16) | \ 123 (((uint32_t)(off8) & 0xff) << 8) | ((uint32_t)(s1))) 124 #define VRISC_ST(op, off8, s2, s1) \ 125 (((uint32_t)(op) << 24) | (((uint32_t)(off8) & 0xff) << 16) | \ 126 ((uint32_t)(s2) << 8) | ((uint32_t)(s1))) 127 #define VRISC_LI(op, d, imm16) \ 128 (((uint32_t)(op) << 24) | ((uint32_t)(d) << 16) | \ 129 ((uint32_t)(imm16) & 0xffff)) 130 #define VRISC_JMP(addr24) \ 131 (((uint32_t)VRISC_JMP_OP << 24) | ((uint32_t)(addr24))) 132 133 /* Instruction cache */ 134 #define VRISC_ICACHESIZE 2048 135 #define VRISC_ICACHELINESIZE 32 136 #define VRISC_ICACHE_ONOFF_MASK (((uint32_t)1 << 17) | (1 << 3)) 137 138 /* 139 * Context-switch monitor microcode ("csucode") 140 */ 141 static const uint32_t veritefb_csucode[] = { 142 0x10802100, 0x5d808000, 0x4c808002, 0x6b820000, 143 0x00818002, 0x45818103, 0x10828281, 0x6f000082, 144 0x00000000, 0x62000500, 0x00000000, 0x62000300, 145 0x00000000, 0x62000800, 0x00000000, 0x10812100, 146 0x10822100, 0x10c02100, 0x6ffe00c0, 0x00000000, 147 0x62ffeb00, 0x00000000, 0x04812502, 0x61fffe81, 148 0x00000000, 0x10218000, 0x00000000, 0x00000000, 149 0x62ffe300, 0x00000000, 150 }; 151 152 #endif /* VERITEFB_UCODE_H */ 153
Indexes created Sun Jul 12 00:26:10 UTC 2026